X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/8985684ba1f0b0006387e6a45ec44f684bce0d36..d452afd57d3469271a8532a9271ed7c14a53a427:/dhwk/source/top.vhd?ds=sidebyside

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 971b0c4..a148b38 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -32,6 +32,8 @@ entity dhwk is
              PCI_SERRn : Out   std_logic;
              PCI_STOPn : Out   std_logic;
              PCI_TRDYn : Out   std_logic;
+	     PCI_REQn : Out std_logic;
+	     PCI_GNTn : In std_logic;
 --             SERIAL_OUT : Out   std_logic;
 --             SPC_RDY_OUT : Out   std_logic;
              TB_IDSEL : Out   std_logic;
@@ -90,7 +92,12 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_IN : std_logic;
    signal SERIAL_OUT : std_logic;
    signal SPC_RDY_OUT : std_logic;
-   signal watch : std_logic;
+   signal watch_PCI_INTAn : std_logic;
+   signal watch_PCI_TRDYn : std_logic;
+   signal watch_PCI_STOPn : std_logic;
+   signal watch_PCI_SERRn : std_logic;
+   signal watch_PCI_PERRn : std_logic;
+   signal watch_PCI_REQn : std_logic;
    signal control0       : std_logic_vector(35 downto 0);
    signal data       : std_logic_vector(95 downto 0);
    signal trig0      : std_logic_vector(31 downto 0);
@@ -209,7 +216,7 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );
    end component;
 
-component fifo_generator_v3_2
+component dhwk_fifo
         port (
         clk: IN std_logic;
         din: IN std_logic_VECTOR(7 downto 0);
@@ -243,16 +250,37 @@ end component;
 
 
 begin
+	watch_PCI_REQn <= '1';
 	SERIAL_IN <= SERIAL_OUT;
 	SPC_RDY_IN <= SPC_RDY_OUT;
-	LED_2 <= TAST_RESn;
-	LED_3 <= TAST_SETn;
-	LED_4 <= '0';
-	LED_5 <= not watch;
-	PCI_INTAn <= watch;
-	trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
-	data(0) <= watch;
-	
+	LED_2 <= not PCI_RSTn;
+	LED_3 <= PCI_IDSEL;
+	LED_4 <= not PCI_FRAMEn;
+	LED_5 <= not watch_PCI_INTAn;
+	PCI_INTAn <= watch_PCI_INTAn;
+	trig0(31 downto 0) <= (
+		0 => watch_PCI_INTAn,
+		1 => R_FIFO_READn,
+		2 => R_FIFO_WRITEn,
+		3 => S_FIFO_READn,
+		4 => S_FIFO_WRITEn, 
+		5 => PCI_RSTn,
+		16 => PCI_AD(0),
+		17 => PCI_AD(1),
+		18 => PCI_AD(2),
+		19 => PCI_AD(3),
+		20 => PCI_AD(4),
+		21 => PCI_AD(5),
+		22 => PCI_AD(6),
+		23 => PCI_AD(7),
+		27 => PCI_FRAMEn,
+		28 => PCI_CBEn(0),
+		29 => PCI_CBEn(1),
+		30 => PCI_CBEn(2),
+		31 => PCI_CBEn(3),
+		others => '0');
+
+	data(0) <= watch_PCI_INTAn;
 	data(1) <= R_EFn;
 	data(2) <= R_HFn;
 	data(3) <= R_FFn;
@@ -275,6 +303,20 @@ begin
 	data(34 downto 27) <= R_FIFO_Q_OUT;
 	data(66 downto 35) <= PCI_AD(31 downto 0);
 	data(70 downto 67) <= PCI_CBEn(3 downto 0);
+	data(71) <= PCI_FRAMEn;
+	data(72) <= PCI_IDSEL;
+	PCI_TRDYn <= watch_PCI_TRDYn;
+	data(73) <= watch_PCI_TRDYn;
+	data(74) <= PCI_IRDYn;
+	PCI_STOPn <= watch_PCI_STOPn;
+	data(75) <= watch_PCI_STOPn;
+	PCI_SERRn <= watch_PCI_SERRn;
+	data(76) <= watch_PCI_SERRn;
+	PCI_PERRn <= watch_PCI_PERRn;
+	data(77) <= watch_PCI_PERRn;
+	PCI_REQn <= watch_PCI_REQn;
+	data(78) <= watch_PCI_REQn;
+	data(79) <= PCI_GNTn;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -295,7 +337,7 @@ begin
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
-                 INTAn=>INTAn, PCI_INTAn=>watch);
+                 INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);
    I14 : FIFO_CONTROL
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
@@ -331,9 +373,9 @@ begin
                  PCI_PAR=>PCI_PAR,
                  AD_REG(31 downto 0)=>AD_REG(31 downto 0),
                  DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
-                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
-                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
-                 PCI_TRDYn=>PCI_TRDYn,
+                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,
+                 PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,
+                 PCI_TRDYn=>watch_PCI_TRDYn,
                  READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
                  READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
                  READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
@@ -344,7 +386,7 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
                  WRITE_XX7_6=>WRITE_XX7_6 );
 
-receive_fifo : fifo_generator_v3_2
+receive_fifo : dhwk_fifo
                 port map (
                         clk => PCI_CLOCK,
                         din => R_FIFO_D_IN,
@@ -356,7 +398,7 @@ receive_fifo : fifo_generator_v3_2
                         full => R_FFn,
                         prog_full => R_HFn);
 
-send_fifo : fifo_generator_v3_2
+send_fifo : dhwk_fifo
                 port map (
                         clk => PCI_CLOCK,
                         din => S_FIFO_D_IN,