X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/bba7a6d51635a1cb7d31bdfc03b1a66ee9df336b..1d175e4f030e4cee19ec6df3b39bfad3bf64863c:/dhwk/source/top.vhd?ds=inline

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index a79c470..4becb68 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -91,6 +91,9 @@ architecture SCHEMATIC of dhwk is
    signal SERIAL_OUT : std_logic;
    signal SPC_RDY_OUT : std_logic;
    signal watch : std_logic;
+   signal control0       : std_logic_vector(35 downto 0);
+   signal data       : std_logic_vector(35 downto 0);
+   signal trig0      : std_logic_vector(7 downto 0);
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -221,6 +224,24 @@ component fifo_generator_v3_2
         prog_full: OUT std_logic);
 end component;
 
+component icon
+port
+	(
+	 control0    :   out std_logic_vector(35 downto 0)
+	);
+end component;
+
+  component ila
+    port
+    (
+      control     : in    std_logic_vector(35 downto 0);
+      clk         : in    std_logic;
+      data        : in    std_logic_vector(35 downto 0);
+      trig0       : in    std_logic_vector(7 downto 0)
+    );
+  end component;
+
+
 begin
 	SERIAL_IN <= SERIAL_OUT;
 	SPC_RDY_IN <= SPC_RDY_OUT;
@@ -229,6 +250,29 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
+	trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
+	data(0) <= watch;
+	
+	data(1) <= R_EFn;
+	data(2) <= R_HFn;
+	data(3) <= R_FFn;
+	data(4) <= R_FIFO_READn;
+	data(5) <= R_FIFO_RESETn;
+	data(6) <= R_FIFO_RTn;
+	data(7) <= R_FIFO_WRITEn;
+	data(8) <= S_EFn;
+	data(9) <= S_HFn;
+	data(10) <= S_FFn;
+	data(11) <= S_FIFO_READn;
+	data(12) <= S_FIFO_RESETn;
+	data(13) <= S_FIFO_RTn;
+	data(14) <= S_FIFO_WRITEn;
+	data(15) <= SERIAL_IN;
+	data(16) <= SPC_RDY_IN;
+	data(17) <= SERIAL_OUT;
+	data(18) <= SPC_RDY_OUT;
+	data(26 downto 19) <= S_FIFO_Q_OUT;
+	data(34 downto 27) <= R_FIFO_Q_OUT;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -321,4 +365,19 @@ send_fifo : fifo_generator_v3_2
                         empty => S_EFn,
                         full => S_FFn,
                         prog_full => S_HFn);
+
+  i_icon : icon
+      port map
+          (
+	        control0    => control0
+	  );
+
+  i_ila : ila
+    port map
+    (
+      control   => control0,
+      clk       => PCI_CLOCK,
+      data      => data,
+      trig0     => trig0
+    );
 end SCHEMATIC;