X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/d452afd57d3469271a8532a9271ed7c14a53a427..f69f908ec2b5edbaaa2885a79f6dbe5011462fef:/dhwk/source/pci/address_register.vhd?ds=sidebyside

diff --git a/dhwk/source/pci/address_register.vhd b/dhwk/source/pci/address_register.vhd
index 11602a9..56c480e 100644
--- a/dhwk/source/pci/address_register.vhd
+++ b/dhwk/source/pci/address_register.vhd
@@ -1,39 +1,39 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: ADDR_REG.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity ADDRESS_REGISTER is
-	port (
-                PCI_CLOCK	:in	std_logic;
-                PCI_RSTn	:in	std_logic;
-                LOAD_ADDR_REG	:in	std_logic;
-                AD_REG		:in	std_logic_vector (31 downto 0);
-                ADDR_REG	:out	std_logic_vector (31 downto 0)
-        );
-end entity ADDRESS_REGISTER;
-
-architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is
-	signal	REG_ADDR	:std_logic_vector (31 downto 0); 
-begin 
-
-	process (PCI_CLOCK, PCI_RSTn) 
-	begin
-		if	PCI_RSTn = '0'	then
-                        REG_ADDR	<= X"00000000";
-
-		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
-			if LOAD_ADDR_REG = '1' then
-                                REG_ADDR	<=	AD_REG;
-			else
-                                REG_ADDR	<=	REG_ADDR;
-			end if;
-		end if;
-	end process;
-
-	ADDR_REG	<=	REG_ADDR;
-
-end architecture ADDR_REGI_DESIGN;
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: ADDR_REG.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ADDRESS_REGISTER is
+	port (
+                PCI_CLOCK	:in	std_logic;
+                PCI_RSTn	:in	std_logic;
+                LOAD_ADDR_REG	:in	std_logic;
+                AD_REG		:in	std_logic_vector (31 downto 0);
+                ADDR_REG	:out	std_logic_vector (31 downto 0)
+        );
+end entity ADDRESS_REGISTER;
+
+architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is
+	signal	REG_ADDR	:std_logic_vector (31 downto 0); 
+begin 
+
+	process (PCI_CLOCK, PCI_RSTn) 
+	begin
+		if	PCI_RSTn = '0'	then
+                        REG_ADDR	<= X"00000000";
+
+		elsif (rising_edge(PCI_CLOCK)) then
+			if LOAD_ADDR_REG = '1' then
+                                REG_ADDR	<=	AD_REG;
+			else
+                                REG_ADDR	<=	REG_ADDR;
+			end if;
+		end if;
+	end process;
+
+	ADDR_REG	<=	REG_ADDR;
+
+end architecture ADDR_REGI_DESIGN;