X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/ebba63a9f3199fec28ffd25951257b6619feb8bf..0de2df9caee0439ffcd042c82921a4e4753de8c3:/dhwk_old/source/top_dhwk.vhd

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 7c965c1..67fe5aa 100644
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -1,43 +1,8 @@
---+-------------------------------------------------------------------------------------------------+
---|																									|
---|  File:			top.vhd                       		                                   	|
---|																									|
---|  Components:	pci32lite.vhd                                                                   |
---|		            pciwbsequ.vhd           														|
---|		            pcidmux.vhd           															|
---|		            pciregs.vhd           															|
---|		            pcipargen.vhd          															|
---|		            -- Libs --             															|
---|		            ona.vhd		          															|
---|																									|
---|	 Description:	RS1 PCI Demo : (TOP) Main file.						 				        |
---| 				 																				|
---|					                														        |
---|																									|
---+-------------------------------------------------------------------------------------------------+
---|																									|
---|  Revision history :																				|
---|  Date 		  Version	Author	Description														|
---|																									|
---|																									|
---|  To do:																 							|
---|																									|
---+-------------------------------------------------------------------------------------------------+
-
-
---+-----------------------------------------------------------------------------+
---|									LIBRARIES									|
---+-----------------------------------------------------------------------------+
-
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
---+-----------------------------------------------------------------------------+
---|									ENTITY   									|
---+-----------------------------------------------------------------------------+
-
 entity dhwk is
 port (
 
@@ -69,17 +34,9 @@ port (
 end dhwk;
 
 
---+-----------------------------------------------------------------------------+
---|									ARCHITECTURE								|
---+-----------------------------------------------------------------------------+
-
 architecture dhwk_arch of dhwk is
 
 
---+-----------------------------------------------------------------------------+
---|									COMPONENTS									|
---+-----------------------------------------------------------------------------+
-
 component pci32tlite
 port (
 
@@ -131,13 +88,44 @@ port (
 );
 end component;
 
+component generic_fifo_sc_a
+port (
+	clk		: in std_logic;
+	rst		: in std_logic;
+	clr		: in std_logic;
+	din		: in std_logic_vector(7 downto 0);
+	we		: in std_logic;
+	dout		: out std_logic_vector(7 downto 0);
+	re		: in std_logic;
+	full		: out std_logic;
+	full_r		: out std_logic;
+	empty		: out std_logic;
+	empty_r		: out std_logic;
+	full_n		: out std_logic;
+	full_n_r	: out std_logic;
+	empty_n		: out std_logic;
+	empty_n_r	: out std_logic;
+	level		: out std_logic_vector(1 downto 0)
+);
+end component;
+
+component generic_dpram
+port (
+	rclk		: in std_logic;
+	rrst		: in std_logic;
+	rce		: in std_logic;
+	oe		: in std_logic;
+	raddr		: in std_logic_vector(11 downto 0);
+	do		: out std_logic_vector(7 downto 0);
+	wclk		: in std_logic;
+	wrst		: in std_logic;
+	wce		: in std_logic;
+	we		: in std_logic;
+	waddr		: in std_logic_vector(11 downto 0);
+	di		: in std_logic_vector(7 downto 0)
+);
+end component;
 
---+-----------------------------------------------------------------------------+
---|									CONSTANTS  									|
---+-----------------------------------------------------------------------------+
---+-----------------------------------------------------------------------------+
---|									SIGNALS   									|
---+-----------------------------------------------------------------------------+
 
 	signal 	wb_adr :		std_logic_vector(24 downto 1);   
 	signal	wb_dat_out :	std_logic_vector(15 downto 0);
@@ -153,10 +141,6 @@ end component;
 
 begin
 
---+-----------------------------------------+
---|  PCI Target 							|
---+-----------------------------------------+
-
 u_pci: component pci32tlite
 port map(
     	clk33 =>		PCI_CLK,
@@ -187,10 +171,6 @@ port map(
 --		debug_access =>	LED2
 		);
 
---+-----------------------------------------+
---|  WB-7seg             					|
---+-----------------------------------------+
-
 my_heartbeat: component heartbeat
 port map( 
 	clk_i => PCI_CLK,