X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/f026519d99c0b3afb0560431530bb0a5b11e705b..ac5b827129ac002c0b2caa0d822868383c1416f2:/ideboard/source/ide.vhd?ds=sidebyside

diff --git a/ideboard/source/ide.vhd b/ideboard/source/ide.vhd
index 20cc961..3ddc5c1 100644
--- a/ideboard/source/ide.vhd
+++ b/ideboard/source/ide.vhd
@@ -46,10 +46,10 @@ entity ide is
 	   IDE_CHIP_SELECT_3P : out std_logic;
 	   IDE_IRQ : out std_logic;
 	   IDE_ACTIVITY : out std_logic;
-	   FPGA1 : out std_logic;
-	   FPGA2 : out std_logic;
-	   FPGA3 : out std_logic;
-	   FPGA4 : out std_logic;
+	   FPGA1 : in std_logic;
+	   FPGA2 : in std_logic;
+	   FPGA3 : in std_logic;
+	   FPGA4 : in std_logic;
 	   FPGA5 : out std_logic;
 	   FPGA6 : out std_logic;
 	   FPGA7 : out std_logic;
@@ -88,9 +88,9 @@ end ide;
 architecture Behavioral of ide is
 
 begin
-	LED_1 <= '1';
-	LED_2 <= '1';
-	LED_3 <= '1';
-	LED_4 <= '0';
+	LED_1 <= FPGA1;
+	LED_2 <= FPGA2;
+	LED_3 <= FPGA3;
+	LED_4 <= FPGA4;
 end Behavioral;