X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/fe5730c73508bc00a04b1a7a878adf9104f5a11b..11b038c295a0c1c9a2753ad8cdb6da0480ebc1dc:/dhwk_old/source/top_dhwk.vhd

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 83d7a01..13de352 100644
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -128,8 +128,8 @@ port (
 	fifo_data_i	: in std_logic_vector(7 downto 0);
 	fifo_data_o     : out std_logic_vector(7 downto 0);
 
-	fifo_we_out	: out std_logic;
-	fifo_re_out	: out std_logic
+	fifo_we_o	: out std_logic;
+	fifo_re_o	: out std_logic
 );
 end component;
 
@@ -187,7 +187,7 @@ my_generic_fifo: component generic_fifo_sc_a
 port map(
 	clk		=> PCI_CLK,
 	rst		=> PCI_nRES,
---	clr		=>
+	clr		=> '0',
 	din		=> fifo_din,
 	we		=> fifo_we,
 	dout		=> fifo_dout,
@@ -222,8 +222,8 @@ port map(
 	fifo_data_i	 => fifo_dout,
 	fifo_data_o      => fifo_din,
 
-	fifo_we_out	 => fifo_we,
-	fifo_re_out	 => fifo_re
+	fifo_we_o	 => fifo_we,
+	fifo_re_o	 => fifo_re
 );
 
 my_heartbeat: component heartbeat