larger ila

diff --git a/dhwk/ila.arg b/dhwk/ila.arg
index 2d1a3184a154e9502a6d2705ba0af37b7a7704a1..2433cb44a59e9da280306cc162f7035d7774ff14 100644 (file)
--- a/dhwk/ila.arg
+++ b/dhwk/ila.arg
@@ -3,10 +3,10 @@
 #
 -compname=ila
 -outputdirectory=.
 #
 -compname=ila
 -outputdirectory=.

--datadepth=8192
--datawidth=36
+-datadepth=4096
+-datawidth=96

 -numtrigports=1
 -numtrigports=1

--trigportwidth0=8
+-trigportwidth0=32

 -nummatchunits=1
 -mtrigport0=0
 -mtype0=0
 -nummatchunits=1
 -mtrigport0=0
 -mtype0=0

diff --git a/dhwk/source/config_3Ch.vhd b/dhwk/source/config_3Ch.vhd
index 642a4847484efa8fc776e37a03d3134aa078f1ff..5b7ef418585e6c567679f7d29379f0c8784c1bf8 100644 (file)
--- a/dhwk/source/config_3Ch.vhd
+++ b/dhwk/source/config_3Ch.vhd
@@ -27,6 +27,8 @@ architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
        signal          CONF_INT_PIN            :std_logic_vector (15 downto  8);\r
        signal          CONF_INT_LINE           :std_logic_vector ( 7 downto  0);  \r
 \r
        signal          CONF_INT_PIN            :std_logic_vector (15 downto  8);\r
        signal          CONF_INT_LINE           :std_logic_vector ( 7 downto  0);  \r
 \r

+       constant        cmd_conf_write  :std_logic_vector(3 downto 0) := "1011";\r
+\r

 begin \r
 \r
 --*******************************************************************\r
 begin \r
 \r
 --*******************************************************************\r

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 4becb68de5b660595716589d730a2a40835bba91..5258c3aaf49cdaabb34562f88c90113c904914f6 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;\r
    signal watch : std_logic;\r
    signal control0       : std_logic_vector(35 downto 0);\r
    signal SPC_RDY_OUT : std_logic;\r
    signal watch : std_logic;\r
    signal control0       : std_logic_vector(35 downto 0);\r

-   signal data       : std_logic_vector(35 downto 0);\r
-   signal trig0      : std_logic_vector(7 downto 0);\r
+   signal data       : std_logic_vector(95 downto 0);\r
+   signal trig0      : std_logic_vector(31 downto 0);\r

 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r


@@ -236,8 +236,8 @@ end component;
     (\r
       control     : in    std_logic_vector(35 downto 0);\r
       clk         : in    std_logic;\r
     (\r
       control     : in    std_logic_vector(35 downto 0);\r
       clk         : in    std_logic;\r

-      data        : in    std_logic_vector(35 downto 0);\r
-      trig0       : in    std_logic_vector(7 downto 0)\r
+      data        : in    std_logic_vector(95 downto 0);\r
+      trig0       : in    std_logic_vector(31 downto 0)\r

     );\r
   end component;\r
 \r
     );\r
   end component;\r
 \r


@@ -250,7 +250,7 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r

-       trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
+       trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r

        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r
        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r


@@ -273,6 +273,7 @@ begin
        data(18) <= SPC_RDY_OUT;\r
        data(26 downto 19) <= S_FIFO_Q_OUT;\r
        data(34 downto 27) <= R_FIFO_Q_OUT;\r
        data(18) <= SPC_RDY_OUT;\r
        data(26 downto 19) <= S_FIFO_Q_OUT;\r
        data(34 downto 27) <= R_FIFO_Q_OUT;\r

+       data(66 downto 35) <= PCI_AD(31 downto 0);\r

 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r