loopback

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 3036632d887cda9c8b64cf59059f195c65b0dbd8..215b980cd582662ee273aaa65849ed0fbeb3b1f4 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -16,8 +16,8 @@ entity dhwk is
              PCI_IDSEL : In    std_logic;\r
              PCI_IRDYn : In    std_logic;\r
              PCI_RSTn : In    std_logic;\r
              PCI_IDSEL : In    std_logic;\r
              PCI_IRDYn : In    std_logic;\r
              PCI_RSTn : In    std_logic;\r

-             SERIAL_IN : In    std_logic;\r
-             SPC_RDY_IN : In    std_logic;\r
+--             SERIAL_IN : In    std_logic;\r
+--             SPC_RDY_IN : In    std_logic;\r

              TAST_RESn : In    std_logic;\r
              TAST_SETn : In    std_logic;\r
               PCI_AD : InOut std_logic_vector (31 downto 0);\r
              TAST_RESn : In    std_logic;\r
              TAST_SETn : In    std_logic;\r
               PCI_AD : InOut std_logic_vector (31 downto 0);\r


@@ -28,8 +28,8 @@ entity dhwk is
              PCI_SERRn : Out   std_logic;\r
              PCI_STOPn : Out   std_logic;\r
              PCI_TRDYn : Out   std_logic;\r
              PCI_SERRn : Out   std_logic;\r
              PCI_STOPn : Out   std_logic;\r
              PCI_TRDYn : Out   std_logic;\r

-             SERIAL_OUT : Out   std_logic;\r
-             SPC_RDY_OUT : Out   std_logic;\r
+--             SERIAL_OUT : Out   std_logic;\r
+--             SPC_RDY_OUT : Out   std_logic;\r

              TB_IDSEL : Out   std_logic;\r
              TB_nDEVSEL : Out   std_logic;\r
              TB_nINTA : Out   std_logic );\r
              TB_IDSEL : Out   std_logic;\r
              TB_nDEVSEL : Out   std_logic;\r
              TB_nINTA : Out   std_logic );\r


@@ -82,6 +82,10 @@ architecture SCHEMATIC of dhwk is
    signal S_FIFO_RESETn : std_logic;\r
    signal S_FIFO_RTn : std_logic;\r
    signal S_FIFO_WRITEn : std_logic;\r
    signal S_FIFO_RESETn : std_logic;\r
    signal S_FIFO_RTn : std_logic;\r
    signal S_FIFO_WRITEn : std_logic;\r

+   signal SERIAL_IN : std_logic;\r
+   signal SPC_RDY_IN : std_logic;\r
+   signal SERIAL_OUT : std_logic;\r
+   signal SPC_RDY_OUT : std_logic;\r

 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r


@@ -213,6 +217,8 @@ component fifo_generator_v3_2
 end component;\r
 \r
 begin\r
 end component;\r
 \r
 begin\r

+       SERIAL_IN <= SERIAL_OUT;\r
+       SPC_RDY_IN <= SPC_RDY_OUT;\r

 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r