NET "PCI_CBE<1>" LOC = "C10" | IOSTANDARD = PCI33_3 ;
NET "PCI_CBE<2>" LOC = "D13" | IOSTANDARD = PCI33_3 ;
NET "PCI_CBE<3>" LOC = "E13" | IOSTANDARD = PCI33_3 ;
-NET "PCI_CLK" LOC = "A11" | IOSTANDARD = PCI33_3 ;
-#NET "PCI_CLK" LOC = "AA11" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CLK" LOC = "AA11" | IOSTANDARD = PCI33_3 ;
NET "PCI_IDSEL" LOC = "D14" | IOSTANDARD = PCI33_3 ;
NET "PCI_nDEVSEL" LOC = "E12" | IOSTANDARD = PCI33_3 ;
NET "PCI_nFRAME" LOC = "C13" | IOSTANDARD = PCI33_3 ;
begin
process(clk_i, nrst_i)
-variable counter : std_logic_vector(31 downto 0);
+variable counter : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
variable state : std_logic_vector(7 downto 0) := "00000001";
variable direction : std_logic := '0';
begin
if (rising_edge(clk_i)) then
- if nrst_i = '0' then
- counter := (others => '0');
- else
+-- if nrst_i = '0' then
+-- counter := (others => '0');
+-- else
led2_o <= state(0);
led3_o <= state(1);
led4_o <= state(2);
end if;
counter := (others => '0');
end if;
- end if;
+-- end if;
end if;
end process;
end architecture;
--- /dev/null
+############################################################################
+## This system.ucf file is generated by Base System Builder based on the
+## settings in the selected Xilinx Board Definition file. Please add other
+## user constraints to this file based on customer design specifications.
+############################################################################
+
+Net sys_clk_pin LOC=AA11 | IOSTANDARD = LVCMOS33;
+Net sys_rst_pin LOC=AA3 | IOSTANDARD = LVCMOS33 | PULLUP;
+## System level constraints
+Net sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
+Net sys_rst_pin TIG;
+
+## IO Devices constraints
+
+#### Module RS232 constraints
+
+Net fpga_0_RS232_req_to_send_pin LOC=N20;
+Net fpga_0_RS232_req_to_send_pin IOSTANDARD = LVCMOS33;
+Net fpga_0_RS232_RX_pin LOC=Y22;
+Net fpga_0_RS232_RX_pin IOSTANDARD = LVCMOS33;
+Net fpga_0_RS232_TX_pin LOC=R18;
+Net fpga_0_RS232_TX_pin IOSTANDARD = LVCMOS33;
+
+Net RS232foff LOC=T22 | IOSTANDARD = LVCMOS33;
+
+#Net LED_out<0> LOC=AB5 | IOSTANDARD = LVTTL;
+Net LED_out<1> LOC=AA5 | IOSTANDARD = LVTTL;
+Net LED_out<2> LOC=AA4 | IOSTANDARD = LVTTL;
+Net LED_out<3> LOC=AB4 | IOSTANDARD = LVTTL;
+
+Net SEVENSEG_out<12> LOC=AB20 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<11> LOC=AA20 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<10> LOC=V18 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<9> LOC=Y17 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<8> LOC=AB18 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<7> LOC=AA18 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<6> LOC=W18 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<5> LOC=W17 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<4> LOC=AA17 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<3> LOC=U17 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<2> LOC=U16 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<1> LOC=U14 | IOSTANDARD = LVTTL;
+Net SEVENSEG_out<0> LOC=V17 | IOSTANDARD = LVTTL;
+
+Net MEM_FLASH_DQ<0> LOC=AA10 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_DQ<1> LOC=W11 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_DQ<2> LOC=Y11 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_DQ<3> LOC=U11 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_DQ<4> LOC=W13 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_DQ<5> LOC=V13 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_DQ<6> LOC=Y13 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_DQ<7> LOC=W14 | IOSTANDARD = LVCMOS33;
+
+Net MEM_FLASH_ADDR<0> LOC=Y10 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<1> LOC=W10 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<2> LOC=V10 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<3> LOC=W9 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<4> LOC=W8 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<5> LOC=AB8 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<6> LOC=AA8 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<7> LOC=AA9 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<8> LOC=V9 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<9> LOC=AA15 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<10> LOC=U12 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<11> LOC=AB15 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<12> LOC=AB9 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<13> LOC=AB14 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<14> LOC=AA13 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<15> LOC=AB10 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<16> LOC=AB11 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<17> LOC=AB13 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_ADDR<18> LOC=Y12 | IOSTANDARD = LVCMOS33;
+
+Net DBG_FLASH_ADDR<31> LOC=Y1 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<30> LOC=U2 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<29> LOC=U3 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<28> LOC=T1 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<27> LOC=T2 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<26> LOC=M6 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<25> LOC=M5 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<24> LOC=M1 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<23> LOC=M2 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<22> LOC=L5 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<21> LOC=L6 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<20> LOC=K1 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<19> LOC=K2 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<18> LOC=F4 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<17> LOC=E3 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<16> LOC=F2 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<15> LOC=F3 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<14> LOC=E2 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<13> LOC=E1 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<12> LOC=W1 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<11> LOC=W2 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<10> LOC=V5 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<9> LOC=U5 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<8> LOC=V2 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<7> LOC=V1 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<6> LOC=U4 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<5> LOC=T4 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<4> LOC=T5 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<3> LOC=T6 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<2> LOC=M4 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<1> LOC=M3 | IOSTANDARD = LVCMOS33;
+Net DBG_FLASH_ADDR<0> LOC=L3 | IOSTANDARD = LVCMOS33;
+
+Net MEM_FLASH_CE<0> LOC=V14 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_OE<0> LOC=U13 | IOSTANDARD = LVCMOS33;
+Net MEM_FLASH_WE LOC=W12 | IOSTANDARD = LVCMOS33;
--- /dev/null
+setMode -bscan
+setCable -p auto
+identify
+assignfile -p 3 -file implementation/download.bit
+program -p 3
+quit
--- /dev/null
+\1c\84æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Dp\d\`dDv1\84æÄ®Òôtt¦Êè\84ÞÂäÈ@D°ÒØÒÜðD@D\8eÊÜÊäÒÆ@¨ÊÚàØÂèÊD@DbDv-\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D\82¤\86\90\92¨\8a\86¨ª¤\8aD@DæàÂäèÂÜfDv,\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D\88\8a¬\92\86\8a¾¦\92´\8aD@DðÆfæbj``Dv%\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D \82\86\96\82\8e\8aD@DÌÎhjlDv%\84æÄ®ÒôttªàÈÂèÊ\8c \8e\82@D¦ \8a\8a\88\8e¤\82\88\8aD@DZhDv"\84æÄ®Òôtt\82ÈÈ äÞÆÊææÞä@DÚÒÆäÞÄØÂôÊDv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\84ª¦¾\8c¤\8a¢D@Dj`\``````Dv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\82\86\90\8aD@D\9c\9e@\86\82\86\90\8aDv>\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\82\86\90\8a\98\92\9c\96@\86\9e\9a \9e\9c\8a\9c¨D@DDv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\86\98\96¾\8c¤\8a¢D@Dj`\``````DvJ\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\88\8a\84ª\8e¾\92\8cD@D\9eÜZ\86ÐÒà@\90®@\88ÊÄêÎ@\9aÞÈêØÊDv<\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\98\9a\84\84¤\82\9a@¦\92´\8aD@DljjflDv2\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D\9a\84@\8c ªD@D`Dv=\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D ¤\9e\86¾\8c¤\8a¢D@Dj`\``````Dv8\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@DÚÒÆäÞÄØÂôÊD@D¤¦¨¾ \9e\98\82¤\92¨²D@D`Dv-\84æÄ®Òôtt\82ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfdD@DÞàľêÂäèØÒèÊDv4\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfdD@D\86¾\84\82ª\88¤\82¨\8aD@Drl``Dv2\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfdD@D\86¾\88\82¨\82¾\84\92¨¦D@DpDv3\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfdD@D\86¾\9e\88\88¾ \82¤\92¨²D@DbDv3\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfdD@D\86¾ª¦\8a¾ \82¤\92¨²D@D`Dv7\84æÄ®ÒôttªàÈÂèÊ\86ÞÚàÞÜÊÜè@D¤¦dfdD@D\92\9e¨² \8aD@D°\92\98¾ª\82¤¨¾¬bDv.\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\8e\8a\9c\8a¤\82¨\8a¾\9a\8a\9a¨\8a¦¨D@D¨¤ª\8aDv2\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\8e\8a\9c\8a¤\82¨\8a¾ \8a¤\92 \90¨\8a¦¨D@D\8c\82\98¦\8aDv$\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\88\92\9cD@D¤¦dfdDv%\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\88\9eª¨D@D¤¦dfdDv=\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\88\82¨\82¾\92\9c¦D@DÈØÚľÆÜèØäD@D¨Êæè\82àà¾\9aÊÚÞäòDv=\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾\88\82¨\82¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àà¾\9aÊÚÞäòDv@\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾ ¤\9e\8e¤\82\9a¾\92\9c¦D@DÒØÚľÆÜèØäD@D¨Êæè\82àà¾\9aÊÚÞäòDv@\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾ ¤\9e\8e¤\82\9a¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àà¾\9aÊÚÞäòDv>\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\82\86\96¾\92\9c¦D@DÈØÚľÆÜèØäD@D¨Êæè\82àà¾\9aÊÚÞäòDv>\84æÄ®ÒôttªàÈÂèʦ®@D¦®¾¦¨\82\86\96¾ \82¤D@D\86¾\84\82¦\8a\82\88\88¤D@D¨Êæè\82àà¾\9aÊÚÞäòDv
\ No newline at end of file
--- /dev/null
+#include "xparameters.h"
+#include "xgpio_l.h"
+
+#include "stdio.h"
+
+#include "xutil.h"
+
+#define DISP7(a,b,c,d,e,f,g) (0|((~(a|b<<1|c<<2|d<<3|e<<4|f<<5|g<<6))&0xff))
+
+void display_num(unsigned short num) {
+ unsigned int val = 0x00;
+ int i;
+ unsigned short digit;
+
+ XGpio_mSetDataDirection(XPAR_SEVENSEG_BASEADDR, 1, 0x00000000);
+
+ for (i=0; i<5; i++) {
+ digit = ((num>>(4*i)) & 0xf);
+ switch(digit) {
+ case 0x0:
+ val = DISP7(1,1,1,1,1,1,0);
+ break;
+ case 0x1:
+ val = DISP7(0,1,1,0,0,0,0);
+ break;
+ case 0x2:
+ val = DISP7(1,1,0,1,1,0,1);
+ break;
+ case 0x3:
+ val = DISP7(1,1,1,1,0,0,1);
+ break;
+ case 0x4:
+ val = DISP7(0,1,1,0,0,1,1);
+ break;
+ case 0x5:
+ val = DISP7(1,0,1,1,0,1,1);
+ break;
+ case 0x6:
+ val = DISP7(1,0,1,1,1,1,1);
+ break;
+ case 0x7:
+ val = DISP7(1,1,1,0,0,0,0);
+ break;
+ case 0x8:
+ val = DISP7(1,1,1,1,1,1,1);
+ break;
+ case 0x9:
+ val = DISP7(1,1,1,1,0,1,1);
+ break;
+ case 0xa:
+ val = DISP7(1,1,1,0,1,1,1);
+ break;
+ case 0xb:
+ val = DISP7(0,0,1,1,1,1,1);
+ break;
+ case 0xc:
+ val = DISP7(1,0,0,1,1,1,0);
+ break;
+ case 0xd:
+ val = DISP7(0,1,1,1,1,0,1);
+ break;
+ case 0xe:
+ val = DISP7(1,0,0,1,1,1,1);
+ break;
+ case 0xf:
+ val = DISP7(1,0,0,0,1,1,1);
+ break;
+ }
+
+ val |= 1 << (8+(3-i));
+
+ if (i == 4)
+ val = 0x00;
+
+ XGpio_mSetDataReg(XPAR_SEVENSEG_BASEADDR, 1, val);
+ if (i != 4)
+ for (val = 0; val < 100000; val++);
+ }
+}
+
+void flash_chip_erase() {
+ volatile unsigned char *flash = (volatile unsigned char*)XPAR_FLASH_MEM0_BASEADDR;
+
+ flash[0x555] = 0xAA;
+ flash[0xAAA] = 0x55;
+ flash[0x555] = 0x80;
+ flash[0x555] = 0xAA;
+ flash[0xAAA] = 0x55;
+ flash[0x555] = 0x10;
+}
+
+void flash_erase_sector(unsigned int addr) {
+ volatile unsigned char *flash = (volatile unsigned char*)XPAR_FLASH_MEM0_BASEADDR;
+
+ flash[0x555] = 0xAA;
+ flash[0xAAA] = 0x55;
+ flash[0x555] = 0x80;
+ flash[0x555] = 0xAA;
+ flash[0xAAA] = 0x55;
+ flash[addr] = 0x30;
+}
+
+void flash_program_byte(unsigned int addr, unsigned char value) {
+ volatile unsigned char *flash = (volatile unsigned char*)XPAR_FLASH_MEM0_BASEADDR;
+ unsigned int count = 0xffffffff;
+
+ if (flash[addr] != 0xff)
+ return;
+
+ flash[0x555] = 0xAA;
+ flash[0xAAA] = 0x55;
+ flash[0x555] = 0xA0;
+ flash[addr] = value;
+
+ while (flash[addr] != value && count) { count--; }
+}
+
+void flash_identify(int enable) {
+ volatile unsigned char *flash = (volatile unsigned char*)XPAR_FLASH_MEM0_BASEADDR;
+
+ flash[0x555] = 0xAA;
+ flash[0xAAA] = 0x55;
+ flash[0x555] = enable?0x90:0xF0;
+}
+
+int main (void) {
+ int i,a;
+ volatile unsigned char *flash = (volatile unsigned char*)XPAR_FLASH_MEM0_BASEADDR;
+
+ XGpio_mSetDataDirection(XPAR_LEDS_BASEADDR, 1, 0x00000000);
+ XGpio_mSetDataReg(XPAR_LEDS_BASEADDR, 1, 0x00);
+ print("\r\nHallo Raggedstone!\r\n");
+ for (i = 0; i < 1500000000; i++);
+
+ flash_identify(1);
+ putnum(flash[0]|flash[1]<<8|flash[2]<<16|flash[3]<<24);
+ print("\r\n");
+ flash_identify(0);
+ putnum(flash[0]|flash[1]<<8|flash[2]<<16|flash[3]<<24);
+ print("\r\n");
+
+ for (i = 0; i < 1500000000; i++);
+ i = 0;
+ while(1) {
+ print("Hallo Raggedstone ");
+ display_num(i>>8);
+ putnum(i);
+ XGpio_mSetDataReg(XPAR_LEDS_BASEADDR, 1, (i & 0xf00)>>8);
+ print("\r\n");
+ if (i == 0x7ffff)
+ i = 0;
+ else
+ i++;
+ }
+ return 0;
+}
--- /dev/null
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
+# Thu Mar 22 21:42:23 2007
+# Target Board: Custom
+# Family: spartan3
+# Device: xc3s1500
+# Package: fg456
+# Speed Grade: -4
+# Processor: Microblaze
+# System clock frequency: 50.000000 MHz
+# Debug interface: On-Chip HW Debug Module
+# On Chip Memory : 64 KB
+# ##############################################################################
+
+
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = O
+ PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
+ PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
+ PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
+ PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
+ PORT RS232foff = net_vcc, DIR = O
+ PORT LED_out = GPIO_LED_out, VEC = [0:3], DIR = O
+ PORT MEM_FLASH_DQ = FLASH_DQ, DIR = IO, VEC = [7:0]
+ PORT MEM_FLASH_ADDR = FLASH_ADDR, DIR = O, VEC = [18:0]
+ PORT MEM_FLASH_CE = FLASH_CEN, DIR = O, VEC = [0:0]
+ PORT MEM_FLASH_OE = FLASH_OEN, DIR = O, VEC = [0:0]
+ PORT MEM_FLASH_WE = FLASH_WEN, DIR = O
+ PORT SEVENSEG_out = GPIO_7SEG_OUT, DIR = O, VEC = [0:12]
+ PORT DBG_FLASH_ADDR = FLASH_ADDR_split, DIR = O, VEC = [0:31]
+
+
+BEGIN microblaze
+ PARAMETER INSTANCE = microblaze_0
+ PARAMETER HW_VER = 4.00.b
+ PARAMETER C_USE_FPU = 0
+ PARAMETER C_DEBUG_ENABLED = 1
+ PARAMETER C_NUMBER_OF_PC_BRK = 2
+ PARAMETER C_FSL_DATA_SIZE = 32
+ PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
+ PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
+ BUS_INTERFACE DLMB = dlmb
+ BUS_INTERFACE ILMB = ilmb
+ BUS_INTERFACE DOPB = mb_opb
+ BUS_INTERFACE IOPB = mb_opb
+ PORT DBG_CAPTURE = DBG_CAPTURE_s
+ PORT DBG_CLK = DBG_CLK_s
+ PORT DBG_REG_EN = DBG_REG_EN_s
+ PORT DBG_TDI = DBG_TDI_s
+ PORT DBG_TDO = DBG_TDO_s
+ PORT DBG_UPDATE = DBG_UPDATE_s
+END
+
+BEGIN opb_v20
+ PARAMETER INSTANCE = mb_opb
+ PARAMETER HW_VER = 1.10.c
+ PARAMETER C_EXT_RESET_HIGH = 0
+ PORT SYS_Rst = sys_rst_s
+ PORT OPB_Clk = sys_clk_s
+END
+
+BEGIN opb_mdm
+ PARAMETER INSTANCE = debug_module
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_MB_DBG_PORTS = 1
+ PARAMETER C_USE_UART = 0
+ PARAMETER C_BASEADDR = 0x41400000
+ PARAMETER C_HIGHADDR = 0x4140ffff
+ BUS_INTERFACE SOPB = mb_opb
+ PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
+ PORT DBG_CLK_0 = DBG_CLK_s
+ PORT DBG_REG_EN_0 = DBG_REG_EN_s
+ PORT DBG_TDI_0 = DBG_TDI_s
+ PORT DBG_TDO_0 = DBG_TDO_s
+ PORT DBG_UPDATE_0 = DBG_UPDATE_s
+END
+
+BEGIN lmb_v10
+ PARAMETER INSTANCE = ilmb
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_EXT_RESET_HIGH = 0
+ PORT SYS_Rst = sys_rst_s
+ PORT LMB_Clk = sys_clk_s
+END
+
+BEGIN lmb_v10
+ PARAMETER INSTANCE = dlmb
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_EXT_RESET_HIGH = 0
+ PORT SYS_Rst = sys_rst_s
+ PORT LMB_Clk = sys_clk_s
+END
+
+BEGIN lmb_bram_if_cntlr
+ PARAMETER INSTANCE = dlmb_cntlr
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BASEADDR = 0x00000000
+ PARAMETER C_HIGHADDR = 0x00007FFF
+ BUS_INTERFACE SLMB = dlmb
+ BUS_INTERFACE BRAM_PORT = dlmb_port
+END
+
+BEGIN lmb_bram_if_cntlr
+ PARAMETER INSTANCE = ilmb_cntlr
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BASEADDR = 0x00000000
+ PARAMETER C_HIGHADDR = 0x00007FFF
+ BUS_INTERFACE SLMB = ilmb
+ BUS_INTERFACE BRAM_PORT = ilmb_port
+END
+
+BEGIN bram_block
+ PARAMETER INSTANCE = lmb_bram
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE PORTA = ilmb_port
+ BUS_INTERFACE PORTB = dlmb_port
+END
+
+BEGIN opb_uartlite
+ PARAMETER INSTANCE = RS232
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BAUDRATE = 115200
+ PARAMETER C_DATA_BITS = 8
+ PARAMETER C_ODD_PARITY = 1
+ PARAMETER C_USE_PARITY = 0
+ PARAMETER C_CLK_FREQ = 50000000
+ PARAMETER C_BASEADDR = 0x40600000
+ PARAMETER C_HIGHADDR = 0x4060ffff
+ BUS_INTERFACE SOPB = mb_opb
+ PORT RX = fpga_0_RS232_RX
+ PORT TX = fpga_0_RS232_TX
+END
+
+BEGIN dcm_module
+ PARAMETER INSTANCE = dcm_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_CLK0_BUF = TRUE
+ PARAMETER C_CLKIN_PERIOD = 20.000000
+ PARAMETER C_CLK_FEEDBACK = 1X
+ PARAMETER C_DLL_FREQUENCY_MODE = LOW
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PORT CLKIN = dcm_clk_s
+ PORT CLK0 = sys_clk_s
+ PORT CLKFB = sys_clk_s
+ PORT RST = net_gnd
+ PORT LOCKED = dcm_0_lock
+END
+
+BEGIN opb_gpio
+ PARAMETER INSTANCE = LEDS
+ PARAMETER HW_VER = 3.01.b
+ PARAMETER C_GPIO_WIDTH = 4
+ PARAMETER C_IS_BIDIR = 0
+ PARAMETER C_BASEADDR = 0x40020000
+ PARAMETER C_HIGHADDR = 0x4002ffff
+ BUS_INTERFACE SOPB = mb_opb
+ PORT GPIO_d_out = GPIO_LED_out
+END
+
+BEGIN opb_emc
+ PARAMETER INSTANCE = FLASH
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_NUM_BANKS_MEM = 1
+ PARAMETER C_MAX_MEM_WIDTH = 8
+ PARAMETER C_MEM0_WIDTH = 8
+ PARAMETER C_TCEDV_PS_MEM_0 = 70000
+ PARAMETER C_TAVDV_PS_MEM_0 = 70000
+ PARAMETER C_THZCE_PS_MEM_0 = 25000
+ PARAMETER C_TWC_PS_MEM_0 = 110000
+ PARAMETER C_TWP_PS_MEM_0 = 70000
+ PARAMETER C_TLZWE_PS_MEM_0 = 15000
+ PARAMETER C_OPB_CLK_PERIOD_PS = 20000
+ PARAMETER C_THZOE_PS_MEM_0 = 25000
+ PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
+ PARAMETER C_MEM0_BASEADDR = 0x20000000
+ PARAMETER C_MEM0_HIGHADDR = 0x2007FFFF
+ PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 0
+ BUS_INTERFACE SOPB = mb_opb
+ PORT Mem_A = FLASH_ADDR_split
+ PORT Mem_CEN = FLASH_CEN
+ PORT Mem_OEN = FLASH_OEN
+ PORT Mem_WEN = FLASH_WEN
+ PORT Mem_DQ = FLASH_DQ
+END
+
+BEGIN opb_gpio
+ PARAMETER INSTANCE = SEVENSEG
+ PARAMETER HW_VER = 3.01.b
+ PARAMETER C_GPIO_WIDTH = 13
+ PARAMETER C_BASEADDR = 0x40000000
+ PARAMETER C_HIGHADDR = 0x4000ffff
+ BUS_INTERFACE SOPB = mb_opb
+ PORT GPIO_d_out = GPIO_7SEG_OUT
+END
+
+BEGIN chipscope_icon
+ PARAMETER INSTANCE = chipscope_icon_0
+ PARAMETER HW_VER = 1.01.a
+ PORT control0 = ila_control0
+END
+
+BEGIN chipscope_ila
+ PARAMETER INSTANCE = chipscope_ila_0
+ PARAMETER HW_VER = 1.01.a
+ PARAMETER C_NUM_DATA_SAMPLES = 1024
+ PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 19
+ PARAMETER C_TRIG1_UNITS = 1
+ PARAMETER C_TRIG2_UNITS = 1
+ PORT CHIPSCOPE_ILA_CONTROL = ila_control0
+ PORT CLK = sys_clk_s
+ PORT TRIG0 = FLASH_ADDR
+END
+
+BEGIN util_bus_split
+ PARAMETER INSTANCE = flash_split
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_SIZE_IN = 32
+ PARAMETER C_SPLIT = 13
+ PORT Sig = FLASH_ADDR_split
+ PORT Out2 = FLASH_ADDR
+END
+
--- /dev/null
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 1.00.a
+ PARAMETER PROC_INSTANCE = microblaze_0
+ PARAMETER stdout = RS232
+ PARAMETER stdin = RS232
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu
+ PARAMETER DRIVER_VER = 1.01.a
+ PARAMETER HW_INSTANCE = microblaze_0
+ PARAMETER COMPILER = mb-gcc
+ PARAMETER ARCHIVER = mb-ar
+ PARAMETER XMDSTUB_PERIPHERAL = debug_module
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = opbarb
+ PARAMETER DRIVER_VER = 1.02.a
+ PARAMETER HW_INSTANCE = mb_opb
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartlite
+ PARAMETER DRIVER_VER = 1.01.a
+ PARAMETER HW_INSTANCE = debug_module
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = dlmb_cntlr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = ilmb_cntlr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartlite
+ PARAMETER DRIVER_VER = 1.01.a
+ PARAMETER HW_INSTANCE = RS232
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.01.a
+ PARAMETER HW_INSTANCE = LEDS
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emc
+ PARAMETER DRIVER_VER = 2.00.a
+ PARAMETER HW_INSTANCE = FLASH
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.01.a
+ PARAMETER HW_INSTANCE = SEVENSEG
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = chipscope_icon_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = chipscope_ila_0
+END
+
+
--- /dev/null
+#Please do not modify this file by hand
+XmpVersion: 8.2.02
+IntStyle: default
+MHS File: raggedstone.mhs
+MSS File: raggedstone.mss
+NPL File: projnav/raggedstone.ise
+Architecture: spartan3
+Device: xc3s1500
+Package: fg456
+SpeedGrade: -4
+UseProjNav: 0
+PNImportBitFile:
+PNImportBmmFile:
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+TopInst: system_i
+ReloadPbde: 0
+MainMhsEditor: 0
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+Simulator: mti
+SimModel: BEHAVIORAL
+SimXLib:
+SimEdkLib:
+MixLangSim: 1
+UcfFile: data/raggedstone.ucf
+FpgaImpMode: 0
+ShowLicenseDialog: 1
+Processor: microblaze_0
+BootLoop: 0
+XmdStub: 0
+SwProj: raggedstone
+Processor: microblaze_0
+Executable: raggedstone/executable.elf
+Source: raggedstone.c
+DefaultInit: executable
+InitBram: 1
+Active: 1
+CompilerOptLevel: 2
+GlobPtrOpt: 0
+DebugSym: 1
+ProfileFlag: 0
+ProgStart:
+StackSize:
+HeapSize:
+LinkerScript: raggedstone_linker_script.ld
+ProgCCFlags:
+CompileInXps: 1
+NonXpsApp: 0
--- /dev/null
+/*******************************************************************/
+/* */
+/* This file is automatically generated by linker script generator.*/
+/* */
+/* Version: Xilinx EDK 8.2.02EDK_Im_Sp2.4 */
+/* */
+/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */
+/* */
+/* Description : MicroBlaze Linker Script */
+/* */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+ ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000050, LENGTH = 0x00007FB0
+ FLASH_C_MEM0_BASEADDR : ORIGIN = 0x20000000, LENGTH = 0x00080000
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_start)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.vectors.reset 0x00000000 : {
+ *(.vectors.reset)
+}
+
+.vectors.sw_exception 0x00000008 : {
+ *(.vectors.sw_exception)
+}
+
+.vectors.interrupt 0x00000010 : {
+ *(.vectors.interrupt)
+}
+
+.vectors.hw_exception 0x00000020 : {
+ *(.vectors.hw_exception)
+}
+
+.text : {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+} > ilmb_cntlr_dlmb_cntlr
+
+.init : {
+ KEEP (*(.init))
+} > ilmb_cntlr_dlmb_cntlr
+
+.fini : {
+ KEEP (*(.fini))
+} > ilmb_cntlr_dlmb_cntlr
+
+.rodata : {
+ __rodata_start = .;
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+ __rodata_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.sdata2 : {
+ . = ALIGN(8);
+ __sdata2_start = .;
+ *(.sdata2)
+ *(.gnu.linkonce.s2.*)
+ . = ALIGN(8);
+ __sdata2_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.sbss2 : {
+ __sbss2_start = .;
+ *(.sbss2)
+ *(.gnu.linkonce.sb2.*)
+ __sbss2_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.data : {
+ . = ALIGN(4);
+ __data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __data_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.got : {
+ *(.got)
+} > ilmb_cntlr_dlmb_cntlr
+
+.got1 : {
+ *(.got1)
+} > ilmb_cntlr_dlmb_cntlr
+
+.got2 : {
+ *(.got2)
+} > ilmb_cntlr_dlmb_cntlr
+
+.ctors : {
+ __CTOR_LIST__ = .;
+ ___CTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ ___CTORS_END___ = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.dtors : {
+ __DTOR_LIST__ = .;
+ ___DTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ ___DTORS_END___ = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.eh_frame : {
+ *(.eh_frame)
+} > ilmb_cntlr_dlmb_cntlr
+
+.jcr : {
+ *(.jcr)
+} > ilmb_cntlr_dlmb_cntlr
+
+.gcc_except_table : {
+ *(.gcc_except_table)
+} > ilmb_cntlr_dlmb_cntlr
+
+.sdata : {
+ . = ALIGN(8);
+ __sdata_start = .;
+ *(.sdata)
+ *(.gnu.linkonce.s.*)
+ __sdata_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.sbss : {
+ . = ALIGN(4);
+ __sbss_start = .;
+ *(.sbss)
+ *(.gnu.linkonce.sb.*)
+ . = ALIGN(8);
+ __sbss_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.tdata : {
+ __tdata_start = .;
+ *(.tdata)
+ *(.gnu.linkonce.td.*)
+ __tdata_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.tbss : {
+ __tbss_start = .;
+ *(.tbss)
+ *(.gnu.linkonce.tb.*)
+ __tbss_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.bss : {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap : {
+ . = ALIGN(8);
+ _heap = .;
+ _heap_start = .;
+ . += _HEAP_SIZE;
+ _heap_end = .;
+} > ilmb_cntlr_dlmb_cntlr
+
+.stack : {
+ _stack_end = .;
+ . += _STACK_SIZE;
+ . = ALIGN(8);
+ _stack = .;
+ __stack = _stack;
+} > ilmb_cntlr_dlmb_cntlr
+
+}
+
projects / raggedstone / commitdiff