From: Michael Gernoth <michael@gernoth.net>
Date: Sat, 3 Nov 2007 17:41:48 +0000 (+0100)
Subject: Update to EDK 9.2
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/2245a9fc38ae7959867a57992da382b22117b8a4

Update to EDK 9.2
 * New Microblaze 7.00.a
 * Change BUS from OPB to PLB
 * Exchange all peripherials to PLB ones
---

diff --git a/xps/raggedstone.mhs b/xps/raggedstone.mhs
index 9dd07ca..0cd0fa6 100644
--- a/xps/raggedstone.mhs
+++ b/xps/raggedstone.mhs
@@ -1,3 +1,4 @@
+
 # ##############################################################################
 # Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
 # Thu Mar 22 21:42:23 2007
@@ -11,8 +12,6 @@
 # Debug interface: On-Chip HW Debug Module
 # On Chip Memory :  64 KB
 # ##############################################################################
-
-
  PARAMETER VERSION = 2.1.0
 
 
@@ -22,7 +21,6 @@
  PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
  PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
  PORT RS232foff = net_vcc, DIR = O
- PORT LED_out = GPIO_LED_out, VEC = [0:3], DIR = O
  PORT MEM_FLASH_DQ = FLASH_DQ, DIR = IO, VEC = [7:0]
  PORT MEM_FLASH_ADDR = FLASH_ADDR, DIR = O, VEC = [18:0]
  PORT MEM_FLASH_CE = FLASH_CEN, DIR = O, VEC = [0:0]
@@ -30,39 +28,20 @@
  PORT MEM_FLASH_WE = FLASH_WEN, DIR = O
  PORT SEVENSEG_out = GPIO_7SEG_OUT, DIR = O, VEC = [0:12]
  PORT DBG_FLASH_ADDR = FLASH_ADDR_split, DIR = O, VEC = [0:31]
+ PORT LED_out = LEDS_GPIO_d_out, DIR = O, VEC = [0:3]
 
 
-BEGIN opb_v20
- PARAMETER INSTANCE = mb_opb
- PARAMETER HW_VER = 1.10.c
- PARAMETER C_EXT_RESET_HIGH = 0
- PORT SYS_Rst = sys_rst_s
- PORT OPB_Clk = sys_clk_s
-END
-
-BEGIN opb_mdm
- PARAMETER INSTANCE = debug_module
- PARAMETER HW_VER = 2.00.a
- PARAMETER C_MB_DBG_PORTS = 1
- PARAMETER C_USE_UART = 0
- PARAMETER C_BASEADDR = 0x41400000
- PARAMETER C_HIGHADDR = 0x4140ffff
- BUS_INTERFACE SOPB = mb_opb
-END
-
 BEGIN lmb_v10
  PARAMETER INSTANCE = ilmb
  PARAMETER HW_VER = 1.00.a
- PARAMETER C_EXT_RESET_HIGH = 0
- PORT SYS_Rst = sys_rst_s
+ PORT SYS_Rst = sys_bus_reset
  PORT LMB_Clk = sys_clk_s
 END
 
 BEGIN lmb_v10
  PARAMETER INSTANCE = dlmb
  PARAMETER HW_VER = 1.00.a
- PARAMETER C_EXT_RESET_HIGH = 0
- PORT SYS_Rst = sys_rst_s
+ PORT SYS_Rst = sys_bus_reset
  PORT LMB_Clk = sys_clk_s
 END
 
@@ -73,83 +52,6 @@ BEGIN bram_block
  BUS_INTERFACE PORTB = ilmb_cntlr_BRAM_PORT
 END
 
-BEGIN opb_uartlite
- PARAMETER INSTANCE = RS232
- PARAMETER HW_VER = 1.00.b
- PARAMETER C_BAUDRATE = 115200
- PARAMETER C_DATA_BITS = 8
- PARAMETER C_ODD_PARITY = 1
- PARAMETER C_USE_PARITY = 0
- PARAMETER C_CLK_FREQ = 50000000
- PARAMETER C_BASEADDR = 0x40600000
- PARAMETER C_HIGHADDR = 0x4060ffff
- BUS_INTERFACE SOPB = mb_opb
- PORT RX = fpga_0_RS232_RX
- PORT TX = fpga_0_RS232_TX
-END
-
-BEGIN dcm_module
- PARAMETER INSTANCE = dcm_0
- PARAMETER HW_VER = 1.00.c
- PARAMETER C_CLK0_BUF = TRUE
- PARAMETER C_CLKIN_PERIOD = 20.000000
- PARAMETER C_CLK_FEEDBACK = 1X
- PARAMETER C_DLL_FREQUENCY_MODE = LOW
- PARAMETER C_EXT_RESET_HIGH = 1
- PORT CLKIN = dcm_clk_s
- PORT CLK0 = sys_clk_s
- PORT CLKFB = sys_clk_s
- PORT RST = net_gnd
- PORT LOCKED = dcm_0_lock
-END
-
-BEGIN opb_gpio
- PARAMETER INSTANCE = LEDS
- PARAMETER HW_VER = 3.01.b
- PARAMETER C_GPIO_WIDTH = 4
- PARAMETER C_IS_BIDIR = 0
- PARAMETER C_BASEADDR = 0x40020000
- PARAMETER C_HIGHADDR = 0x4002ffff
- BUS_INTERFACE SOPB = mb_opb
- PORT GPIO_d_out = GPIO_LED_out
-END
-
-BEGIN opb_emc
- PARAMETER INSTANCE = FLASH
- PARAMETER HW_VER = 2.00.a
- PARAMETER C_NUM_BANKS_MEM = 1
- PARAMETER C_MAX_MEM_WIDTH = 8
- PARAMETER C_MEM0_WIDTH = 8
- PARAMETER C_TCEDV_PS_MEM_0 = 70000
- PARAMETER C_TAVDV_PS_MEM_0 = 70000
- PARAMETER C_THZCE_PS_MEM_0 = 25000
- PARAMETER C_TWC_PS_MEM_0 = 110000
- PARAMETER C_TWP_PS_MEM_0 = 70000
- PARAMETER C_TLZWE_PS_MEM_0 = 15000
- PARAMETER C_OPB_CLK_PERIOD_PS = 20000
- PARAMETER C_THZOE_PS_MEM_0 = 25000
- PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
- PARAMETER C_MEM0_BASEADDR = 0x20000000
- PARAMETER C_MEM0_HIGHADDR = 0x2007FFFF
- PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 0
- BUS_INTERFACE SOPB = mb_opb
- PORT Mem_A = FLASH_ADDR_split
- PORT Mem_CEN = FLASH_CEN
- PORT Mem_OEN = FLASH_OEN
- PORT Mem_WEN = FLASH_WEN
- PORT Mem_DQ = FLASH_DQ
-END
-
-BEGIN opb_gpio
- PARAMETER INSTANCE = SEVENSEG
- PARAMETER HW_VER = 3.01.b
- PARAMETER C_GPIO_WIDTH = 13
- PARAMETER C_BASEADDR = 0x40000000
- PARAMETER C_HIGHADDR = 0x4000ffff
- BUS_INTERFACE SOPB = mb_opb
- PORT GPIO_d_out = GPIO_7SEG_OUT
-END
-
 BEGIN chipscope_icon
  PARAMETER INSTANCE = chipscope_icon_0
  PARAMETER HW_VER = 1.01.a
@@ -180,30 +82,137 @@ END
 
 BEGIN microblaze
  PARAMETER INSTANCE = microblaze_0
- PARAMETER HW_VER = 6.00.b
+ PARAMETER HW_VER = 7.00.a
  PARAMETER C_DEBUG_ENABLED = 1
  PARAMETER C_NUMBER_OF_PC_BRK = 2
- BUS_INTERFACE DOPB = mb_opb
- BUS_INTERFACE IOPB = mb_opb
- BUS_INTERFACE ILMB = ilmb
+ PARAMETER C_FAMILY = spartan3
+ PARAMETER C_INSTANCE = microblaze_0
+ PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
+ PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
+ BUS_INTERFACE DEBUG = mdm_0_MBDEBUG_0
+ BUS_INTERFACE IPLB = mb_plb
+ BUS_INTERFACE DPLB = mb_plb
  BUS_INTERFACE DLMB = dlmb
+ BUS_INTERFACE ILMB = ilmb
+ PORT MB_RESET = mb_reset
 END
 
 BEGIN lmb_bram_if_cntlr
  PARAMETER INSTANCE = dlmb_cntlr
- PARAMETER HW_VER = 2.00.a
+ PARAMETER HW_VER = 2.10.a
  PARAMETER C_BASEADDR = 0x00000000
- PARAMETER C_HIGHADDR = 0x00007FFF
+ PARAMETER C_HIGHADDR = 0x00007fff
  BUS_INTERFACE SLMB = dlmb
  BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT
 END
 
 BEGIN lmb_bram_if_cntlr
  PARAMETER INSTANCE = ilmb_cntlr
- PARAMETER HW_VER = 2.00.a
+ PARAMETER HW_VER = 2.10.a
  PARAMETER C_BASEADDR = 0x00000000
- PARAMETER C_HIGHADDR = 0x00007FFF
+ PARAMETER C_HIGHADDR = 0x00007fff
  BUS_INTERFACE SLMB = ilmb
  BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT
 END
 
+BEGIN mdm
+ PARAMETER INSTANCE = debug_module
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0x84400000
+ PARAMETER C_HIGHADDR = 0x8440ffff
+ PARAMETER C_MB_DBG_PORTS = 1
+ BUS_INTERFACE MBDEBUG_0 = mdm_0_MBDEBUG_0
+ BUS_INTERFACE SPLB = mb_plb
+ PORT Debug_SYS_Rst = MB_Debug_Sys_Rst
+END
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = mb_plb
+ PARAMETER HW_VER = 1.00.a
+ PORT SYS_Rst = sys_bus_reset
+ PORT PLB_Clk = sys_clk_s
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = LEDS
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_GPIO_WIDTH = 4
+ PARAMETER C_BASEADDR = 0x84418000
+ PARAMETER C_HIGHADDR = 0x844181ff
+ BUS_INTERFACE SPLB = mb_plb
+ PORT GPIO_d_out = LEDS_GPIO_d_out
+END
+
+BEGIN xps_uartlite
+ PARAMETER INSTANCE = RS232
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BAUDRATE = 115200
+ PARAMETER C_USE_PARITY = 0
+ PARAMETER C_BASEADDR = 0x84000000
+ PARAMETER C_HIGHADDR = 0x8400ffff
+ PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
+ BUS_INTERFACE SPLB = mb_plb
+ PORT TX = fpga_0_RS232_TX
+ PORT RX = fpga_0_RS232_RX
+END
+
+BEGIN proc_sys_reset
+ PARAMETER INSTANCE = proc_sys_reset_0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_EXT_RESET_HIGH = 0
+ PORT MB_Debug_Sys_Rst = MB_Debug_Sys_Rst
+ PORT Bus_Struct_Reset = sys_bus_reset
+ PORT MB_Reset = mb_reset
+ PORT Ext_Reset_In = sys_rst_s
+ PORT Slowest_sync_clk = sys_clk_s
+ PORT Dcm_locked = dcm_locked
+END
+
+BEGIN xps_mch_emc
+ PARAMETER INSTANCE = FLASH
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_MEM0_BASEADDR = 0x20000000
+ PARAMETER C_MEM0_HIGHADDR = 0x2007FFFF
+ PARAMETER C_NUM_CHANNELS = 0
+ PARAMETER C_MAX_MEM_WIDTH = 8
+ PARAMETER C_MEM0_WIDTH = 8
+ PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
+ PARAMETER C_TCEDV_PS_MEM_0 = 70000
+ PARAMETER C_TAVDV_PS_MEM_0 = 70000
+ PARAMETER C_THZCE_PS_MEM_0 = 25000
+ PARAMETER C_THZOE_PS_MEM_0 = 25000
+ PARAMETER C_TWC_PS_MEM_0 = 110000
+ PARAMETER C_TWP_PS_MEM_0 = 70000
+ PARAMETER C_TLZWE_PS_MEM_0 = 15000
+ BUS_INTERFACE SPLB = mb_plb
+ PORT Mem_DQ = FLASH_DQ
+ PORT Mem_WEN = FLASH_WEN
+ PORT Mem_OEN = FLASH_OEN
+ PORT Mem_CEN = FLASH_CEN
+ PORT Mem_A = FLASH_ADDR_split
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = SEVENSEG
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_BASEADDR = 0x40000000
+ PARAMETER C_HIGHADDR = 0x400001FF
+ PARAMETER C_GPIO_WIDTH = 13
+ BUS_INTERFACE SPLB = mb_plb
+ PORT GPIO_d_out = GPIO_7SEG_OUT
+END
+
+BEGIN clock_generator
+ PARAMETER INSTANCE = clock_generator_0
+ PARAMETER HW_VER = 1.00.a
+ PARAMETER C_CLKIN_FREQ = 50000000
+ PARAMETER C_EXT_RESET_HIGH = 1
+ PARAMETER C_CLKOUT0_FREQ = 50000000
+ PARAMETER C_CLKOUT0_PHASE = 0
+ PARAMETER C_CLKOUT0_GROUP = NONE
+ PORT CLKIN = dcm_clk_s
+ PORT CLKOUT0 = sys_clk_s
+ PORT RST = net_gnd
+ PORT LOCKED = dcm_locked
+END
+
diff --git a/xps/raggedstone.mss b/xps/raggedstone.mss
index d0963a7..d767d62 100644
--- a/xps/raggedstone.mss
+++ b/xps/raggedstone.mss
@@ -13,70 +13,71 @@ END
 
 BEGIN PROCESSOR
  PARAMETER DRIVER_NAME = cpu
- PARAMETER DRIVER_VER = 1.01.a
+ PARAMETER DRIVER_VER = 1.11.a
  PARAMETER HW_INSTANCE = microblaze_0
  PARAMETER xmdstub_peripheral = debug_module
+ PARAMETER CORE_CLOCK_FREQ_HZ = 50000000
 END
 
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = opbarb
- PARAMETER DRIVER_VER = 1.02.a
- PARAMETER HW_INSTANCE = mb_opb
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = chipscope_icon_0
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartlite
- PARAMETER DRIVER_VER = 1.02.a
- PARAMETER HW_INSTANCE = debug_module
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = chipscope_ila_0
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = uartlite
- PARAMETER DRIVER_VER = 1.02.a
- PARAMETER HW_INSTANCE = RS232
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = dlmb_cntlr
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 2.01.a
- PARAMETER HW_INSTANCE = LEDS
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = ilmb_cntlr
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = emc
- PARAMETER DRIVER_VER = 2.00.a
- PARAMETER HW_INSTANCE = FLASH
+ PARAMETER DRIVER_NAME = uartlite
+ PARAMETER DRIVER_VER = 1.12.a
+ PARAMETER HW_INSTANCE = debug_module
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = gpio
- PARAMETER DRIVER_VER = 2.01.a
- PARAMETER HW_INSTANCE = SEVENSEG
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = mb_plb
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = chipscope_icon_0
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.11.a
+ PARAMETER HW_INSTANCE = LEDS
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = chipscope_ila_0
+ PARAMETER DRIVER_NAME = uartlite
+ PARAMETER DRIVER_VER = 1.12.a
+ PARAMETER HW_INSTANCE = RS232
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = bram
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = dlmb_cntlr
+ PARAMETER DRIVER_NAME = emc
+ PARAMETER DRIVER_VER = 2.00.a
+ PARAMETER HW_INSTANCE = FLASH
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = bram
- PARAMETER DRIVER_VER = 1.00.a
- PARAMETER HW_INSTANCE = ilmb_cntlr
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.11.a
+ PARAMETER HW_INSTANCE = SEVENSEG
 END
 
 
diff --git a/xps/raggedstone.xmp b/xps/raggedstone.xmp
index 3910345..8e4c715 100644
--- a/xps/raggedstone.xmp
+++ b/xps/raggedstone.xmp
@@ -1,6 +1,6 @@
 #Please do not modify this file by hand
-XmpVersion: 9.1.02
-VerMgmt: 9.1.02
+XmpVersion: 9.2.01
+VerMgmt: 9.2.01
 IntStyle: default
 MHS File: raggedstone.mhs
 MSS File: raggedstone.mss
@@ -26,6 +26,8 @@ SimModel: BEHAVIORAL
 MixLangSim: 1
 UcfFile: data/raggedstone.ucf
 FpgaImpMode: 0
+EnableParTimingError: 0
+EnableResetOptimization: 0
 ShowLicenseDialog: 1
 Processor: microblaze_0
 BootLoop: 0