From: Michael Gernoth Date: Thu, 27 Mar 2008 19:02:16 +0000 (+0100) Subject: Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1 X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/40a64bf197a313eb87943d84a985e0d90086729e?ds=sidebyside Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1 --- diff --git a/dhwk/Makefile b/dhwk/Makefile index f63f36c..fed9553 100644 --- a/dhwk/Makefile +++ b/dhwk/Makefile @@ -1,18 +1,21 @@ PROJECT := dhwk -CLEANFILES := dhwk_fifo* fifo_generator_* param.opt +CLEANFILES := dhwk_fifo* fifo_generator_* param.opt icon.vhd icon.vho icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.vhd ila.vho ila_flist.txt ila_readme.txt ila_xmdf.tcl vio.vhd vio.vho vio_flist.txt vio_readme.txt vio_xmdf.tcl dhwk_all: ip all -ip: icon.edn ila.edn vio.edn dhwk_fifo.ngc +ip: icon.ngc ila.ngc vio.ngc dhwk_fifo.ngc -icon.edn: icon.arg - $(CHIPSCOPE)/bin/lin/generate.sh icon -f=$< +icon.ngc: icon.xco + coregen -b $< + -rmdir -p tmp/_cg -ila.edn: ila.arg - $(CHIPSCOPE)/bin/lin/generate.sh ila -f=$< +ila.ngc: ila.xco + coregen -b $< + -rmdir -p tmp/_cg -vio.edn: vio.arg - $(CHIPSCOPE)/bin/lin/generate.sh vio -f=$< +vio.ngc: vio.xco + coregen -b $< + -rmdir -p tmp/_cg dhwk_fifo.ngc: fifo.xco coregen -b $< diff --git a/dhwk/icon.arg b/dhwk/icon.arg deleted file mode 100644 index 9e4596a..0000000 --- a/dhwk/icon.arg +++ /dev/null @@ -1,8 +0,0 @@ -# -# Usage: generate.exe icon -f= -# --compname=icon --numports=2 --devicefamily=Spartan3 --bscanchain=1 --outputdirectory=. diff --git a/dhwk/icon.xco b/dhwk/icon.xco new file mode 100644 index 0000000..e501122 --- /dev/null +++ b/dhwk/icon.xco @@ -0,0 +1,31 @@ +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s1500 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a +# END Select +# BEGIN Parameters +CSET component_name=icon +CSET number_control_ports=2 +CSET use_ext_bscan=false +CSET use_jtag_bufg=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +GENERATE diff --git a/dhwk/ila.arg b/dhwk/ila.arg deleted file mode 100644 index 2433cb4..0000000 --- a/dhwk/ila.arg +++ /dev/null @@ -1,16 +0,0 @@ -# -# Usage: generate.exe ila -f= -# --compname=ila --outputdirectory=. --datadepth=4096 --datawidth=96 --numtrigports=1 --trigportwidth0=32 --nummatchunits=1 --mtrigport0=0 --mtype0=0 --enablestoragequal --devicefamily=Spartan3 --srl16type=2 --createcdc diff --git a/dhwk/ila.xco b/dhwk/ila.xco new file mode 100644 index 0000000..c0a3496 --- /dev/null +++ b/dhwk/ila.xco @@ -0,0 +1,115 @@ +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s1500 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a +# END Select +# BEGIN Parameters +CSET component_name=ila +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=96 +CSET data_same_as_trigger=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET exclude_from_data_storage_1=true +CSET exclude_from_data_storage_10=true +CSET exclude_from_data_storage_11=true +CSET exclude_from_data_storage_12=true +CSET exclude_from_data_storage_13=true +CSET exclude_from_data_storage_14=true +CSET exclude_from_data_storage_15=true +CSET exclude_from_data_storage_16=true +CSET exclude_from_data_storage_2=true +CSET exclude_from_data_storage_3=true +CSET exclude_from_data_storage_4=true +CSET exclude_from_data_storage_5=true +CSET exclude_from_data_storage_6=true +CSET exclude_from_data_storage_7=true +CSET exclude_from_data_storage_8=true +CSET exclude_from_data_storage_9=true +CSET match_type_1=basic +CSET match_type_10=basic +CSET match_type_11=basic +CSET match_type_12=basic +CSET match_type_13=basic +CSET match_type_14=basic +CSET match_type_15=basic +CSET match_type_16=basic +CSET match_type_2=basic +CSET match_type_3=basic +CSET match_type_4=basic +CSET match_type_5=basic +CSET match_type_6=basic +CSET match_type_7=basic +CSET match_type_8=basic +CSET match_type_9=basic +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=4096 +CSET sample_on=Rising +CSET trigger_port_width_1=32 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=true +# END Parameters +GENERATE diff --git a/dhwk/vio.arg b/dhwk/vio.arg deleted file mode 100644 index e719ad4..0000000 --- a/dhwk/vio.arg +++ /dev/null @@ -1,10 +0,0 @@ -# -# Usage: generate.exe vio -f= -# --compname=vio --outputdirectory=. --devicefamily=Virtex4 --srl16type=2 --asyncinwidth=4 --syncoutwidth=1 --createcdc diff --git a/dhwk/vio.xco b/dhwk/vio.xco new file mode 100644 index 0000000..7575b90 --- /dev/null +++ b/dhwk/vio.xco @@ -0,0 +1,35 @@ +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s1500 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.02.a +# END Select +# BEGIN Parameters +CSET asynchronous_input_port_width=4 +CSET asynchronous_output_port_width=8 +CSET component_name=vio +CSET enable_asynchronous_input_port=true +CSET enable_asynchronous_output_port=false +CSET enable_synchronous_input_port=false +CSET enable_synchronous_output_port=true +CSET invert_clock_input=false +CSET synchronous_input_port_width=8 +CSET synchronous_output_port_width=1 +# END Parameters +GENERATE diff --git a/ethernet/Makefile b/ethernet/Makefile index 1569b23..e8a7031 100644 --- a/ethernet/Makefile +++ b/ethernet/Makefile @@ -1,13 +1,16 @@ PROJECT := ethernet +CLEANFILES := param.opt icon.vhd icon.vho icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.vhd ila.vho ila_flist.txt ila_readme.txt ila_xmdf.tcl ethernet_all: ip all -ip: icon.edn ila.edn +ip: icon.ngc ila.ngc -icon.edn: icon.arg - $(CHIPSCOPE)/bin/lin/generate.sh icon -f=$< +icon.ngc: icon.xco + coregen -b $< + -rmdir -p tmp/_cg -ila.edn: ila.arg - $(CHIPSCOPE)/bin/lin/generate.sh ila -f=$< +ila.ngc: ila.xco + coregen -b $< + -rmdir -p tmp/_cg include ../common/Makefile.common diff --git a/ethernet/icon.arg b/ethernet/icon.arg deleted file mode 100644 index fc56ce1..0000000 --- a/ethernet/icon.arg +++ /dev/null @@ -1,8 +0,0 @@ -# -# Usage: generate.exe icon -f= -# --compname=icon --numports=1 --devicefamily=Spartan3 --bscanchain=1 --outputdirectory=. diff --git a/ethernet/icon.xco b/ethernet/icon.xco new file mode 100644 index 0000000..bc65d9c --- /dev/null +++ b/ethernet/icon.xco @@ -0,0 +1,31 @@ +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s1500 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a +# END Select +# BEGIN Parameters +CSET component_name=icon +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_jtag_bufg=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +GENERATE diff --git a/ethernet/ila.arg b/ethernet/ila.arg deleted file mode 100644 index 14f9eba..0000000 --- a/ethernet/ila.arg +++ /dev/null @@ -1,16 +0,0 @@ -# -# Usage: generate.exe ila -f= -# --compname=ila --outputdirectory=. --datadepth=2048 --datawidth=64 --numtrigports=1 --trigportwidth0=32 --nummatchunits=1 --mtrigport0=0 --mtype0=0 --enablestoragequal --devicefamily=Spartan3 --srl16type=2 --createcdc diff --git a/ethernet/ila.xco b/ethernet/ila.xco new file mode 100644 index 0000000..713d6d6 --- /dev/null +++ b/ethernet/ila.xco @@ -0,0 +1,115 @@ +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s1500 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a +# END Select +# BEGIN Parameters +CSET component_name=ila +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=64 +CSET data_same_as_trigger=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET exclude_from_data_storage_1=true +CSET exclude_from_data_storage_10=true +CSET exclude_from_data_storage_11=true +CSET exclude_from_data_storage_12=true +CSET exclude_from_data_storage_13=true +CSET exclude_from_data_storage_14=true +CSET exclude_from_data_storage_15=true +CSET exclude_from_data_storage_16=true +CSET exclude_from_data_storage_2=true +CSET exclude_from_data_storage_3=true +CSET exclude_from_data_storage_4=true +CSET exclude_from_data_storage_5=true +CSET exclude_from_data_storage_6=true +CSET exclude_from_data_storage_7=true +CSET exclude_from_data_storage_8=true +CSET exclude_from_data_storage_9=true +CSET match_type_1=basic +CSET match_type_10=basic +CSET match_type_11=basic +CSET match_type_12=basic +CSET match_type_13=basic +CSET match_type_14=basic +CSET match_type_15=basic +CSET match_type_16=basic +CSET match_type_2=basic +CSET match_type_3=basic +CSET match_type_4=basic +CSET match_type_5=basic +CSET match_type_6=basic +CSET match_type_7=basic +CSET match_type_8=basic +CSET match_type_9=basic +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=2048 +CSET sample_on=Rising +CSET trigger_port_width_1=32 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=true +# END Parameters +GENERATE