From: michael <michael>
Date: Tue, 20 Mar 2007 15:26:44 +0000 (+0000)
Subject: use internal clock
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/528d015aa19100f9f97b3469ab7d2aafa43b425e?ds=inline

use internal clock
---

diff --git a/ethernet/ethernet.ucf b/ethernet/ethernet.ucf
index b0b7d52..3353112 100644
--- a/ethernet/ethernet.ucf
+++ b/ethernet/ethernet.ucf
@@ -30,7 +30,7 @@
 # NET "PCI_AD<7>"  LOC = "E7" | IOSTANDARD = PCI33_3 ;
 # NET "PCI_AD<8>"  LOC = "B8" | IOSTANDARD = PCI33_3 ;
 # NET "PCI_AD<9>"  LOC = "F10" | IOSTANDARD = PCI33_3 ;
-NET "PCI_CLOCK"  LOC = "A11" | IOSTANDARD = PCI33_3 ;
+#NET "PCI_CLOCK"  LOC = "A11" | IOSTANDARD = PCI33_3 ;
 # NET "PCI_IDSEL"  LOC = "D14" | IOSTANDARD = PCI33_3 ;
 # NET "PCI_CBEn<0>"  LOC = "F9" | IOSTANDARD = PCI33_3 ;
 # NET "PCI_CBEn<1>"  LOC = "C10" | IOSTANDARD = PCI33_3 ;
@@ -59,6 +59,7 @@ NET "PCI_CLOCK"  LOC = "A11" | IOSTANDARD = PCI33_3 ;
 # NET "TB_nDEVSEL"  LOC = "M5" | IOSTANDARD = LVCMOS33 ;
 # NET "TB_nINTA"  LOC = "U2" | IOSTANDARD = LVCMOS33 ;
 
+NET "INT_CLOCK"  LOC = "AA11" | IOSTANDARD = PCI33_3 ;
 NET "MTX_CLK_PAD_I"  LOC = "M2" | IOSTANDARD = LVCMOS33;
 
 NET "MTXD_PAD_O<0>"  LOC = "M5" | IOSTANDARD = LVCMOS33;
diff --git a/heartbeat/raggedstone.ucf b/heartbeat/raggedstone.ucf
index 2dd2b3f..4cfac3d 100644
--- a/heartbeat/raggedstone.ucf
+++ b/heartbeat/raggedstone.ucf
@@ -36,7 +36,8 @@ NET "PCI_CBE<0>"  LOC = "F9" | IOSTANDARD = PCI33_3 ;
 NET "PCI_CBE<1>"  LOC = "C10" | IOSTANDARD = PCI33_3 ;
 NET "PCI_CBE<2>"  LOC = "D13" | IOSTANDARD = PCI33_3 ;
 NET "PCI_CBE<3>"  LOC = "E13" | IOSTANDARD = PCI33_3 ;
-NET "PCI_CLK"  LOC = "A11" | IOSTANDARD = PCI33_3 ;
+#NET "PCI_CLK"  LOC = "A11" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CLK"  LOC = "AA11" | IOSTANDARD = PCI33_3 ;
 NET "PCI_IDSEL"  LOC = "D14" | IOSTANDARD = PCI33_3 ;
 NET "PCI_nDEVSEL"  LOC = "E12" | IOSTANDARD = PCI33_3 ;
 NET "PCI_nFRAME"  LOC = "C13" | IOSTANDARD = PCI33_3 ;
@@ -51,7 +52,7 @@ NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nREQ"  LOC = "C18" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
 NET "LED5"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
 NET "LED4"  LOC = "AA4" | IOSTANDARD = LVCMOS33 ;
-NET "IDE1"  LOC = "Y1" | IOSTANDARD = LVCMOS33 ;
-NET "IDE2"  LOC = "M6" | IOSTANDARD = LVCMOS33 ;
-NET "IDE3"  LOC = "M5" | IOSTANDARD = LVCMOS33 ;
-NET "IDE4"  LOC = "U2" | IOSTANDARD = LVCMOS33 ;
+#NET "IDE1"  LOC = "Y1" | IOSTANDARD = LVCMOS33 ;
+#NET "IDE2"  LOC = "M6" | IOSTANDARD = LVCMOS33 ;
+#NET "IDE3"  LOC = "M5" | IOSTANDARD = LVCMOS33 ;
+#NET "IDE4"  LOC = "U2" | IOSTANDARD = LVCMOS33 ;
diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index cae72cd..a396160 100644
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -46,7 +46,7 @@ if (rising_edge(clk_i)) then
 		led9_o <= state(7);
 		counter := counter + 1;
 		if counter = divider then
-			if state(7) = '1' then
+			if state(3) = '1' then
 				direction := '1';
 			end if;
 
diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 3d369cf..01dc26b 100644
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -64,11 +64,11 @@ port (
 	LED3	: out std_logic;
 	LED2	: out std_logic;
 	LED4		: out std_logic;
-	LED5		: out std_logic;
-	IDE1	: out std_logic;
-	IDE2	: out std_logic;
-	IDE3	: out std_logic;
-	IDE4	: out std_logic
+	LED5		: out std_logic
+--	IDE1	: out std_logic;
+--	IDE2	: out std_logic;
+--	IDE3	: out std_logic;
+--	IDE4	: out std_logic
 
 );
 end raggedstone;
@@ -209,11 +209,11 @@ port map(
 	led2_o => LED2,
 	led3_o => LED3,
 	led4_o => LED4,
-	led5_o => LED5,
-	led6_o => IDE1,
-	led7_o => IDE2,
-	led8_o => IDE3,
-	led9_o => IDE4
+	led5_o => LED5
+--	led6_o => IDE1,
+--	led7_o => IDE2,
+--	led8_o => IDE3,
+--	led9_o => IDE4
 );
 
 end raggedstone_arch;