From: michael <michael>
Date: Sun, 11 Feb 2007 22:18:24 +0000 (+0000)
Subject: component for dram
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/9ca1e76d1e45429bb79201ceaf0c1078ce018ad0

component for dram
---

diff --git a/dhwk_old/source/generic_dpram.v b/dhwk_old/source/generic_dpram.v
index 816122e..e75a91e 100644
--- a/dhwk_old/source/generic_dpram.v
+++ b/dhwk_old/source/generic_dpram.v
@@ -66,7 +66,10 @@
 // CVS Revision History
 //
 // $Log: generic_dpram.v,v $
-// Revision 1.2  2007-02-11 22:15:39  sithglan
+// Revision 1.3  2007-02-11 22:18:24  michael
+// component for dram
+//
+// Revision 1.2  2007/02/11 22:15:39  sithglan
 // define xilinix and fpga
 //
 // Revision 1.1  2007/02/11 22:05:26  sithglan
@@ -118,8 +121,8 @@ module generic_dpram(
 	//
 	// Default address and data buses width
 	//
-	parameter aw = 5;  // number of bits in address-bus
-	parameter dw = 16; // number of bits in data-bus
+	parameter aw = 12;  // number of bits in address-bus
+	parameter dw = 8; // number of bits in data-bus
 
 	//
 	// Generic synchronous double-port RAM interface
diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index dbb54e9..841f82a 100644
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -152,6 +152,23 @@ port (
 );
 end component;
 
+component generic_dpram
+port (
+	rclk		: in std_logic;
+	rrst		: in std_logic;
+	rce		: in std_logic;
+	oe		: in std_logic;
+	raddr		: in std_logic_vector(11 downto 0);
+	do		: out std_logic_vector(7 downto 0);
+	wclk		: in std_logic;
+	wrst		: in std_logic;
+	wce		: in std_logic;
+	we		: in std_logic;
+	waddr		: in std_logic_vector(11 downto 0);
+	di		: in std_logic_vector(7 downto 0);
+);
+end component;
+
 
 --+-----------------------------------------------------------------------------+
 --|									CONSTANTS  									|