From: michael <michael>
Date: Tue, 13 Feb 2007 22:43:44 +0000 (+0000)
Subject: running light ;-)
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/e784339415bba0d3752c32bb8bba21c09abfe137

running light ;-)
---

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index e079bbb..a1a181f 100644
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -5,7 +5,7 @@ use ieee.std_logic_unsigned.all;
 
 entity heartbeat is
 generic (
-	divider : std_logic_vector(31 downto 0) := X"01F78A40"
+	divider : std_logic_vector(31 downto 0) := "00000000001111101111000101001000"
 );
 
 port (
@@ -24,20 +24,35 @@ begin
 
 process(clk_i, nrst_i)
 variable counter : std_logic_vector(31 downto 0);
-variable state : std_logic := '0';
+variable state : std_logic_vector(3 downto 0) := "0001";
+variable direction : std_logic := '0';
 begin
 
 if (clk_i'event AND clk_i = '1') then
 	if nrst_i = '0' then
 		counter := (others => '0');
         else
-		led5_o <= state;
-		led2_o <= state;
-		led4_o <= not state;
-		led3_o <= not state;
+		led2_o <= state(0);
+		led3_o <= state(1);
+		led4_o <= state(2);
+		led5_o <= state(3);
 		counter := counter + 1;
 		if counter = divider then
-			state := not state;
+			if state(3) = '1' then
+				direction := '1';
+			end if;
+
+			if state(0) = '1' then
+				direction := '0';
+			end if;
+
+			if direction = '0' then
+				state(3 downto 1) := state(2 downto 0);
+				state(0) := '0';
+			else
+				state(2 downto 0) := state(3 downto 1);
+				state(3) := '0';
+			end if;
 			counter := (others => '0');
 	        end if;
 	end if;