From: michael <michael>
Date: Sat, 10 Feb 2007 22:05:37 +0000 (+0000)
Subject: give LED's more sensible names
X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/f7be01477b0e068cbd8bc736401baff92def833b?ds=sidebyside

give LED's more sensible names
blink more ;-)
---

diff --git a/heartbeat/raggedstone.ucf b/heartbeat/raggedstone.ucf
index 31d028c..9f9ac54 100644
--- a/heartbeat/raggedstone.ucf
+++ b/heartbeat/raggedstone.ucf
@@ -1,5 +1,5 @@
-NET "LED_ACCESS"  LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
-NET "LED_INIT"  LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
+NET "LED2"  LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
+NET "LED3"  LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
 NET "PCI_AD<0>"  LOC = "A5" | IOSTANDARD = PCI33_3 ;
 NET "PCI_AD<10>"  LOC = "E9" | IOSTANDARD = PCI33_3 ;
 NET "PCI_AD<11>"  LOC = "F11" | IOSTANDARD = PCI33_3 ;
@@ -48,4 +48,5 @@ NET "PCI_nSERR"  LOC = "B12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nSTOP"  LOC = "A12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
 NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
-NET "LED_ALIVE"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
+NET "LED5"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
+NET "LED4"  LOC = "AA4" | IOSTANDARD = LVCMOS33 ;
diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index 6938e3f..e079bbb 100644
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -11,7 +11,10 @@ generic (
 port (
 	clk_i : in std_logic;
 	nrst_i : in std_logic;
-	led_o : out std_logic
+	led2_o : out std_logic;
+	led3_o : out std_logic;
+	led4_o : out std_logic;
+	led5_o : out std_logic
 );   
 
 end heartbeat;
@@ -28,7 +31,10 @@ if (clk_i'event AND clk_i = '1') then
 	if nrst_i = '0' then
 		counter := (others => '0');
         else
-		led_o <= state;
+		led5_o <= state;
+		led2_o <= state;
+		led4_o <= not state;
+		led3_o <= not state;
 		counter := counter + 1;
 		if counter = divider then
 			state := not state;
diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 2834959..b073989 100644
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -60,9 +60,10 @@ port (
     PCI_nINT    : out std_logic;
  
 	-- debug signals
-	LED_INIT	 : out std_logic;
-	LED_ACCESS	 : out std_logic;
-	LED_ALIVE : out std_logic
+	LED3	: out std_logic;
+	LED2	: out std_logic;
+	LED4		: out std_logic;
+	LED5		: out std_logic
 
 );
 end raggedstone;
@@ -123,7 +124,10 @@ component heartbeat
 port (
 	clk_i : in std_logic;
 	nrst_i : in std_logic;
-	led_o : out std_logic
+	led2_o : out std_logic;
+	led3_o : out std_logic;
+	led4_o : out std_logic;
+	led5_o : out std_logic
 );
 end component;
 
@@ -178,9 +182,9 @@ port map(
 		wb_cyc_o =>		wb_cyc,
 		wb_ack_i =>		wb_ack,
 		wb_err_i =>		wb_err,
-		wb_int_i =>		wb_int,
-		debug_init =>	LED_INIT,
-		debug_access =>	LED_ACCESS
+		wb_int_i =>		wb_int
+--		debug_init =>	LED3,
+--		debug_access =>	LED2
 		);
 
 --+-----------------------------------------+
@@ -191,7 +195,10 @@ my_heartbeat: component heartbeat
 port map( 
 	clk_i => PCI_CLK,
 	nrst_i => PCI_nRES,
-	led_o => LED_ALIVE
+	led2_o => LED2,
+	led3_o => LED3,
+	led4_o => LED4,
+	led5_o => LED5
 );
 
 end raggedstone_arch;