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Commit | Line | Data |
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99e4226b MG |
1 | #include <util/twi.h> |
2 | #include <avr/interrupt.h> | |
3 | #include <stdio.h> | |
4 | #include "i2c.h" | |
77ad1a84 | 5 | #include "bmc.h" |
99e4226b MG |
6 | |
7 | #define TWCR_ACK TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC); | |
8 | #define TWCR_NACK TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(0<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC); | |
9 | #define TWCR_RESET TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(0<<TWWC); | |
10 | ||
77ad1a84 MG |
11 | static volatile unsigned char databuf[12]; |
12 | static volatile uint8_t pos = 0x00; | |
13 | ||
99e4226b MG |
14 | void i2c_init() |
15 | { | |
7f52e040 MG |
16 | TWAR = BMC_ADDR & 0xfe; |
17 | TWDR = 0x00; | |
18 | TWCR &= ~((1<<TWSTA) | (1<<TWSTO)); | |
19 | TWCR |= ((1<<TWEA) | (1<<TWEN) | (1<<TWIE)); | |
20 | printf("Status: 0x%02x\n", TW_STATUS); | |
21 | PORTC = 0x03; | |
99e4226b MG |
22 | } |
23 | ||
7f52e040 | 24 | ISR (TWI_vect, ISR_BLOCK) |
99e4226b | 25 | { |
99e4226b | 26 | switch (TW_STATUS) { |
77ad1a84 MG |
27 | case TW_SR_SLA_ACK: |
28 | #ifdef DEBUG | |
29 | printf("I2C: Slave 0x%02x adressed\n", TWDR); | |
30 | #endif | |
31 | pos = 0x00; | |
32 | TWCR_ACK; | |
33 | break; | |
34 | ||
35 | case TW_SR_DATA_ACK: | |
36 | #ifdef DEBUG | |
37 | printf("I2C: Data received: 0x%02x\n", TWDR); | |
38 | #endif | |
39 | databuf[pos] = TWDR; | |
40 | pos++; | |
41 | TWCR_ACK; | |
42 | break; | |
43 | ||
44 | case TW_SR_STOP: | |
45 | #ifdef DEBUG | |
46 | printf("I2C: STOP received\n"); | |
47 | #endif | |
48 | decode_bmc_cmd((unsigned char*)databuf, pos); | |
49 | pos = 0x00; | |
50 | TWCR_RESET; | |
51 | break; | |
52 | ||
53 | case TW_ST_SLA_ACK: | |
54 | case TW_ST_DATA_ACK: | |
55 | printf("I2C: Data requested\n"); | |
56 | TWDR = 0x00; | |
7f52e040 | 57 | TWCR_ACK; |
99e4226b | 58 | break; |
77ad1a84 MG |
59 | |
60 | default: | |
61 | printf("I2C: Unimplemented status 0x%02x\n", TW_STATUS); | |
62 | TWCR_RESET; | |
63 | break; | |
99e4226b MG |
64 | } |
65 | } |