+ chassis_set_pins((1<<POWER_PIN) | (1<<RESET_PIN), 0);
+ CDDR |= ((1<<POWER_PIN) | (1<<RESET_PIN));
+
+ /* About 1ms */
+ OCR0 = ((F_CPU/64)/1000) - 1;
+
+ TCCR0 = ((1<<WGM01) | (1<<CS01) | (1<<CS00)); /* CTC, Prescaler 64 */
+ TIMSK |= (1<<OCIE0);
+
+}
+
+static void chassis_set_pins(uint8_t pins, uint8_t state)
+{
+#ifdef ACTIVE_LOW
+ state = !state;
+#endif
+
+ if(state) {
+ CPORT |= pins;
+ } else {
+ CPORT &= ~pins;
+ }
+}
+
+static void chassis_power(int msec)
+{
+ uint8_t old_SREG = SREG;
+
+ chassis_set_pins((1<<POWER_PIN), 1);
+
+ cli();
+ if (!power_cnt)
+ power_cnt = msec;
+ SREG = old_SREG;
+}
+
+static void chassis_reset(int msec)
+{
+ uint8_t old_SREG = SREG;
+
+ chassis_set_pins((1<<RESET_PIN), 1);
+
+ cli();
+ if (!reset_cnt)
+ reset_cnt = msec;
+ SREG = old_SREG;