projects / fpga-games / blame
| Commit | Line | Data |
|---|---|---|
| 782690d0 MG |
1 | //---------------------------------------------------------------------\r |
| 2 | // FPGA MOONCRESTA INPORT \r | |
| 3 | //\r | |
| 4 | // Version : 1.01\r | |
| 5 | //\r | |
| 6 | // Copyright(c) 2004 Katsumi Degawa , All rights reserved\r | |
| 7 | //\r | |
| 8 | // Important !\r | |
| 9 | //\r | |
| 10 | // This program is freeware for non-commercial use. \r | |
| 11 | // An author does no guarantee about this program.\r | |
| 12 | // You can use this under your own risk.\r | |
| 13 | //\r | |
| 14 | // 2004-4-30 galaxian modify by K.DEGAWA\r | |
| 15 | //---------------------------------------------------------------------\r | |
| 16 | \r | |
| 17 | // DIP SW 0 1 2 3 4 5 \r | |
| 18 | //---------------------------------------------------------------\r | |
| 19 | // COIN CHUTE \r | |
| 20 | // 1 COIN/1 PLAY 1'b0 1'b0 \r | |
| 21 | // 2 COIN/1 PLAY 1'b1 1'b0 \r | |
| 22 | // 1 COIN/2 PLAY 1'b0 1'b1 \r | |
| 23 | // FREE PLAY 1'b1 1'b1 \r | |
| 24 | // BOUNS\r | |
| 25 | // 1'b0 1'b0 \r | |
| 26 | // 1'b1 1'b0 \r | |
| 27 | // 1'b0 1'b1 \r | |
| 28 | // 1'b1 1'b1\r | |
| 29 | // LIVES \r | |
| 30 | // 2 1'b0\r | |
| 31 | // 3 1'b1\r | |
| 32 | \r | |
| 33 | module mc_inport(\r | |
| 34 | \r | |
| 35 | I_COIN1, // ACTIVE HI\r | |
| 36 | I_COIN2, // ACTIVE HI\r | |
| 37 | I_1P_LE, // ACTIVE HI\r | |
| 38 | I_1P_RI, // ACTIVE HI\r | |
| 39 | I_1P_SH, // ACTIVE HI\r | |
| 40 | I_2P_LE,\r | |
| 41 | I_2P_RI,\r | |
| 42 | I_2P_SH,\r | |
| 43 | I_1P_START, // ACTIVE HI\r | |
| 44 | I_2P_START, // ACTIVE HI\r | |
| 45 | \r | |
| 46 | I_SW0_OEn,\r | |
| 47 | I_SW1_OEn,\r | |
| 48 | I_DIP_OEn,\r | |
| 49 | \r | |
| 50 | O_D\r | |
| 51 | \r | |
| 52 | );\r | |
| 53 | \r | |
| 54 | input I_COIN1;\r | |
| 55 | input I_COIN2;\r | |
| 56 | input I_1P_LE;\r | |
| 57 | input I_1P_RI;\r | |
| 58 | input I_1P_SH;\r | |
| 59 | input I_2P_LE;\r | |
| 60 | input I_2P_RI;\r | |
| 61 | input I_2P_SH;\r | |
| 62 | input I_1P_START;\r | |
| 63 | input I_2P_START;\r | |
| 64 | \r | |
| 65 | input I_SW0_OEn;\r | |
| 66 | input I_SW1_OEn;\r | |
| 67 | input I_DIP_OEn;\r | |
| 68 | \r | |
| 69 | output [7:0]O_D;\r | |
| 70 | \r | |
| 71 | wire W_TABLE = 0; // UP TYPE = 0;\r | |
| 72 | \r | |
| 73 | wire [5:0]W_DIP_D = {1'b0,1'b1,1'b0,1'b0,1'b0,1'b0};\r | |
| 74 | wire [7:0]W_SW0_DI = { 1'b0, 1'b0, W_TABLE, I_1P_SH, I_1P_RI, I_1P_LE, I_COIN2, I_COIN1};\r | |
| 75 | wire [7:0]W_SW1_DI = {W_DIP_D[1],W_DIP_D[0], 1'b0, I_2P_SH, I_2P_RI, I_2P_LE,I_2P_START,I_1P_START};\r | |
| 76 | wire [7:0]W_DIP_DI = { 1'b0, 1'b0, 1'b0, 1'b0,W_DIP_D[5],W_DIP_D[4],W_DIP_D[3],W_DIP_D[2]};\r | |
| 77 | \r | |
| 78 | wire [7:0]W_SW0_DO = I_SW0_OEn ? 8'h00 : W_SW0_DI;\r | |
| 79 | wire [7:0]W_SW1_DO = I_SW1_OEn ? 8'h00 : W_SW1_DI;\r | |
| 80 | wire [7:0]W_DIP_DO = I_DIP_OEn ? 8'h00 : W_DIP_DI;\r | |
| 81 | \r | |
| 82 | assign O_D = W_SW0_DO | W_SW1_DO | W_DIP_DO ;\r | |
| 83 | \r | |
| 84 | endmodule |