cvs.zerfleddert.de Git - fpga-games/blob - galaxian/src/mc_inport.v

   1 //---------------------------------------------------------------------
   2 // FPGA MOONCRESTA   INPORT
   3 //
   4 // Version : 1.01
   5 //
   6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
   7 //
   8 // Important !
   9 //
  10 // This program is freeware for non-commercial use.
  11 // An author does no guarantee about this program.
  12 // You can use this under your own risk.
  13 //
  14 // 2004-4-30  galaxian modify by K.DEGAWA
  15 //---------------------------------------------------------------------
  16
  17 //    DIP SW        0     1     2     3     4     5
  18 //---------------------------------------------------------------
  19 //  COIN CHUTE
  20 // 1 COIN/1 PLAY   1'b0  1'b0
  21 // 2 COIN/1 PLAY   1'b1  1'b0
  22 // 1 COIN/2 PLAY   1'b0  1'b1
  23 // FREE PLAY       1'b1  1'b1
  24 //   BOUNS
  25 //                             1'b0  1'b0
  26 //                             1'b1  1'b0
  27 //                             1'b0  1'b1
  28 //                             1'b1  1'b1
  29 //   LIVES
  30 //     2                                   1'b0
  31 //     3                                   1'b1
  32
  33 module mc_inport(
  34
  35 I_COIN1,      //  ACTIVE HI
  36 I_COIN2,      //  ACTIVE HI
  37 I_1P_LE,      //  ACTIVE HI
  38 I_1P_RI,      //  ACTIVE HI
  39 I_1P_SH,      //  ACTIVE HI
  40 I_2P_LE,
  41 I_2P_RI,
  42 I_2P_SH,
  43 I_1P_START,   //  ACTIVE HI
  44 I_2P_START,   //  ACTIVE HI
  45
  46 I_SW0_OEn,
  47 I_SW1_OEn,
  48 I_DIP_OEn,
  49
  50 O_D
  51
  52 );
  53
  54 input  I_COIN1;
  55 input  I_COIN2;
  56 input  I_1P_LE;
  57 input  I_1P_RI;
  58 input  I_1P_SH;
  59 input  I_2P_LE;
  60 input  I_2P_RI;
  61 input  I_2P_SH;
  62 input  I_1P_START;
  63 input  I_2P_START;
  64
  65 input  I_SW0_OEn;
  66 input  I_SW1_OEn;
  67 input  I_DIP_OEn;
  68
  69 output [7:0]O_D;
  70
  71 wire   W_TABLE = 0;   //  UP TYPE = 0;
  72
  73 wire   [5:0]W_DIP_D  = {1'b0,1'b1,1'b0,1'b0,1'b0,1'b0};
  74 wire   [7:0]W_SW0_DI = {      1'b0,      1'b0,   W_TABLE,   I_1P_SH,   I_1P_RI,   I_1P_LE,   I_COIN2,   I_COIN1};
  75 wire   [7:0]W_SW1_DI = {W_DIP_D[1],W_DIP_D[0],      1'b0,   I_2P_SH,   I_2P_RI,   I_2P_LE,I_2P_START,I_1P_START};
  76 wire   [7:0]W_DIP_DI = {      1'b0,      1'b0,      1'b0,      1'b0,W_DIP_D[5],W_DIP_D[4],W_DIP_D[3],W_DIP_D[2]};
  77
  78 wire   [7:0]W_SW0_DO = I_SW0_OEn ? 8'h00 : W_SW0_DI;
  79 wire   [7:0]W_SW1_DO = I_SW1_OEn ? 8'h00 : W_SW1_DI;
  80 wire   [7:0]W_DIP_DO = I_DIP_OEn ? 8'h00 : W_DIP_DI;
  81
  82 assign O_D = W_SW0_DO | W_SW1_DO | W_DIP_DO ;
  83
  84 endmodule