picture getting better again

[fpga-games] / galaxian / src / roms.v

module galaxian_roms(
I_CLK_18432M,
I_CLK_12M,
I_ADDR,
O_DATA
);

input I_CLK_18432M;
input I_CLK_12M;
input [18:0]I_ADDR;
output [7:0]O_DATA;

//CPU-Roms
wire [7:0]U_ROM_D;

GALAXIAN_U U_ROM(
.CLK(I_CLK_12M),
.ADDR(I_ADDR[10:0]),
.DATA(U_ROM_D),
.ENA(1'b1)
);

wire [7:0]V_ROM_D;

GALAXIAN_V V_ROM(
.CLK(I_CLK_12M),
.ADDR(I_ADDR[10:0]),
.DATA(V_ROM_D),
.ENA(1'b1)
);

wire [7:0]W_ROM_D;

GALAXIAN_W W_ROM(
.CLK(I_CLK_12M),
.ADDR(I_ADDR[10:0]),
.DATA(W_ROM_D),
.ENA(1'b1)
);

wire [7:0]Y_ROM_D;

GALAXIAN_Y Y_ROM(
.CLK(I_CLK_12M),
.ADDR(I_ADDR[10:0]),
.DATA(Y_ROM_D),
.ENA(1'b1)
);

//7L CPU-Rom
wire [7:0]L_ROM_D;

GALAXIAN_7L L_ROM(
.CLK(I_CLK_12M),
.ADDR(I_ADDR[10:0]),
.DATA(L_ROM_D),
.ENA(1'b1)
);

//1K VID-Rom
wire [7:0]K_ROM_D;

GALAXIAN_1K K_ROM(
.CLK(I_CLK_12M),
.ADDR(I_ADDR[10:0]),
.DATA(K_ROM_D),
.ENA(1'b1)
);

//1H VID-Rom
wire [7:0]H_ROM_D;

GALAXIAN_1H H_ROM(
.CLK(I_CLK_12M),
.ADDR(I_ADDR[10:0]),
.DATA(H_ROM_D),
.ENA(1'b1)
);

reg [7:0]DATA_OUT;
reg [7:0]DATA_OUT2;

//    address map
//--------------------------------------------------
// 0x00000 - 0x007FF       galmidw.u        CPU-ROM
// 0x00800 - 0x00FFF       galmidw.v        CPU-ROM
// 0x01000 - 0x017FF       galmidw.w        CPU-ROM
// 0x01800 - 0x01FFF       galmidw.y        CPU-ROM
// 0x02000 - 0x027FF       7l               CPU-ROM
// 0x04000 - 0x047FF       1k.bin           VID-ROM
// 0x05000 - 0x057FF       1h.bin           VID-ROM
// 0x10000 - 0x3FFFF       mc_wav_2.bin     Sound(Wav)Data
always@(I_ADDR or U_ROM_D or V_ROM_D or W_ROM_D or Y_ROM_D or L_ROM_D or K_ROM_D or H_ROM_D)
begin
	if (I_ADDR <= 18'h7ff) begin
		//u
		DATA_OUT <= U_ROM_D;
	end
	else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
		//v
		DATA_OUT <= V_ROM_D;
	end
	else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
		//w
		DATA_OUT <= W_ROM_D;
	end
	else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
		//y
		DATA_OUT <= Y_ROM_D;
	end
	else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
		//7l
		DATA_OUT <= L_ROM_D;
	end
	else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
		//1k
		DATA_OUT <= K_ROM_D;
	end
	else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
		//1h
		DATA_OUT <= H_ROM_D;
	end
	else if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
		//sound
		DATA_OUT <= 8'h00;
	end
	else begin
		DATA_OUT <= 8'h00;
	end
end

always@(negedge I_CLK_18432M)
begin
	DATA_OUT2 <= DATA_OUT;
end

assign O_DATA = DATA_OUT2;

endmodule