cvs.zerfleddert.de Git - fpga-games/blob - galaxian/src/roms.v

   1 module galaxian_roms(
   2 I_CLK_18432M,
   3 I_CLK_12M,
   4 I_ADDR,
   5 O_DATA
   6 );
   7
   8 input I_CLK_18432M;
   9 input I_CLK_12M;
  10 input [18:0]I_ADDR;
  11 output [7:0]O_DATA;
  12
  13 //CPU-Roms
  14 wire [7:0]U_ROM_D;
  15
  16 GALAXIAN_U U_ROM(
  17 .CLK(I_CLK_12M),
  18 .ADDR(I_ADDR[10:0]),
  19 .DATA(U_ROM_D),
  20 .ENA(1'b1)
  21 );
  22
  23 wire [7:0]V_ROM_D;
  24
  25 GALAXIAN_V V_ROM(
  26 .CLK(I_CLK_12M),
  27 .ADDR(I_ADDR[10:0]),
  28 .DATA(V_ROM_D),
  29 .ENA(1'b1)
  30 );
  31
  32 wire [7:0]W_ROM_D;
  33
  34 GALAXIAN_W W_ROM(
  35 .CLK(I_CLK_12M),
  36 .ADDR(I_ADDR[10:0]),
  37 .DATA(W_ROM_D),
  38 .ENA(1'b1)
  39 );
  40
  41 wire [7:0]Y_ROM_D;
  42
  43 GALAXIAN_Y Y_ROM(
  44 .CLK(I_CLK_12M),
  45 .ADDR(I_ADDR[10:0]),
  46 .DATA(Y_ROM_D),
  47 .ENA(1'b1)
  48 );
  49
  50 //7L CPU-Rom
  51 wire [7:0]L_ROM_D;
  52
  53 GALAXIAN_7L L_ROM(
  54 .CLK(I_CLK_12M),
  55 .ADDR(I_ADDR[10:0]),
  56 .DATA(L_ROM_D),
  57 .ENA(1'b1)
  58 );
  59
  60 //1K VID-Rom
  61 wire [7:0]K_ROM_D;
  62
  63 GALAXIAN_1K K_ROM(
  64 .CLK(I_CLK_12M),
  65 .ADDR(I_ADDR[10:0]),
  66 .DATA(K_ROM_D),
  67 .ENA(1'b1)
  68 );
  69
  70 //1H VID-Rom
  71 wire [7:0]H_ROM_D;
  72
  73 GALAXIAN_1H H_ROM(
  74 .CLK(I_CLK_12M),
  75 .ADDR(I_ADDR[10:0]),
  76 .DATA(H_ROM_D),
  77 .ENA(1'b1)
  78 );
  79
  80 reg [7:0]DATA_OUT;
  81 reg [7:0]DATA_OUT2;
  82
  83 //    address map
  84 //--------------------------------------------------
  85 // 0x00000 - 0x007FF       galmidw.u        CPU-ROM
  86 // 0x00800 - 0x00FFF       galmidw.v        CPU-ROM
  87 // 0x01000 - 0x017FF       galmidw.w        CPU-ROM
  88 // 0x01800 - 0x01FFF       galmidw.y        CPU-ROM
  89 // 0x02000 - 0x027FF       7l               CPU-ROM
  90 // 0x04000 - 0x047FF       1k.bin           VID-ROM
  91 // 0x05000 - 0x057FF       1h.bin           VID-ROM
  92 // 0x10000 - 0x3FFFF       mc_wav_2.bin     Sound(Wav)Data
  93 always@(I_ADDR or U_ROM_D or V_ROM_D or W_ROM_D or Y_ROM_D or L_ROM_D or K_ROM_D or H_ROM_D)
  94 begin
  95         if (I_ADDR <= 18'h7ff) begin
  96                 //u
  97                 DATA_OUT <= U_ROM_D;
  98         end
  99         else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
 100                 //v
 101                 DATA_OUT <= V_ROM_D;
 102         end
 103         else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
 104                 //w
 105                 DATA_OUT <= W_ROM_D;
 106         end
 107         else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
 108                 //y
 109                 DATA_OUT <= Y_ROM_D;
 110         end
 111         else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
 112                 //7l
 113                 DATA_OUT <= L_ROM_D;
 114         end
 115         else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
 116                 //1k
 117                 DATA_OUT <= K_ROM_D;
 118         end
 119         else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
 120                 //1h
 121                 DATA_OUT <= H_ROM_D;
 122         end
 123         else if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
 124                 //sound
 125                 DATA_OUT <= 8'h00;
 126         end
 127         else begin
 128                 DATA_OUT <= 8'h00;
 129         end
 130 end
 131
 132 always@(negedge I_CLK_18432M)
 133 begin
 134         DATA_OUT2 <= DATA_OUT;
 135 end
 136
 137 assign O_DATA = DATA_OUT2;
 138
 139 endmodule