faster clock for roms

[fpga-games] / galaxian / src / mc_ld_pls.v

//===============================================================================\r
// FPGA MOONCRESTA VIDEO-LD_PLS_GEN\r
//\r
// Version : 2.00\r
//\r
// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
//================================================================================\r
\r
\r
module mc_ld_pls(\r
\r
I_CLK_6M,\r
I_H_CNT,\r
I_3D_DI,\r
\r
O_LDn,\r
O_CNTRLDn,\r
O_CNTRCLRn,\r
O_COLLn,\r
O_VPLn,\r
O_OBJDATALn,\r
O_MLDn,\r
O_SLDn\r
\r
);\r
\r
input  I_CLK_6M;\r
input  [8:0]I_H_CNT;\r
input  I_3D_DI;\r
\r
output O_LDn;\r
output O_CNTRLDn;\r
output O_CNTRCLRn;\r
output O_COLLn;\r
output O_VPLn;\r
output O_OBJDATALn;\r
output O_MLDn;\r
output O_SLDn;\r
\r
reg    W_5C_Q;\r
always@(posedge I_CLK_6M)\r
   W_5C_Q <= I_H_CNT[0];\r
\r
//    Parts 4D\r
wire   W_4D1_G = ~(I_H_CNT[0]&I_H_CNT[1]&I_H_CNT[2]);\r
wire   [3:0]W_4D1_Q;\r
wire   [3:0]W_4D2_Q;\r
\r
logic_74xx139 U_4D1(\r
\r
.I_G(W_4D1_G),\r
.I_Sel({I_H_CNT[8],I_H_CNT[3]}),\r
.O_Q(W_4D1_Q)\r
\r
);\r
\r
logic_74xx139 U_4D2(\r
\r
.I_G(W_5C_Q),\r
.I_Sel(I_H_CNT[2:1]),\r
.O_Q(W_4D2_Q)\r
\r
);\r
\r
//    Parts 4C\r
wire   [3:0]W_4C1_Q;\r
wire   [3:0]W_4C2_Q;\r
\r
logic_74xx139 U_4C1(\r
\r
.I_G(W_4D2_Q[1]),\r
.I_Sel({I_H_CNT[8],I_H_CNT[3]}),\r
.O_Q(W_4C1_Q)\r
\r
);\r
\r
reg    W_4C1_Q3;\r
always@(negedge I_CLK_6M)    // 2004-9-22 added\r
   W_4C1_Q3 <= W_4C1_Q[3];\r
\r
reg    W_4C2_B;\r
always@(posedge W_4C1_Q3) \r
   W_4C2_B <= I_3D_DI;\r
\r
logic_74xx139 U_4C2(\r
\r
.I_G(W_4D1_Q[3]),\r
.I_Sel({W_4C2_B,~(I_H_CNT[6]&I_H_CNT[5]&I_H_CNT[4]&I_H_CNT[3])}),\r
.O_Q(W_4C2_Q)\r
\r
);\r
\r
assign O_LDn       = W_4D1_G;\r
assign O_CNTRLDn   = W_4D1_Q[2];\r
assign O_CNTRCLRn  = W_4D1_Q[0];\r
assign O_COLLn     = W_4D2_Q[2];\r
assign O_VPLn      = W_4D2_Q[0];\r
assign O_OBJDATALn = W_4C1_Q[2];\r
assign O_MLDn      = W_4C2_Q[0];\r
assign O_SLDn      = W_4C2_Q[1];\r
\r
\r
endmodule\r