]> cvs.zerfleddert.de Git - fpga-games/blob - galaxian/src/mc_ld_pls.v
faster clock for roms
[fpga-games] / galaxian / src / mc_ld_pls.v
1 //===============================================================================
2 // FPGA MOONCRESTA VIDEO-LD_PLS_GEN
3 //
4 // Version : 2.00
5 //
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
7 //
8 // Important !
9 //
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
13 //
14 // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
15 //================================================================================
16
17
18 module mc_ld_pls(
19
20 I_CLK_6M,
21 I_H_CNT,
22 I_3D_DI,
23
24 O_LDn,
25 O_CNTRLDn,
26 O_CNTRCLRn,
27 O_COLLn,
28 O_VPLn,
29 O_OBJDATALn,
30 O_MLDn,
31 O_SLDn
32
33 );
34
35 input I_CLK_6M;
36 input [8:0]I_H_CNT;
37 input I_3D_DI;
38
39 output O_LDn;
40 output O_CNTRLDn;
41 output O_CNTRCLRn;
42 output O_COLLn;
43 output O_VPLn;
44 output O_OBJDATALn;
45 output O_MLDn;
46 output O_SLDn;
47
48 reg W_5C_Q;
49 always@(posedge I_CLK_6M)
50 W_5C_Q <= I_H_CNT[0];
51
52 // Parts 4D
53 wire W_4D1_G = ~(I_H_CNT[0]&I_H_CNT[1]&I_H_CNT[2]);
54 wire [3:0]W_4D1_Q;
55 wire [3:0]W_4D2_Q;
56
57 logic_74xx139 U_4D1(
58
59 .I_G(W_4D1_G),
60 .I_Sel({I_H_CNT[8],I_H_CNT[3]}),
61 .O_Q(W_4D1_Q)
62
63 );
64
65 logic_74xx139 U_4D2(
66
67 .I_G(W_5C_Q),
68 .I_Sel(I_H_CNT[2:1]),
69 .O_Q(W_4D2_Q)
70
71 );
72
73 // Parts 4C
74 wire [3:0]W_4C1_Q;
75 wire [3:0]W_4C2_Q;
76
77 logic_74xx139 U_4C1(
78
79 .I_G(W_4D2_Q[1]),
80 .I_Sel({I_H_CNT[8],I_H_CNT[3]}),
81 .O_Q(W_4C1_Q)
82
83 );
84
85 reg W_4C1_Q3;
86 always@(negedge I_CLK_6M) // 2004-9-22 added
87 W_4C1_Q3 <= W_4C1_Q[3];
88
89 reg W_4C2_B;
90 always@(posedge W_4C1_Q3)
91 W_4C2_B <= I_3D_DI;
92
93 logic_74xx139 U_4C2(
94
95 .I_G(W_4D1_Q[3]),
96 .I_Sel({W_4C2_B,~(I_H_CNT[6]&I_H_CNT[5]&I_H_CNT[4]&I_H_CNT[3])}),
97 .O_Q(W_4C2_Q)
98
99 );
100
101 assign O_LDn = W_4D1_G;
102 assign O_CNTRLDn = W_4D1_Q[2];
103 assign O_CNTRCLRn = W_4D1_Q[0];
104 assign O_COLLn = W_4D2_Q[2];
105 assign O_VPLn = W_4D2_Q[0];
106 assign O_OBJDATALn = W_4C1_Q[2];
107 assign O_MLDn = W_4C2_Q[0];
108 assign O_SLDn = W_4C2_Q[1];
109
110
111 endmodule
Impressum, Datenschutz