cvs.zerfleddert.de Git - fpga-games/blob - galaxian/src/mc_missile.v

   1 //===============================================================================
   2 // FPGA MOONCRESTA VIDEO-MISSILE
   3 //
   4 // Version : 2.00
   5 //
   6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
   7 //
   8 // Important !
   9 //
  10 // This program is freeware for non-commercial use.
  11 // An author does no guarantee about this program.
  12 // You can use this under your own risk.
  13 //
  14 // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
  15 //================================================================================
  16
  17
  18 module mc_missile(
  19
  20 I_CLK_18M,
  21 I_CLK_6M,
  22 I_C_BLn_X,
  23 I_MLDn,
  24 I_SLDn,
  25 I_HPOS,
  26
  27 O_MISSILEn,
  28 O_SHELLn
  29
  30 );
  31
  32 input  I_CLK_6M,I_CLK_18M;
  33 input  I_C_BLn_X;
  34 input  I_MLDn;
  35 input  I_SLDn;
  36 input  [7:0]I_HPOS;
  37
  38 output O_MISSILEn;
  39 output O_SHELLn;
  40
  41 reg    [7:0]W_45R_Q;
  42
  43 always@(posedge I_CLK_6M)
  44 begin
  45    if(I_MLDn==1'b0)
  46       W_45R_Q <= I_HPOS;
  47    else begin
  48       if(I_C_BLn_X)
  49          W_45R_Q <= W_45R_Q +1;
  50       else
  51          W_45R_Q <= W_45R_Q ;
  52    end
  53 end
  54
  55 reg    W_5P1_Q;
  56 reg    W_5P1_CLK;
  57
  58 always@(posedge I_CLK_18M)
  59    W_5P1_CLK <= ~((&W_45R_Q[7:2])&W_5P1_Q);
  60
  61 always@(posedge W_5P1_CLK or negedge I_MLDn)
  62 begin
  63    if(I_MLDn==1'b0)
  64       W_5P1_Q <= 1'b1;
  65    else
  66       W_5P1_Q <= 1'b0;
  67 end
  68
  69 assign O_MISSILEn = W_5P1_CLK;
  70
  71 reg    [7:0]W_45S_Q;
  72 always@(posedge I_CLK_6M)
  73 begin
  74    if(I_SLDn==1'b0)
  75       W_45S_Q <= I_HPOS;
  76    else begin
  77       if(I_C_BLn_X)
  78          W_45S_Q <= W_45S_Q +1;
  79       else
  80          W_45S_Q <= W_45S_Q ;
  81    end
  82 end
  83
  84 reg    W_5P2_Q;
  85 reg    W_5P2_CLK;
  86
  87 always@(posedge I_CLK_18M)
  88    W_5P2_CLK <= ~((&W_45S_Q[7:2])&W_5P2_Q);
  89
  90 always@(posedge W_5P2_CLK or negedge I_SLDn)
  91 begin
  92    if(I_SLDn==1'b0)
  93       W_5P2_Q <= 1'b1;
  94    else
  95       W_5P2_Q <= 1'b0;
  96 end
  97
  98 assign O_SHELLn = W_5P2_CLK;
  99
 100
 101 endmodule