cvs.zerfleddert.de Git - fpga-games/blob - galaxian/src/mc_clock.v

   1 //---------------------------------------------------------------------
   2 // FPGA MOONCRESTA   CLOCK GEN
   3 //
   4 // Version : 1.00
   5 //
   6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
   7 //
   8 // Important !
   9 //
  10 // This program is freeware for non-commercial use.
  11 // An author does no guarantee about this program.
  12 // You can use this under your own risk.
  13 //
  14 //---------------------------------------------------------------------
  15
  16
  17
  18 module mc_clock(
  19
  20 I_CLK_36M,
  21 I_DCM_LOCKED,
  22 O_CLK_18M,
  23 O_CLK_12M,
  24 O_CLK_06M,
  25 O_CLK_06Mn
  26
  27 );
  28
  29 input I_CLK_36M;
  30 input I_DCM_LOCKED;
  31 output O_CLK_18M;
  32 output O_CLK_12M;
  33 output O_CLK_06M;
  34 output O_CLK_06Mn;
  35
  36 // 2/3 clock divider(duty 33%)
  37 //I_CLK   1010101010101010101
  38 //c_ff10  0011110011110011110
  39 //c_ff11  0011000011000011000
  40 //c_ff20  0000110000110000110
  41 //c_ff21  0110000110000110000
  42 //O_12M   0000110110110110110
  43 reg [1:0] state;
  44 reg clk_12m;
  45 initial state = 0;
  46 initial clk_12m = 0;
  47
  48 // 2/3 clock         (duty 66%)
  49 always @(posedge I_CLK_36M)
  50 begin
  51    if (I_DCM_LOCKED == 1) begin
  52       case (state)
  53          2'd0: state <= 2'd1;
  54          2'd1: state <= 2'd2;
  55          2'd2: state <= 2'd0;
  56          2'd3: state <= 2'd0;
  57       endcase
  58
  59       if (state == 2'd2)
  60          clk_12m = 0;
  61       else
  62          clk_12m = 1;
  63    end
  64    else begin
  65       state <= 2'd0;
  66       clk_12m = 0;
  67    end
  68 end
  69
  70 assign O_CLK_12M = clk_12m;
  71
  72 reg CLK_18M;
  73 always @(posedge I_CLK_36M)
  74 begin
  75    if (I_DCM_LOCKED == 1)
  76       CLK_18M <= ~ CLK_18M;
  77    else
  78       CLK_18M <= 0;
  79 end
  80 assign O_CLK_18M = CLK_18M;
  81
  82 // 1/3 clock divider (duty 50%)
  83 reg CLK_6M;
  84 reg CLK_6Mn;
  85
  86 always @(posedge O_CLK_12M)
  87 begin
  88    CLK_6M  <= ~CLK_6M;
  89    CLK_6Mn <= CLK_6M;
  90 end
  91
  92 assign O_CLK_06M = CLK_6M;
  93 assign O_CLK_06Mn = CLK_6Mn;
  94
  95 endmodule