cvs.zerfleddert.de Git - fpga-games/blob - galaxian/t80_ip/T80sed.vhd

   1 -- ****
   2 -- T80(b) core. In an effort to merge and maintain bug fixes ....
   3 --
   4 --
   5 -- Ver 300 started tidyup
   6 -- MikeJ March 2005
   7 -- Latest version from www.fpgaarcade.com (original www.opencores.org)
   8 --
   9 -- ****
  10 -- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
  11 --
  12 -- Z80 compatible microprocessor core, synchronous top level with clock enable
  13 -- Different timing than the original z80
  14 -- Inputs needs to be synchronous and outputs may glitch
  15 --
  16 -- Version : 0238
  17 --
  18 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
  19 --
  20 -- All rights reserved
  21 --
  22 -- Redistribution and use in source and synthezised forms, with or without
  23 -- modification, are permitted provided that the following conditions are met:
  24 --
  25 -- Redistributions of source code must retain the above copyright notice,
  26 -- this list of conditions and the following disclaimer.
  27 --
  28 -- Redistributions in synthesized form must reproduce the above copyright
  29 -- notice, this list of conditions and the following disclaimer in the
  30 -- documentation and/or other materials provided with the distribution.
  31 --
  32 -- Neither the name of the author nor the names of other contributors may
  33 -- be used to endorse or promote products derived from this software without
  34 -- specific prior written permission.
  35 --
  36 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  37 -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  38 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  39 -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  40 -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  41 -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  42 -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  43 -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  44 -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  45 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  46 -- POSSIBILITY OF SUCH DAMAGE.
  47 --
  48 -- Please report bugs to the author, but before you do so, please
  49 -- make sure that this is not a derivative work and that
  50 -- you have the latest version of this file.
  51 --
  52 -- The latest version of this file can be found at:
  53 --      http://www.opencores.org/cvsweb.shtml/t80/
  54 --
  55 -- Limitations :
  56 --
  57 -- File history :
  58 --
  59 --      0235 : First release
  60 --
  61 --      0236 : Added T2Write generic
  62 --
  63 --      0237 : Fixed T2Write with wait state
  64 --
  65 --      0238 : Updated for T80 interface change
  66 --
  67 --      0242 : Updated for T80 interface change
  68 --
  69
  70 library IEEE;
  71 use IEEE.std_logic_1164.all;
  72 use IEEE.numeric_std.all;
  73 use work.T80_Pack.all;
  74
  75 entity T80sed is
  76         port(
  77                 RESET_n         : in  std_logic;
  78                 CLK_n           : in  std_logic;
  79                 CLKEN           : in  std_logic;
  80                 WAIT_n          : in  std_logic;
  81                 INT_n           : in  std_logic;
  82                 NMI_n           : in  std_logic;
  83                 BUSRQ_n         : in  std_logic;
  84                 M1_n            : out std_logic;
  85                 MREQ_n          : out std_logic;
  86                 IORQ_n          : out std_logic;
  87                 RD_n            : out std_logic;
  88                 WR_n            : out std_logic;
  89                 RFSH_n          : out std_logic;
  90                 HALT_n          : out std_logic;
  91                 BUSAK_n         : out std_logic;
  92                 A               : out std_logic_vector(15 downto 0);
  93                 DI              : in  std_logic_vector(7 downto 0);
  94                 DO              : out std_logic_vector(7 downto 0)
  95         );
  96 end T80sed;
  97
  98 architecture rtl of T80sed is
  99
 100         signal IntCycle_n   : std_logic;
 101         signal NoRead       : std_logic;
 102         signal Write        : std_logic;
 103         signal IORQ         : std_logic;
 104         signal DI_Reg       : std_logic_vector(7 downto 0);
 105         signal MCycle       : std_logic_vector(2 downto 0);
 106         signal TState       : std_logic_vector(2 downto 0);
 107
 108 begin
 109
 110         u0 : T80
 111                 generic map(
 112                         Mode      => 0,
 113                         IOWait    => 1)
 114                 port map(
 115                         CEN        => CLKEN,
 116                         M1_n       => M1_n,
 117                         IORQ       => IORQ,
 118                         NoRead     => NoRead,
 119                         Write      => Write,
 120                         RFSH_n     => RFSH_n,
 121                         HALT_n     => HALT_n,
 122                         WAIT_n     => Wait_n,
 123                         INT_n      => INT_n,
 124                         NMI_n      => NMI_n,
 125                         RESET_n    => RESET_n,
 126                         BUSRQ_n    => BUSRQ_n,
 127                         BUSAK_n    => BUSAK_n,
 128                         CLK_n      => CLK_n,
 129                         A          => A,
 130                         DInst      => DI,
 131                         DI         => DI_Reg,
 132                         DO         => DO,
 133                         MC         => MCycle,
 134                         TS         => TState,
 135                         IntCycle_n => IntCycle_n);
 136
 137         process (RESET_n, CLK_n)
 138         begin
 139                 if RESET_n = '0' then
 140                         RD_n <= '1';
 141                         WR_n <= '1';
 142                         IORQ_n <= '1';
 143                         MREQ_n <= '1';
 144                         DI_Reg <= "00000000";
 145                 elsif CLK_n'event and CLK_n = '1' then
 146                         if CLKEN = '1' then
 147                                 RD_n <= '1';
 148                                 WR_n <= '1';
 149                                 IORQ_n <= '1';
 150                                 MREQ_n <= '1';
 151                                 if MCycle = "001" then
 152                                         if TState = "001" or (TState = "010" and Wait_n = '0') then
 153                                                 RD_n <= not IntCycle_n;
 154                                                 MREQ_n <= not IntCycle_n;
 155                                                 IORQ_n <= IntCycle_n;
 156                                         end if;
 157                                         if TState = "011" then
 158                                                 MREQ_n <= '0';
 159                                         end if;
 160                                 else
 161                                         if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
 162                                                 RD_n <= '0';
 163                                                 IORQ_n <= not IORQ;
 164                                                 MREQ_n <= IORQ;
 165                                         end if;
 166                                                 if ((TState = "001") or (TState = "010")) and Write = '1' then
 167                                                         WR_n <= '0';
 168                                                         IORQ_n <= not IORQ;
 169                                                         MREQ_n <= IORQ;
 170                                                 end if;
 171                                 end if;
 172                                 if TState = "010" and Wait_n = '1' then
 173                                         DI_Reg <= DI;
 174                                 end if;
 175                         end if;
 176                 end if;
 177         end process;
 178
 179 end;