cvs.zerfleddert.de Git - linexec-j720/blob - asm/asm-wince.asm

   1         TTL     C:\pocket\test\asm.cpp
   2
   3         AREA    |.drectve|, DRECTVE
   4         DCB     "-defaultlib:coredll.lib "
   5         DCB     "-defaultlib:corelibc.lib "
   6
   7         EXPORT  |?do_it@@YAXXZ|                         ; do_it
   8         AREA    |.pdata|, PDATA
   9 |$T222| DCD     |?do_it@@YAXXZ|
  10         DCD     0x40000100
  11         AREA    |.text|, CODE
  12 |?do_it@@YAXXZ| PROC                                    ; do_it
  13 |$M220|
  14
  15         mcr     p15, 0, r0, c7, c5, 0           ;/* invalidate i cache & BTB */
  16                                                                                 ;       CPWAIT  r0
  17         mrc     p15, 0, r0, c2, c0, 0
  18         mov     r0, r0
  19         sub     pc, pc, #4
  20                                                                                 ;       ldr     r9, =0xa1300100
  21
  22                 mov             r9, r1                                  ;       add             r9, r1, #0x100
  23                 ldr             r5, =0xa0000100                 ;       ldr             r5, =0xa0000100
  24                 ldr             r7, =0xa0100000
  25 label   ldr     r8, [r9]
  26         str     r8, [r5]
  27                 add     r9, r9, #4
  28                 add     r5, r5, #4
  29                 cmp             r5, r7
  30                 blt             label
  31
  32 crash   b crash
  33
  34         MOV             r4, #0xA0000000
  35         add             r2,r4,#0x8000
  36
  37         mov     r11,r2
  38         ldr             r10,=337
  39
  40 ;       mcr     p15, 0, r0, c7, c10, 4 ;/* drain the write buffer*/
  41
  42 ;       CPWAIT  r0
  43 ;       mrc     p15, 0, r0, c2, c0, 0
  44 ;       mov     r0, r0
  45 ;       sub     pc, pc, #4
  46
  47
  48         mcr     p15, 0, r0, c8, c7, 0x00        ;/* invalidate I+D TLB */
  49 ;       CPWAIT  r0
  50         mrc     p15, 0, r0, c2, c0, 0
  51         mov     r0, r0
  52         sub     pc, pc, #4
  53
  54 ;       //; they skipped this, unnecessary? seems like we need to do this
  55         mcr     p15, 0, r0, c7, c5, 0           ;/* invalidate i cache & BTB */
  56
  57 ; S bit set, p and d bit set (no 26 bit mode)
  58 ;       mov     r3, #0x120      ; xscale says p needs to be 0 ???
  59 ;       mcr     p15, 0, r3, c1, c0, 0   ;/* disable the MMU */
  60
  61 ;       CPWAIT  r0
  62 ;       mrc     p15, 0, r0, c2, c0, 0
  63 ;       mov     r0, r0
  64 ;       sub     pc, pc, #4
  65
  66
  67 ;        /*; make sure the pipeline is emptied*/
  68         mov     r0,#0
  69         mov     r0,r0
  70         mov     r0,r0
  71         mov     r0,r0
  72
  73 ;       /* zero PID in Process ID Virtual Address Map register. */
  74 ;       mov     r0, #0
  75         mcr     p15, 0, r0, c13, c0, 0
  76
  77
  78 ;       CPWAIT  r0
  79         mrc     p15, 0, r0, c2, c0, 0
  80         mov     r0, r0
  81         sub     pc, pc, #4
  82
  83 ;       ldr     r5, =0xA00512F5
  84 ;       ldr     r8, =0xefef0000
  85 ;       str     r8, [r5]
  86
  87
  88         mov     r0, #0
  89     mov     r1, r10
  90         ldr     r2, [r2, #0]
  91         mov     r2, #0
  92         mov     pc, r11
  93
  94
  95 |$M221|
  96
  97         ENDP  ; |?do_it@@YAXXZ|, do_it
  98
  99         END