[ms2-kexec] / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 * This Edition is maintained by Matthew Veety (aliasxerog) <mveety@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#define TTB_C		(1 << 0)
#define TTB_S		(1 << 1)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_OC_WBWA	(1 << 3)
#define TTB_RGN_OC_WT	(2 << 3)
#define TTB_RGN_OC_WB	(3 << 3)

#ifndef CONFIG_SMP
#define TTB_FLAGS	TTB_C|TTB_RGN_OC_WB		@ mark PTWs cacheable, outer WB
#else
#define TTB_FLAGS	TTB_C|TTB_S|TTB_RGN_OC_WBWA	@ mark PTWs cacheable and shared, outer WBWA
#endif

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 *
 *	It is assumed that:
 */
	.align	5
ENTRY(cpu_v7_reset)
	mov	pc, r0
ENDPROC(cpu_v7_reset)

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
	dcache_line_size r2, r3
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

/*
 *	cpu_v7_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 */
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
	orr	r0, r0, #TTB_FLAGS
#ifdef CONFIG_ARM_ERRATA_430973
	mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
#endif
	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
	isb
1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
	isb
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
	isb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_switch_mm)

/*
 *	cpu_v7_set_pte_ext(ptep, pte)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at -1024 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
	str	r1, [r0], #-2048		@ linux version

	bic	r3, r1, #0x000003f0
	bic	r3, r3, #PTE_TYPE_MASK
	orr	r3, r3, r2
	orr	r3, r3, #PTE_EXT_AP0 | 2

	tst	r1, #1 << 4
	orrne	r3, r3, #PTE_EXT_TEX(1)

	tst	r1, #L_PTE_WRITE
	tstne	r1, #L_PTE_DIRTY
	orreq	r3, r3, #PTE_EXT_APX

	tst	r1, #L_PTE_USER
	orrne	r3, r3, #PTE_EXT_AP1
	tstne	r3, #PTE_EXT_APX
	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0

	tst	r1, #L_PTE_EXEC
	orreq	r3, r3, #PTE_EXT_XN

	tst	r1, #L_PTE_YOUNG
	tstne	r1, #L_PTE_PRESENT
	moveq	r3, #0

	str	r3, [r0]
	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
#endif
	mov	pc, lr
ENDPROC(cpu_v7_set_pte_ext)

cpu_v7_name:
	.ascii	"ARMv7 Processor"
	.align

	.section ".text.init", #alloc, #execinstr

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	We automatically detect if we have a Harvard cache, and use the
 *	Harvard cache control instructions insead of the unified cache
 *	control instructions.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_setup:
#ifdef CONFIG_SMP
	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
	orr	r0, r0, #(0x1 << 6)
	mcr	p15, 0, r0, c1, c0, 1
#endif
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl	v7_flush_dcache_all
	ldmia	r12, {r0-r5, r7, r9, r11, lr}
#ifdef CONFIG_ARM_ERRATA_430973
	mrc     p15, 0, r10, c1, c0, 1          @ read aux control register
	orr     r10, r10, #(1 << 6)             @ set IBE to 1
	mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
#endif
	mov	r10, #0
#ifdef HARVARD_CACHE
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
#endif
	dsb
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
	orr	r4, r4, #TTB_FLAGS
	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
	mov	r10, #0x1f			@ domains 0, 1 = manager
	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
#endif
	ldr	r5, =0xff0aa1a8
	ldr	r6, =0x40e040e0
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	/*   AT
	 *  TFR   EV X F   I D LR
	 * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *    1    0 110       0011 1.00 .111 1101 < we want
	 */
	.type	v7_crval, #object
v7_crval:
	crval	clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c

__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	.type	v7_processor_functions, #object
ENTRY(v7_processor_functions)
	.word	v7_early_abort
	.word	pabort_ifar
	.word	cpu_v7_proc_init
	.word	cpu_v7_proc_fin
	.word	cpu_v7_reset
	.word	cpu_v7_do_idle
	.word	cpu_v7_dcache_clean_area
	.word	cpu_v7_switch_mm
	.word	cpu_v7_set_pte_ext
	.size	v7_processor_functions, . - v7_processor_functions

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv7"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v7"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__v7_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
4e93cb00 MG	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	* This Edition is maintained by Matthew Veety (aliasxerog) <mveety@gmail.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This is the "shell" of the ARMv7 processor support.
	12	*/
	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
	15	#include <asm/asm-offsets.h>
	16	#include <asm/hwcap.h>
	17	#include <asm/pgtable-hwdef.h>
	18	#include <asm/pgtable.h>
	19
	20	#include "proc-macros.S"
	21
	22	#define TTB_C (1 << 0)
	23	#define TTB_S (1 << 1)
	24	#define TTB_RGN_NC (0 << 3)
	25	#define TTB_RGN_OC_WBWA (1 << 3)
	26	#define TTB_RGN_OC_WT (2 << 3)
	27	#define TTB_RGN_OC_WB (3 << 3)
	28
	29	#ifndef CONFIG_SMP
	30	#define TTB_FLAGS TTB_C\|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB
	31	#else
	32	#define TTB_FLAGS TTB_C\|TTB_S\|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA
	33	#endif
	34
	35	ENTRY(cpu_v7_proc_init)
	36	mov pc, lr
	37	ENDPROC(cpu_v7_proc_init)
	38
	39	ENTRY(cpu_v7_proc_fin)
	40	mov pc, lr
	41	ENDPROC(cpu_v7_proc_fin)
	42
	43	/*
	44	* cpu_v7_reset(loc)
	45	*
	46	* Perform a soft reset of the system. Put the CPU into the
	47	* same state as it would be if it had been reset, and branch
	48	* to what would be the reset vector.
	49	*
	50	* - loc - location to jump to for soft reset
	51	*
	52	* It is assumed that:
	53	*/
	54	.align 5
	55	ENTRY(cpu_v7_reset)
	56	mov pc, r0
	57	ENDPROC(cpu_v7_reset)
	58
	59	/*
	60	* cpu_v7_do_idle()
	61	*
	62	* Idle the processor (eg, wait for interrupt).
	63	*
	64	* IRQs are already disabled.
65	*/
66	ENTRY(cpu_v7_do_idle)
67	dsb @ WFI may enter a low-power mode
68	wfi
69	mov pc, lr
70	ENDPROC(cpu_v7_do_idle)
71
72	ENTRY(cpu_v7_dcache_clean_area)
73	#ifndef TLB_CAN_READ_FROM_L1_CACHE
74	dcache_line_size r2, r3
75	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
76	add r0, r0, r2
77	subs r1, r1, r2
78	bhi 1b
79	dsb
80	#endif
81	mov pc, lr
82	ENDPROC(cpu_v7_dcache_clean_area)
83
84	/*
85	* cpu_v7_switch_mm(pgd_phys, tsk)
86	*
87	* Set the translation table base pointer to be pgd_phys
88	*
89	* - pgd_phys - physical address of new TTB
90	*
91	* It is assumed that:
92	* - we are not using split page tables
93	*/
94	ENTRY(cpu_v7_switch_mm)
95	#ifdef CONFIG_MMU
96	mov r2, #0
97	ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
98	orr r0, r0, #TTB_FLAGS
99	#ifdef CONFIG_ARM_ERRATA_430973
100	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
101	#endif
102	mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
103	isb
104	1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
105	isb
106	mcr p15, 0, r1, c13, c0, 1 @ set context ID
107	isb
108	#endif
109	mov pc, lr
110	ENDPROC(cpu_v7_switch_mm)
111
112	/*
113	* cpu_v7_set_pte_ext(ptep, pte)
114	*
115	* Set a level 2 translation table entry.
116	*
117	* - ptep - pointer to level 2 translation table entry
118	* (hardware version is stored at -1024 bytes)
119	* - pte - PTE value to store
120	* - ext - value for extended PTE bits
121	*/
122	ENTRY(cpu_v7_set_pte_ext)
123	#ifdef CONFIG_MMU
124	str r1, [r0], #-2048 @ linux version
125
126	bic r3, r1, #0x000003f0
127	bic r3, r3, #PTE_TYPE_MASK
128	orr r3, r3, r2
129	orr r3, r3, #PTE_EXT_AP0 \| 2
130
131	tst r1, #1 << 4
132	orrne r3, r3, #PTE_EXT_TEX(1)
133
134	tst r1, #L_PTE_WRITE
135	tstne r1, #L_PTE_DIRTY
136	orreq r3, r3, #PTE_EXT_APX
137
138	tst r1, #L_PTE_USER
139	orrne r3, r3, #PTE_EXT_AP1
140	tstne r3, #PTE_EXT_APX
141	bicne r3, r3, #PTE_EXT_APX \| PTE_EXT_AP0
142
143	tst r1, #L_PTE_EXEC
144	orreq r3, r3, #PTE_EXT_XN
145
146	tst r1, #L_PTE_YOUNG
147	tstne r1, #L_PTE_PRESENT
148	moveq r3, #0
149
150	str r3, [r0]
151	mcr p15, 0, r0, c7, c10, 1 @ flush_pte
152	#endif
153	mov pc, lr
154	ENDPROC(cpu_v7_set_pte_ext)
155
156	cpu_v7_name:
157	.ascii "ARMv7 Processor"
158	.align
159
160	.section ".text.init", #alloc, #execinstr
161
162	/*
163	* __v7_setup
164	*
165	* Initialise TLB, Caches, and MMU state ready to switch the MMU
166	* on. Return in r0 the new CP15 C1 control register setting.
167	*
168	* We automatically detect if we have a Harvard cache, and use the
169	* Harvard cache control instructions insead of the unified cache
170	* control instructions.
171	*
172	* This should be able to cover all ARMv7 cores.
173	*
174	* It is assumed that:
175	* - cache type register is implemented
176	*/
177	__v7_setup:
178	#ifdef CONFIG_SMP
179	mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
180	orr r0, r0, #(0x1 << 6)
181	mcr p15, 0, r0, c1, c0, 1
182	#endif
183	adr r12, __v7_setup_stack @ the local stack
184	stmia r12, {r0-r5, r7, r9, r11, lr}
185	bl v7_flush_dcache_all
186	ldmia r12, {r0-r5, r7, r9, r11, lr}
187	#ifdef CONFIG_ARM_ERRATA_430973
188	mrc p15, 0, r10, c1, c0, 1 @ read aux control register
189	orr r10, r10, #(1 << 6) @ set IBE to 1
190	mcr p15, 0, r10, c1, c0, 1 @ write aux control register
191	#endif
192	mov r10, #0
193	#ifdef HARVARD_CACHE
194	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
195	#endif
196	dsb
197	#ifdef CONFIG_MMU
198	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
199	mcr p15, 0, r10, c2, c0, 2 @ TTB control register
200	orr r4, r4, #TTB_FLAGS
201	mcr p15, 0, r4, c2, c0, 1 @ load TTB1
202	mov r10, #0x1f @ domains 0, 1 = manager
203	mcr p15, 0, r10, c3, c0, 0 @ load domain access register
204	#endif
205	ldr r5, =0xff0aa1a8
206	ldr r6, =0x40e040e0
207	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
208	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
209	adr r5, v7_crval
210	ldmia r5, {r5, r6}
211	mrc p15, 0, r0, c1, c0, 0 @ read control register
212	bic r0, r0, r5 @ clear bits them
213	orr r0, r0, r6 @ set them
214	mov pc, lr @ return to head.S:__ret
215	ENDPROC(__v7_setup)
216
217	/* AT
218	* TFR EV X F I D LR
219	* .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
220	* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
221	* 1 0 110 0011 1.00 .111 1101 < we want
222	*/
223	.type v7_crval, #object
224	v7_crval:
225	crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
226
227	__v7_setup_stack:
228	.space 4 * 11 @ 11 registers
229
230	.type v7_processor_functions, #object
231	ENTRY(v7_processor_functions)
232	.word v7_early_abort
233	.word pabort_ifar
234	.word cpu_v7_proc_init
235	.word cpu_v7_proc_fin
236	.word cpu_v7_reset
237	.word cpu_v7_do_idle
238	.word cpu_v7_dcache_clean_area
239	.word cpu_v7_switch_mm
240	.word cpu_v7_set_pte_ext
241	.size v7_processor_functions, . - v7_processor_functions
242
243	.type cpu_arch_name, #object
244	cpu_arch_name:
245	.asciz "armv7"
246	.size cpu_arch_name, . - cpu_arch_name
247
248	.type cpu_elf_name, #object
249	cpu_elf_name:
250	.asciz "v7"
251	.size cpu_elf_name, . - cpu_elf_name
252	.align
253
254	.section ".proc.info.init", #alloc, #execinstr
255
256	/*
257	* Match any ARMv7 processor core.
258	*/
259	.type __v7_proc_info, #object
260	__v7_proc_info:
261	.long 0x000f0000 @ Required ID value
262	.long 0x000f0000 @ Mask for ID
263	.long PMD_TYPE_SECT \| \
264	PMD_SECT_BUFFERABLE \| \
265	PMD_SECT_CACHEABLE \| \
266	PMD_SECT_AP_WRITE \| \
267	PMD_SECT_AP_READ
268	.long PMD_TYPE_SECT \| \
269	PMD_SECT_XN \| \
270	PMD_SECT_AP_WRITE \| \
271	PMD_SECT_AP_READ
272	b __v7_setup
273	.long cpu_arch_name
274	.long cpu_elf_name
275	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
276	.long cpu_v7_name
277	.long v7_processor_functions
278	.long v7wbi_tlb_fns
279	.long v6_user_fns
280	.long v7_cache_fns
281	.size __v7_proc_info, . - __v7_proc_info