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[ms2-kexec] / omap2_serial.c
1 /*
2 * arch/arm/mach-omap2/serial.c
3 *
4 * OMAP2 serial support.
5 *
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * Major rework for PM support by Kevin Hilman
10 *
11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial_reg.h>
20 #include <linux/clk.h>
21 #ifdef CONFIG_SERIAL_OMAP
22 #include <linux/platform_device.h>
23 #endif
24 #include <linux/io.h>
25 #include <linux/delay.h>
26 #include <linux/debugfs.h>
27
28 #include <plat/common.h>
29 #include <plat/board.h>
30 #include <plat/clock.h>
31 #include <plat/control.h>
32 #include <mach/gpio.h>
33 #include <plat/omap-serial.h>
34
35 #include <asm/mach/serial_omap.h>
36
37 #include "prm.h"
38 #include "pm.h"
39 #include "prm-regbits-34xx.h"
40
41 #define OMAP_CTRL_REGADDR(reg) (OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE) + (reg))
42
43 static int (*my_pwrdm_clkdm_state_switch)(struct clockdomain *) = (int (*)(struct clockdomain *))0xc0041370;
44
45
46 void omap_ctrl_writew(u16 val, u16 offset)
47 {
48 __raw_writew(val, OMAP_CTRL_REGADDR(offset));
49 }
50
51 u16 omap_ctrl_readw(u16 offset)
52 {
53 return __raw_readw(OMAP_CTRL_REGADDR(offset));
54 }
55
56 #define DEFAULT_TIMEOUT HZ
57
58 struct omap_uart_state {
59 int num;
60 int can_sleep;
61 struct timer_list timer;
62 u32 timeout;
63
64 void __iomem *wk_st;
65 void __iomem *wk_en;
66 u32 wk_mask;
67 u32 padconf;
68
69 u32 rts_padconf;
70 int rts_override;
71 u16 rts_padvalue;
72
73 struct clk *ick;
74 struct clk *fck;
75 int clocked;
76
77 struct plat_serialomap_port *p;
78 struct list_head node;
79
80 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
81 int context_valid;
82
83 /* Registers to be saved/restored for OFF-mode */
84 u16 dll;
85 u16 dlh;
86 u16 ier;
87 u16 sysc;
88 u16 scr;
89 u16 wer;
90 #endif
91 };
92
93 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
94 static LIST_HEAD(uart_list);
95 static unsigned int fifo_idleblks = 0;
96 static int uart0_padconf = 0x180;
97
98 static struct plat_serialomap_port serial_platform_data[] = {
99 {
100 .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART1_BASE),
101 .irq = 72,
102 .regshift = 2,
103 #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
104 .ctsrts = UART_EFR_CTS | UART_EFR_RTS,
105 #endif
106 .flags = UPF_BOOT_AUTOCONF,
107 },
108 {
109 .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART2_BASE),
110 .irq = 73,
111 .regshift = 2,
112 #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
113 .ctsrts = UART_EFR_CTS | UART_EFR_RTS,
114 #endif
115 .flags = UPF_BOOT_AUTOCONF,
116 },
117 {
118 .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART3_BASE),
119 .irq = 74,
120 .regshift = 2,
121 #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL
122 .ctsrts = UART_EFR_RTS,
123 #endif
124 .flags = UPF_BOOT_AUTOCONF,
125 },
126 };
127
128 #if 0
129 static struct resource omap2_uart1_resources[] = {
130 {
131 .start = OMAP_UART1_BASE,
132 .end = OMAP_UART1_BASE + 0x3ff,
133 .flags = IORESOURCE_MEM,
134 }, {
135 .start = 72,
136 .flags = IORESOURCE_IRQ,
137 }
138 };
139
140 static struct resource omap2_uart2_resources[] = {
141 {
142 .start = OMAP_UART2_BASE,
143 .end = OMAP_UART2_BASE + 0x3ff,
144 .flags = IORESOURCE_MEM,
145 }, {
146 .start = 73,
147 .flags = IORESOURCE_IRQ,
148 }
149 };
150 #endif
151
152 static struct resource omap2_uart3_resources[] = {
153 {
154 .start = OMAP_UART3_BASE,
155 .end = OMAP_UART3_BASE + 0x3ff,
156 .flags = IORESOURCE_MEM,
157 }, {
158 .start = 74,
159 .flags = IORESOURCE_IRQ,
160 }
161 };
162
163 #ifdef CONFIG_MACH_OMAP_ZOOM2
164 static struct resource omap2_quaduart_resources[] = {
165 {
166 .start = 0x10000000,
167 .end = 0x10000000 + (0x16 << 1),
168 .flags = IORESOURCE_MEM,
169 }, {
170 .start = OMAP_GPIO_IRQ(102),
171 .flags = IORESOURCE_IRQ,
172 }
173 };
174 #endif
175
176 #if 0
177 /* OMAP UART platform structure */
178 static struct platform_device uart1_device = {
179 .name = "omap-uart",
180 .id = 1,
181 .num_resources = ARRAY_SIZE(omap2_uart1_resources),
182 .resource = omap2_uart1_resources,
183 .dev.platform_data = &serial_platform_data[0],
184 };
185 static struct platform_device uart2_device = {
186 .name = "omap-uart",
187 .id = 2,
188 .num_resources = ARRAY_SIZE(omap2_uart2_resources),
189 .resource = omap2_uart2_resources,
190 .dev.platform_data = &serial_platform_data[1],
191 };
192 #endif
193 static struct platform_device uart3_device = {
194 .name = "omap-uart",
195 .id = 3,
196 .num_resources = ARRAY_SIZE(omap2_uart3_resources),
197 .resource = omap2_uart3_resources,
198 .dev.platform_data = &serial_platform_data[2],
199 };
200
201 static struct platform_device *uart_devices[] = {
202 &uart3_device,
203 };
204
205 static inline unsigned int serial_read_reg(struct plat_serialomap_port *up,
206 int offset)
207 {
208 offset <<= up->regshift;
209 return (unsigned int)__raw_readb(up->membase + offset);
210 }
211
212 static inline void serial_write_reg(struct plat_serialomap_port *p, int offset,
213 int value)
214 {
215 offset <<= p->regshift;
216 __raw_writeb(value, p->membase + offset);
217 }
218
219 /*
220 * Internal UARTs need to be initialized for the 8250 autoconfig to work
221 * properly. Note that the TX watermark initialization may not be needed
222 * once the 8250.c watermark handling code is merged.
223 */
224 static inline void omap_uart_reset(struct omap_uart_state *uart)
225 {
226 struct plat_serialomap_port *p = uart->p;
227
228 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
229 serial_write_reg(p, UART_OMAP_SCR, 0x08);
230 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
231 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
232 }
233
234 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
235 {
236 printk(KERN_INFO "UART clocked?\n");
237 if (uart->clocked)
238 return;
239
240 printk(KERN_INFO "enabling clocks\n");
241 clk_enable(uart->ick);
242 clk_enable(uart->fck);
243
244 if (uart->ick->clkdm != NULL)
245 my_pwrdm_clkdm_state_switch(uart->ick->clkdm);
246
247 if (uart->fck->clkdm != NULL)
248 my_pwrdm_clkdm_state_switch(uart->fck->clkdm);
249
250 uart->clocked = 1;
251 }
252
253 #ifdef CONFIG_PM
254 #ifdef CONFIG_ARCH_OMAP3
255
256 static void omap_uart_save_context(struct omap_uart_state *uart)
257 {
258 u16 lcr = 0;
259 struct plat_serialomap_port *p = uart->p;
260
261 if (!enable_off_mode)
262 return;
263
264 /* FIXME
265 * For omap3430 CORE/PERR OFF isn't temporarily supported,
266 * so no need to save&restore the context of serial.
267 */
268 if (cpu_is_omap34xx())
269 return;
270
271 lcr = serial_read_reg(p, UART_LCR);
272 serial_write_reg(p, UART_LCR, 0xBF);
273 uart->dll = serial_read_reg(p, UART_DLL);
274 uart->dlh = serial_read_reg(p, UART_DLM);
275 serial_write_reg(p, UART_LCR, lcr);
276 uart->ier = serial_read_reg(p, UART_IER);
277 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
278 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
279 uart->wer = serial_read_reg(p, UART_OMAP_WER);
280
281 uart->context_valid = 1;
282 }
283
284 static void omap_uart_restore_context(struct omap_uart_state *uart)
285 {
286 u16 efr = 0;
287 struct plat_serialomap_port *p = uart->p;
288
289 if (!enable_off_mode)
290 return;
291
292 if (!uart->context_valid)
293 return;
294
295 /* FIXME
296 * For omap3430 CORE/PERR OFF isn't temporarily supported,
297 * so no need to save&restore the context of serial.
298 */
299 if (cpu_is_omap34xx())
300 return;
301
302 uart->context_valid = 0;
303
304 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
305 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
306 efr = serial_read_reg(p, UART_EFR);
307 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
308 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
309 serial_write_reg(p, UART_IER, 0x0);
310 #ifdef CONFIG_SERIAL_OMAP
311 serial_write_reg(p, UART_FCR, fcr[uart->num]);
312 #else
313 serial_write_reg(p, UART_FCR, 0xA1);
314 #endif
315 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
316 serial_write_reg(p, UART_DLL, uart->dll);
317 serial_write_reg(p, UART_DLM, uart->dlh);
318 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
319 serial_write_reg(p, UART_IER, uart->ier);
320 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
321 serial_write_reg(p, UART_EFR, efr);
322 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
323 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
324 serial_write_reg(p, UART_OMAP_WER, uart->wer);
325 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
326 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
327 }
328 #else
329 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
330 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
331 #endif /* CONFIG_ARCH_OMAP3 */
332
333 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
334 int enable)
335 {
336 struct plat_serialomap_port *p = uart->p;
337 u16 sysc;
338
339 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
340 if (enable)
341 sysc |= 0x2 << 3;
342 else
343 sysc |= 0x1 << 3;
344
345 serial_write_reg(p, UART_OMAP_SYSC, sysc);
346 }
347
348 static inline void omap_uart_disable_rtspullup(struct omap_uart_state *uart)
349 {
350 if (!uart->rts_padconf || !uart->rts_override)
351 return;
352 omap_ctrl_writew(uart->rts_padvalue, uart->rts_padconf);
353 uart->rts_override = 0;
354 }
355
356 static inline void omap_uart_enable_rtspullup(struct omap_uart_state *uart)
357 {
358 if (!uart->rts_padconf || uart->rts_override)
359 return;
360
361 uart->rts_padvalue = omap_ctrl_readw(uart->rts_padconf);
362 omap_ctrl_writew(0x18 | 0x7, uart->rts_padconf);
363 uart->rts_override = 1;
364 }
365
366 static inline void omap_uart_restore(struct omap_uart_state *uart)
367 {
368 omap_uart_enable_clocks(uart);
369 omap_uart_restore_context(uart);
370 }
371
372 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
373 {
374 if (!uart->clocked)
375 return;
376 omap_uart_save_context(uart);
377 uart->clocked = 0;
378 clk_disable(uart->ick);
379 clk_disable(uart->fck);
380 }
381
382 static void _omap_uart_block_sleep(struct omap_uart_state *uart)
383 {
384 omap_uart_restore(uart);
385
386 omap_uart_smart_idle_enable(uart, 0);
387 uart->can_sleep = 0;
388 if (uart->timeout)
389 mod_timer(&uart->timer, jiffies + uart->timeout);
390 else
391 del_timer(&uart->timer);
392 }
393
394 #if 0
395 static void omap_uart_block_sleep(int num)
396 {
397 struct omap_uart_state *uart;
398
399 list_for_each_entry(uart, &uart_list, node) {
400 if (num == uart->num)
401 _omap_uart_block_sleep(uart);
402 return;
403 }
404 }
405 EXPORT_SYMBOL(omap_uart_block_sleep);
406 #endif
407
408 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
409 {
410 if (!uart->clocked)
411 return;
412
413 omap_uart_smart_idle_enable(uart, 1);
414 uart->can_sleep = 1;
415 del_timer(&uart->timer);
416 }
417
418 static void omap_uart_idle_timer(unsigned long data)
419 {
420 struct omap_uart_state *uart = (struct omap_uart_state *)data;
421
422 omap_uart_allow_sleep(uart);
423 }
424
425 void omap_uart_prepare_idle(int num)
426 {
427 struct omap_uart_state *uart;
428
429 list_for_each_entry(uart, &uart_list, node) {
430 if (num == uart->num && uart->can_sleep) {
431
432 omap_uart_enable_rtspullup(uart);
433 /*
434 * There seems to be a window here where
435 * data could still be on the way to the
436 * fifo. This delay is ~1 byte time @ 115.2k
437 */
438 if (uart->num == 0)
439 udelay(80);
440
441 #ifdef CONFIG_SERIAL_OMAP
442 if (are_driveromap_uarts_active(num)) {
443 fifo_idleblks++;
444 _omap_uart_block_sleep(uart);
445 omap_uart_disable_rtspullup(uart);
446 return;
447 }
448 #endif
449 omap_uart_disable_clocks(uart);
450 return;
451 }
452 }
453 }
454
455 void omap_uart_resume_idle(int num)
456 {
457 struct omap_uart_state *uart;
458
459 list_for_each_entry(uart, &uart_list, node) {
460 if (num == uart->num) {
461 omap_uart_restore(uart);
462 omap_uart_disable_rtspullup(uart);
463
464 /* Check for IO pad wakeup */
465 if (cpu_is_omap34xx() && uart->padconf) {
466 u16 p = omap_ctrl_readw(uart->padconf);
467
468 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
469 _omap_uart_block_sleep(uart);
470 }
471
472 /* Check for normal UART wakeup */
473 if (__raw_readl(uart->wk_st) & uart->wk_mask) {
474 _omap_uart_block_sleep(uart);
475 }
476
477 return;
478 }
479 }
480 }
481
482 void omap_uart_prepare_suspend(void)
483 {
484 struct omap_uart_state *uart;
485
486 list_for_each_entry(uart, &uart_list, node) {
487 omap_uart_allow_sleep(uart);
488 }
489 }
490
491 int omap_uart_can_sleep(void)
492 {
493 struct omap_uart_state *uart;
494 int can_sleep = 1;
495
496 list_for_each_entry(uart, &uart_list, node) {
497 if (!uart->clocked)
498 continue;
499
500 if (!uart->can_sleep) {
501 can_sleep = 0;
502 continue;
503 }
504
505 #ifdef CONFIG_SERIAL_OMAP
506 if (are_driveromap_uarts_active(uart->num)) {
507 can_sleep = 0;
508 continue;
509 }
510 #endif
511
512 /* This UART can now safely sleep. */
513 omap_uart_allow_sleep(uart);
514 }
515
516 return can_sleep;
517 }
518
519 /**
520 * omap_uart_interrupt()
521 *
522 * This handler is used only to detect that *any* UART interrupt has
523 * occurred. It does _nothing_ to handle the interrupt. Rather,
524 * any UART interrupt will trigger the inactivity timer so the
525 * UART will not idle or sleep for its timeout period.
526 *
527 **/
528 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
529 {
530 struct omap_uart_state *uart = dev_id;
531
532 _omap_uart_block_sleep(uart);
533
534 return IRQ_NONE;
535 }
536
537 static u32 sleep_timeout = DEFAULT_TIMEOUT;
538
539 static void omap_uart_rtspad_init(struct omap_uart_state *uart)
540 {
541 if (!cpu_is_omap34xx())
542 return;
543 switch(uart->num) {
544 case 0:
545 uart->rts_padconf = 0x17e;
546 break;
547 case 1:
548 uart->rts_padconf = 0x176;
549 break;
550 case 2:
551 /* uart->rts_padconf = 0x19c; */
552 break;
553 default:
554 uart->rts_padconf = 0;
555 break;
556 }
557 }
558
559 static void omap_uart_idle_init(struct omap_uart_state *uart)
560 {
561 u32 v;
562 struct plat_serialomap_port *p = uart->p;
563 int ret;
564
565 uart->can_sleep = 0;
566 uart->timeout = sleep_timeout;
567 if (!uart->timeout)
568 _omap_uart_block_sleep(uart);
569 else {
570 setup_timer(&uart->timer, omap_uart_idle_timer,
571 (unsigned long) uart);
572 mod_timer(&uart->timer, jiffies + uart->timeout);
573 omap_uart_smart_idle_enable(uart, 0);
574 }
575
576 if (cpu_is_omap34xx()) {
577 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
578 u32 wk_mask = 0;
579 u32 padconf = 0;
580
581 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
582 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
583 switch (uart->num) {
584 case 0:
585 wk_mask = OMAP3430_ST_UART1_MASK;
586 padconf = uart0_padconf;
587 break;
588 case 1:
589 wk_mask = OMAP3430_ST_UART2_MASK;
590 padconf = 0x17a;
591 break;
592 case 2:
593 wk_mask = OMAP3430_ST_UART3_MASK;
594 padconf = 0x19e;
595 break;
596 }
597 uart->wk_mask = wk_mask;
598 uart->padconf = padconf;
599 } else if (cpu_is_omap24xx()) {
600 u32 wk_mask = 0;
601
602 if (cpu_is_omap2430()) {
603 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
604 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
605 } else if (cpu_is_omap2420()) {
606 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
607 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
608 }
609 switch (uart->num) {
610 case 0:
611 wk_mask = OMAP24XX_ST_UART1_MASK;
612 break;
613 case 1:
614 wk_mask = OMAP24XX_ST_UART2_MASK;
615 break;
616 case 2:
617 wk_mask = OMAP24XX_ST_UART3_MASK;
618 break;
619 }
620 uart->wk_mask = wk_mask;
621 } else {
622 uart->wk_en = 0;
623 uart->wk_st = 0;
624 uart->wk_mask = 0;
625 uart->padconf = 0;
626 }
627
628 /* Set wake-enable bit */
629 if (uart->wk_en && uart->wk_mask) {
630 v = __raw_readl(uart->wk_en);
631 v |= uart->wk_mask;
632 __raw_writel(v, uart->wk_en);
633 }
634
635 /* Ensure IOPAD wake-enables are set */
636 if (cpu_is_omap34xx() && uart->padconf) {
637 u16 v;
638
639 v = omap_ctrl_readw(uart->padconf);
640 v |= OMAP3_PADCONF_WAKEUPENABLE0;
641 omap_ctrl_writew(v, uart->padconf);
642 }
643
644 p->flags |= UPF_SHARE_IRQ;
645 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
646 "serial idle", (void *)uart);
647 WARN_ON(ret);
648 }
649
650 void omap_uart_enable_irqs(int enable)
651 {
652 int ret;
653 struct omap_uart_state *uart;
654
655 list_for_each_entry(uart, &uart_list, node) {
656 if (enable)
657 ret = request_irq(uart->p->irq, omap_uart_interrupt,
658 IRQF_SHARED, "serial idle", (void *)uart);
659 else
660 free_irq(uart->p->irq, (void *)uart);
661 }
662 }
663
664 #if 0
665 static ssize_t sleep_timeout_show(struct kobject *kobj,
666 struct kobj_attribute *attr,
667 char *buf)
668 {
669 return sprintf(buf, "%u\n", sleep_timeout / HZ);
670 }
671
672 static ssize_t sleep_timeout_store(struct kobject *kobj,
673 struct kobj_attribute *attr,
674 const char *buf, size_t n)
675 {
676 struct omap_uart_state *uart;
677 unsigned int value;
678
679 if (sscanf(buf, "%u", &value) != 1) {
680 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
681 return -EINVAL;
682 }
683 sleep_timeout = value * HZ;
684 list_for_each_entry(uart, &uart_list, node) {
685 uart->timeout = sleep_timeout;
686 if (uart->timeout)
687 mod_timer(&uart->timer, jiffies + uart->timeout);
688 else
689 /* A zero value means disable timeout feature */
690 _omap_uart_block_sleep(uart);
691 }
692 return n;
693 }
694
695 static struct kobj_attribute sleep_timeout_attr =
696 __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
697 #endif
698
699 #else
700 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
701 #endif /* CONFIG_PM */
702
703 static int fifo_idleblk_get(void *data, u64 *val)
704 {
705 *val = fifo_idleblks;
706 return 0;
707 }
708
709 static int fifo_idleblk_set(void *data, u64 val)
710 {
711 fifo_idleblks = 0;
712 return 0;
713 }
714
715 DEFINE_SIMPLE_ATTRIBUTE(fifo_idleblk_fops, fifo_idleblk_get, fifo_idleblk_set, "%llu\n");
716 void omap_serial_early_init(void)
717 {
718 }
719
720 void omap_serial_ctsrts_init(unsigned char ctsrts[])
721 {
722 #if defined(CONFIG_SERIAL_OMAP) && \
723 defined(CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL)
724 serial_platform_data[0].ctsrts = ctsrts[0];
725 serial_platform_data[1].ctsrts = ctsrts[1];
726 serial_platform_data[2].ctsrts = ctsrts[2];
727 #endif
728 }
729
730 void omap_uart_set_uart0_padconf(int padconf)
731 {
732 uart0_padconf = padconf;
733 }
734
735 void my_omap_serial_init(int wake_gpio_strobe,
736 unsigned int wake_strobe_enable_mask)
737 {
738 int i;
739 char name[16];
740
741 debugfs_create_file("fifo_idle_block_count", 0644, NULL, NULL, &fifo_idleblk_fops);
742 /*
743 * Make sure the serial ports are muxed on at this point.
744 * You have to mux them off in device drivers later on
745 * if not needed.
746 */
747
748 i=2;
749 {
750 struct plat_serialomap_port *p = serial_platform_data + i;
751 struct omap_uart_state *uart = &omap_uart[i];
752
753 if (wake_strobe_enable_mask & (1 << i))
754 p->wake_gpio_strobe = wake_gpio_strobe;
755
756 sprintf(name, "uart%d_ick", i+1);
757 uart->ick = clk_get(NULL, name);
758 if (IS_ERR(uart->ick)) {
759 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
760 uart->ick = NULL;
761 }
762
763 sprintf(name, "uart%d_fck", i+1);
764 uart->fck = clk_get(NULL, name);
765 if (IS_ERR(uart->fck)) {
766 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
767 uart->fck = NULL;
768 }
769
770 if (!uart->ick || !uart->fck)
771 return;
772
773 uart->num = i;
774 p->private_data = uart;
775 uart->p = p;
776 list_add(&uart->node, &uart_list);
777
778 omap_uart_enable_clocks(uart);
779 omap_uart_reset(uart);
780 omap_uart_rtspad_init(uart);
781 omap_uart_idle_init(uart);
782 }
783 }
784
785 int my_omap_hs_init(void)
786 {
787 int ret = 0;
788
789 ret = platform_add_devices(uart_devices, ARRAY_SIZE(uart_devices));
790 if (ret) {
791 printk(KERN_ERR "Error adding uart devices (%d)\n", ret);
792 return ret;
793 }
794 return ret;
795 }
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