]> cvs.zerfleddert.de Git - ms2-kexec/blob - proc-v7.S
Revert "call real kernel_restart_prepare"
[ms2-kexec] / proc-v7.S
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
19
20 #include "proc-macros.S"
21
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
32
33 #ifndef CONFIG_SMP
34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35 #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
36 #define PMD_FLAGS PMD_SECT_WB
37 #else
38 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39 #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40 #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
41 #endif
42
43 ENTRY(cpu_v7_proc_init)
44 mov pc, lr
45 ENDPROC(cpu_v7_proc_init)
46
47 ENTRY(cpu_v7_proc_fin)
48 stmfd sp!, {lr}
49 cpsid if @ disable interrupts
50 bl v7_flush_kern_cache_all
51 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 bic r0, r0, #0x1000 @ ...i............
53 bic r0, r0, #0x0006 @ .............ca.
54 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 ldmfd sp!, {pc}
56 ENDPROC(cpu_v7_proc_fin)
57
58 /*
59 * cpu_v7_reset(loc)
60 *
61 * Perform a soft reset of the system. Put the CPU into the
62 * same state as it would be if it had been reset, and branch
63 * to what would be the reset vector.
64 *
65 * - loc - location to jump to for soft reset
66 *
67 * It is assumed that:
68 */
69 .align 5
70 ENTRY(cpu_v7_reset)
71 mov pc, r0
72 ENDPROC(cpu_v7_reset)
73
74 /*
75 * cpu_v7_do_idle()
76 *
77 * Idle the processor (eg, wait for interrupt).
78 *
79 * IRQs are already disabled.
80 */
81 ENTRY(cpu_v7_do_idle)
82 dsb @ WFI may enter a low-power mode
83 wfi
84 mov pc, lr
85 ENDPROC(cpu_v7_do_idle)
86
87 ENTRY(cpu_v7_dcache_clean_area)
88 #ifndef TLB_CAN_READ_FROM_L1_CACHE
89 dcache_line_size r2, r3
90 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
91 add r0, r0, r2
92 subs r1, r1, r2
93 bhi 1b
94 dsb
95 #endif
96 mov pc, lr
97 ENDPROC(cpu_v7_dcache_clean_area)
98
99 /*
100 * cpu_v7_switch_mm(pgd_phys, tsk)
101 *
102 * Set the translation table base pointer to be pgd_phys
103 *
104 * - pgd_phys - physical address of new TTB
105 *
106 * It is assumed that:
107 * - we are not using split page tables
108 */
109 ENTRY(cpu_v7_switch_mm)
110 #ifdef CONFIG_MMU
111 mov r2, #0
112 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
113 orr r0, r0, #TTB_FLAGS
114 #ifdef CONFIG_ARM_ERRATA_430973
115 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
116 #endif
117 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
118 isb
119 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
120 isb
121 mcr p15, 0, r1, c13, c0, 1 @ set context ID
122 isb
123 #endif
124 mov pc, lr
125 ENDPROC(cpu_v7_switch_mm)
126
127 /*
128 * cpu_v7_set_pte_ext(ptep, pte)
129 *
130 * Set a level 2 translation table entry.
131 *
132 * - ptep - pointer to level 2 translation table entry
133 * (hardware version is stored at -1024 bytes)
134 * - pte - PTE value to store
135 * - ext - value for extended PTE bits
136 */
137 ENTRY(cpu_v7_set_pte_ext)
138 #ifdef CONFIG_MMU
139 ARM( str r1, [r0], #-2048 ) @ linux version
140 THUMB( str r1, [r0] ) @ linux version
141 THUMB( sub r0, r0, #2048 )
142
143 bic r3, r1, #0x000003f0
144 bic r3, r3, #PTE_TYPE_MASK
145 orr r3, r3, r2
146 orr r3, r3, #PTE_EXT_AP0 | 2
147
148 tst r1, #1 << 4
149 orrne r3, r3, #PTE_EXT_TEX(1)
150
151 tst r1, #L_PTE_WRITE
152 tstne r1, #L_PTE_DIRTY
153 orreq r3, r3, #PTE_EXT_APX
154
155 tst r1, #L_PTE_USER
156 orrne r3, r3, #PTE_EXT_AP1
157 tstne r3, #PTE_EXT_APX
158 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
159
160 tst r1, #L_PTE_EXEC
161 orreq r3, r3, #PTE_EXT_XN
162
163 tst r1, #L_PTE_YOUNG
164 tstne r1, #L_PTE_PRESENT
165 moveq r3, #0
166
167 str r3, [r0]
168 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
169 #endif
170 mov pc, lr
171 ENDPROC(cpu_v7_set_pte_ext)
172
173 cpu_v7_name:
174 .ascii "ARMv7 Processor"
175 .align
176
177 __INIT
178
179 /*
180 * __v7_setup
181 *
182 * Initialise TLB, Caches, and MMU state ready to switch the MMU
183 * on. Return in r0 the new CP15 C1 control register setting.
184 *
185 * We automatically detect if we have a Harvard cache, and use the
186 * Harvard cache control instructions insead of the unified cache
187 * control instructions.
188 *
189 * This should be able to cover all ARMv7 cores.
190 *
191 * It is assumed that:
192 * - cache type register is implemented
193 */
194 __v7_setup:
195 #ifdef CONFIG_SMP
196 mrc p15, 0, r0, c1, c0, 1
197 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
198 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
199 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
200 #endif
201 adr r12, __v7_setup_stack @ the local stack
202 stmia r12, {r0-r5, r7, r9, r11, lr}
203 bl v7_flush_dcache_all
204 ldmia r12, {r0-r5, r7, r9, r11, lr}
205
206 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
207 and r10, r0, #0xff000000 @ ARM?
208 teq r10, #0x41000000
209 bne 2f
210 and r5, r0, #0x00f00000 @ variant
211 and r6, r0, #0x0000000f @ revision
212 orr r0, r6, r5, lsr #20-4 @ combine variant and revision
213
214 #ifdef CONFIG_ARM_ERRATA_430973
215 teq r5, #0x00100000 @ only present in r1p*
216 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
217 orreq r10, r10, #(1 << 6) @ set IBE to 1
218 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
219 #endif
220 #ifdef CONFIG_ARM_ERRATA_458693
221 teq r0, #0x20 @ only present in r2p0
222 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
223 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
224 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
225 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
226 #endif
227 #ifdef CONFIG_ARM_ERRATA_460075
228 teq r0, #0x20 @ only present in r2p0
229 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
230 tsteq r10, #1 << 22
231 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
232 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
233 #endif
234
235 2: mov r10, #0
236 #ifdef HARVARD_CACHE
237 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
238 #endif
239 dsb
240 #ifdef CONFIG_MMU
241 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
242 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
243 orr r4, r4, #TTB_FLAGS
244 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
245 mov r10, #0x1f @ domains 0, 1 = manager
246 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
247 /*
248 * Memory region attributes with SCTLR.TRE=1
249 *
250 * n = TEX[0],C,B
251 * TR = PRRR[2n+1:2n] - memory type
252 * IR = NMRR[2n+1:2n] - inner cacheable property
253 * OR = NMRR[2n+17:2n+16] - outer cacheable property
254 *
255 * n TR IR OR
256 * UNCACHED 000 00
257 * BUFFERABLE 001 10 00 00
258 * WRITETHROUGH 010 10 10 10
259 * WRITEBACK 011 10 11 11
260 * reserved 110
261 * WRITEALLOC 111 10 01 01
262 * DEV_SHARED 100 01
263 * DEV_NONSHARED 100 01
264 * DEV_WC 001 10
265 * DEV_CACHED 011 10
266 *
267 * Other attributes:
268 *
269 * DS0 = PRRR[16] = 0 - device shareable property
270 * DS1 = PRRR[17] = 1 - device shareable property
271 * NS0 = PRRR[18] = 0 - normal shareable property
272 * NS1 = PRRR[19] = 1 - normal shareable property
273 * NOS = PRRR[24+n] = 1 - not outer shareable
274 */
275 ldr r5, =0xff0a81a8 @ PRRR
276 ldr r6, =0x40e040e0 @ NMRR
277 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
278 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
279 #endif
280 adr r5, v7_crval
281 ldmia r5, {r5, r6}
282 #ifdef CONFIG_CPU_ENDIAN_BE8
283 orr r6, r6, #1 << 25 @ big-endian page tables
284 #endif
285 mrc p15, 0, r0, c1, c0, 0 @ read control register
286 bic r0, r0, r5 @ clear bits them
287 orr r0, r0, r6 @ set them
288 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
289 mov pc, lr @ return to head.S:__ret
290 ENDPROC(__v7_setup)
291
292 /* AT
293 * TFR EV X F I D LR S
294 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
295 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
296 * 1 0 110 0011 1100 .111 1101 < we want
297 */
298 .type v7_crval, #object
299 v7_crval:
300 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
301
302 __v7_setup_stack:
303 .space 4 * 11 @ 11 registers
304
305 .type v7_processor_functions, #object
306 ENTRY(v7_processor_functions)
307 .word v7_early_abort
308 .word v7_pabort
309 .word cpu_v7_proc_init
310 .word cpu_v7_proc_fin
311 .word cpu_v7_reset
312 .word cpu_v7_do_idle
313 .word cpu_v7_dcache_clean_area
314 .word cpu_v7_switch_mm
315 .word cpu_v7_set_pte_ext
316 .size v7_processor_functions, . - v7_processor_functions
317
318 .type cpu_arch_name, #object
319 cpu_arch_name:
320 .asciz "armv7"
321 .size cpu_arch_name, . - cpu_arch_name
322
323 .type cpu_elf_name, #object
324 cpu_elf_name:
325 .asciz "v7"
326 .size cpu_elf_name, . - cpu_elf_name
327 .align
328
329 .section ".proc.info.init", #alloc, #execinstr
330
331 /*
332 * Match any ARMv7 processor core.
333 */
334 .type __v7_proc_info, #object
335 __v7_proc_info:
336 .long 0x000f0000 @ Required ID value
337 .long 0x000f0000 @ Mask for ID
338 .long PMD_TYPE_SECT | \
339 PMD_SECT_AP_WRITE | \
340 PMD_SECT_AP_READ | \
341 PMD_FLAGS
342 .long PMD_TYPE_SECT | \
343 PMD_SECT_XN | \
344 PMD_SECT_AP_WRITE | \
345 PMD_SECT_AP_READ
346 b __v7_setup
347 .long cpu_arch_name
348 .long cpu_elf_name
349 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
350 .long cpu_v7_name
351 .long v7_processor_functions
352 .long v7wbi_tlb_fns
353 .long v6_user_fns
354 .long v7_cache_fns
355 .size __v7_proc_info, . - __v7_proc_info
Impressum, Datenschutz