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fix broken formatting in command table
[proxmark3-svn] / armsrc / lfops.c
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9bea179a 1//-----------------------------------------------------------------------------\r
2// Miscellaneous routines for low frequency tag operations.\r
3// Tags supported here so far are Texas Instruments (TI), HID\r
4// Also routines for raw mode reading/simulating of LF waveform\r
5//\r
6//-----------------------------------------------------------------------------\r
7#include <proxmark3.h>\r
8#include "apps.h"\r
0fa9ca5b 9#include "hitag2.h"\r
9bea179a 10#include "../common/crc16.c"\r
11\r
6f5cb60c 12int sprintf(char *dest, const char *fmt, ...);\r
13\r
9bea179a 14void AcquireRawAdcSamples125k(BOOL at134khz)\r
15{\r
0d974852 16 if (at134khz)\r
9bea179a 17 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 18 else\r
9bea179a 19 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 20\r
21 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 22\r
23 // Connect the A/D to the peak-detected low-frequency path.\r
24 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
25\r
26 // Give it a bit of time for the resonant antenna to settle.\r
27 SpinDelay(50);\r
28\r
29 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
30 FpgaSetupSsc();\r
31\r
32 // Now call the acquisition routine\r
0d974852 33 DoAcquisition125k();\r
9bea179a 34}\r
35\r
36// split into two routines so we can avoid timing issues after sending commands //\r
0d974852 37void DoAcquisition125k(void)\r
9bea179a 38{\r
39 BYTE *dest = (BYTE *)BigBuf;\r
40 int n = sizeof(BigBuf);\r
41 int i;\r
6f5cb60c 42 \r
0d974852 43 memset(dest, 0, n);\r
9bea179a 44 i = 0;\r
45 for(;;) {\r
6f5cb60c 46 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r
6949aca9 47 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 48 LED_D_ON();\r
49 }\r
0d974852 50 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
6949aca9 51 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 52 i++;\r
53 LED_D_OFF();\r
6f5cb60c 54 if (i >= n) break;\r
9bea179a 55 }\r
56 }\r
1e1b3030 57 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",\r
58 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);\r
9bea179a 59}\r
60\r
0d974852 61void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, BYTE *command)\r
9bea179a 62{\r
63 BOOL at134khz;\r
64\r
0fa9ca5b 65 /* Make sure the tag is reset */\r
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
67 SpinDelay(2500);\r
68 \r
9bea179a 69 // see if 'h' was specified\r
0d974852 70 if (command[strlen((char *) command) - 1] == 'h')\r
71 at134khz = TRUE;\r
9bea179a 72 else\r
0d974852 73 at134khz = FALSE;\r
9bea179a 74\r
0d974852 75 if (at134khz)\r
9bea179a 76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 77 else\r
9bea179a 78 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 79\r
80 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 81\r
82 // Give it a bit of time for the resonant antenna to settle.\r
83 SpinDelay(50);\r
0fa9ca5b 84 // And a little more time for the tag to fully power up\r
85 SpinDelay(2000);\r
9bea179a 86\r
87 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
88 FpgaSetupSsc();\r
89\r
90 // now modulate the reader field\r
0d974852 91 while(*command != '\0' && *command != ' ') {\r
9bea179a 92 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
93 LED_D_OFF();\r
94 SpinDelayUs(delay_off);\r
0d974852 95 if (at134khz)\r
9bea179a 96 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 97 else\r
9bea179a 98 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 99\r
100 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 101 LED_D_ON();\r
0d974852 102 if(*(command++) == '0')\r
9bea179a 103 SpinDelayUs(period_0);\r
0d974852 104 else\r
9bea179a 105 SpinDelayUs(period_1);\r
0d974852 106 }\r
9bea179a 107 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
108 LED_D_OFF();\r
109 SpinDelayUs(delay_off);\r
0d974852 110 if (at134khz)\r
9bea179a 111 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 112 else\r
9bea179a 113 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 114\r
115 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 116\r
117 // now do the read\r
0d974852 118 DoAcquisition125k();\r
9bea179a 119}\r
120\r
7381e8f2 121/* blank r/w tag data stream\r
122...0000000000000000 01111111\r
1231010101010101010101010101010101010101010101010101010101010101010\r
1240011010010100001\r
12501111111\r
126101010101010101[0]000...\r
127\r
128[5555fe852c5555555555555555fe0000]\r
129*/\r
0d974852 130void ReadTItag(void)\r
7381e8f2 131{\r
132 // some hardcoded initial params\r
133 // when we read a TI tag we sample the zerocross line at 2Mhz\r
134 // TI tags modulate a 1 as 16 cycles of 123.2Khz\r
135 // TI tags modulate a 0 as 16 cycles of 134.2Khz\r
136 #define FSAMPLE 2000000\r
137 #define FREQLO 123200\r
138 #define FREQHI 134200\r
139\r
140 signed char *dest = (signed char *)BigBuf;\r
141 int n = sizeof(BigBuf);\r
142// int *dest = GraphBuffer;\r
143// int n = GraphTraceLen;\r
144\r
145 // 128 bit shift register [shift3:shift2:shift1:shift0]\r
146 DWORD shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;\r
147\r
148 int i, cycles=0, samples=0;\r
149 // how many sample points fit in 16 cycles of each frequency\r
150 DWORD sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;\r
151 // when to tell if we're close enough to one freq or another\r
152 DWORD threshold = (sampleslo - sampleshi + 1)>>1;\r
153\r
154 // TI tags charge at 134.2Khz\r
155 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
156\r
157 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
158 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
159 // whether we're modulating the antenna (high)\r
160 // or listening to the antenna (low)\r
161 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
162\r
163 // get TI tag data into the buffer\r
164 AcquireTiType();\r
165\r
166 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
167\r
168 for (i=0; i<n-1; i++) {\r
169 // count cycles by looking for lo to hi zero crossings\r
170 if ( (dest[i]<0) && (dest[i+1]>0) ) {\r
171 cycles++;\r
172 // after 16 cycles, measure the frequency\r
173 if (cycles>15) {\r
174 cycles=0;\r
175 samples=i-samples; // number of samples in these 16 cycles\r
176\r
177 // TI bits are coming to us lsb first so shift them\r
178 // right through our 128 bit right shift register\r
179 shift0 = (shift0>>1) | (shift1 << 31);\r
180 shift1 = (shift1>>1) | (shift2 << 31);\r
181 shift2 = (shift2>>1) | (shift3 << 31);\r
182 shift3 >>= 1;\r
183\r
184 // check if the cycles fall close to the number\r
185 // expected for either the low or high frequency\r
186 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {\r
187 // low frequency represents a 1\r
188 shift3 |= (1<<31);\r
189 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {\r
190 // high frequency represents a 0\r
191 } else {\r
192 // probably detected a gay waveform or noise\r
193 // use this as gaydar or discard shift register and start again\r
194 shift3 = shift2 = shift1 = shift0 = 0;\r
195 }\r
196 samples = i;\r
197\r
198 // for each bit we receive, test if we've detected a valid tag\r
199\r
200 // if we see 17 zeroes followed by 6 ones, we might have a tag\r
201 // remember the bits are backwards\r
202 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {\r
203 // if start and end bytes match, we have a tag so break out of the loop\r
204 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {\r
205 cycles = 0xF0B; //use this as a flag (ugly but whatever)\r
206 break;\r
207 }\r
208 }\r
209 }\r
210 }\r
211 }\r
212\r
213 // if flag is set we have a tag\r
214 if (cycles!=0xF0B) {\r
215 DbpString("Info: No valid tag detected.");\r
216 } else {\r
217 // put 64 bit data into shift1 and shift0\r
218 shift0 = (shift0>>24) | (shift1 << 8);\r
219 shift1 = (shift1>>24) | (shift2 << 8);\r
220\r
221 // align 16 bit crc into lower half of shift2\r
222 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;\r
223\r
224 // if r/w tag, check ident match\r
225 if ( shift3&(1<<15) ) {\r
226 DbpString("Info: TI tag is rewriteable");\r
227 // only 15 bits compare, last bit of ident is not valid\r
228 if ( ((shift3>>16)^shift0)&0x7fff ) {\r
229 DbpString("Error: Ident mismatch!");\r
230 } else {\r
231 DbpString("Info: TI tag ident is valid");\r
232 }\r
233 } else {\r
234 DbpString("Info: TI tag is readonly");\r
235 }\r
236\r
237 // WARNING the order of the bytes in which we calc crc below needs checking\r
238 // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
239 // bytes in reverse or something\r
240 // calculate CRC\r
241 DWORD crc=0;\r
242\r
243 crc = update_crc16(crc, (shift0)&0xff);\r
244 crc = update_crc16(crc, (shift0>>8)&0xff);\r
245 crc = update_crc16(crc, (shift0>>16)&0xff);\r
246 crc = update_crc16(crc, (shift0>>24)&0xff);\r
247 crc = update_crc16(crc, (shift1)&0xff);\r
248 crc = update_crc16(crc, (shift1>>8)&0xff);\r
249 crc = update_crc16(crc, (shift1>>16)&0xff);\r
250 crc = update_crc16(crc, (shift1>>24)&0xff);\r
251\r
1e1b3030 252 Dbprintf("Info: Tag data: %x%08x, crc=%x",\r
6f5cb60c 253 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);\r
7381e8f2 254 if (crc != (shift2&0xffff)) {\r
a9bc033b 255 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);\r
7381e8f2 256 } else {\r
257 DbpString("Info: CRC is good");\r
258 }\r
259 }\r
260}\r
261\r
262void WriteTIbyte(BYTE b)\r
263{\r
264 int i = 0;\r
265\r
266 // modulate 8 bits out to the antenna\r
267 for (i=0; i<8; i++)\r
268 {\r
269 if (b&(1<<i)) {\r
270 // stop modulating antenna\r
6949aca9 271 LOW(GPIO_SSC_DOUT);\r
7381e8f2 272 SpinDelayUs(1000);\r
273 // modulate antenna\r
6949aca9 274 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 275 SpinDelayUs(1000);\r
276 } else {\r
277 // stop modulating antenna\r
6949aca9 278 LOW(GPIO_SSC_DOUT);\r
7381e8f2 279 SpinDelayUs(300);\r
280 // modulate antenna\r
6949aca9 281 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 282 SpinDelayUs(1700);\r
283 }\r
284 }\r
285}\r
286\r
9bea179a 287void AcquireTiType(void)\r
288{\r
7381e8f2 289 int i, j, n;\r
9bea179a 290 // tag transmission is <20ms, sampling at 2M gives us 40K samples max\r
291 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS\r
7381e8f2 292 #define TIBUFLEN 1250\r
9bea179a 293\r
294 // clear buffer\r
295 memset(BigBuf,0,sizeof(BigBuf));\r
296\r
297 // Set up the synchronous serial port\r
6949aca9 298 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;\r
299 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r
9bea179a 300\r
301 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 302 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
0d974852 303 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 304\r
6949aca9 305 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
306 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
9bea179a 307\r
6949aca9 308 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
309 // 48/2 = 24 MHz clock must be divided by 12\r
310 AT91C_BASE_SSC->SSC_CMR = 12;\r
9bea179a 311\r
6949aca9 312 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r
313 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r
314 AT91C_BASE_SSC->SSC_TCMR = 0;\r
315 AT91C_BASE_SSC->SSC_TFMR = 0;\r
9bea179a 316\r
317 LED_D_ON();\r
318\r
319 // modulate antenna\r
6949aca9 320 HIGH(GPIO_SSC_DOUT);\r
9bea179a 321\r
322 // Charge TI tag for 50ms.\r
323 SpinDelay(50);\r
324\r
325 // stop modulating antenna and listen\r
6949aca9 326 LOW(GPIO_SSC_DOUT);\r
9bea179a 327\r
328 LED_D_OFF();\r
329\r
330 i = 0;\r
331 for(;;) {\r
6949aca9 332 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
333 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer\r
334 i++; if(i >= TIBUFLEN) break;\r
335 }\r
336 WDT_HIT();\r
9bea179a 337 }\r
338\r
339 // return stolen pin to SSP\r
6949aca9 340 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
341 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r
9bea179a 342\r
7381e8f2 343 char *dest = (char *)BigBuf;\r
344 n = TIBUFLEN*32;\r
345 // unpack buffer\r
346 for (i=TIBUFLEN-1; i>=0; i--) {\r
7381e8f2 347 for (j=0; j<32; j++) {\r
348 if(BigBuf[i] & (1 << j)) {\r
349 dest[--n] = 1;\r
350 } else {\r
351 dest[--n] = -1;\r
352 }\r
9bea179a 353 }\r
354 }\r
355}\r
356\r
9bea179a 357// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc\r
358// if crc provided, it will be written with the data verbatim (even if bogus)\r
359// if not provided a valid crc will be computed from the data and written.\r
360void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)\r
361{\r
9bea179a 362 if(crc == 0) {\r
363 crc = update_crc16(crc, (idlo)&0xff);\r
364 crc = update_crc16(crc, (idlo>>8)&0xff);\r
365 crc = update_crc16(crc, (idlo>>16)&0xff);\r
366 crc = update_crc16(crc, (idlo>>24)&0xff);\r
367 crc = update_crc16(crc, (idhi)&0xff);\r
368 crc = update_crc16(crc, (idhi>>8)&0xff);\r
369 crc = update_crc16(crc, (idhi>>16)&0xff);\r
370 crc = update_crc16(crc, (idhi>>24)&0xff);\r
371 }\r
1e1b3030 372 Dbprintf("Writing to tag: %x%08x, crc=%x",\r
6f5cb60c 373 (unsigned int) idhi, (unsigned int) idlo, crc);\r
9bea179a 374\r
375 // TI tags charge at 134.2Khz\r
376 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
377 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
378 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
379 // whether we're modulating the antenna (high)\r
380 // or listening to the antenna (low)\r
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
382 LED_A_ON();\r
383\r
384 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 385 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
6f5cb60c 386 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 387\r
388 // writing algorithm:\r
389 // a high bit consists of a field off for 1ms and field on for 1ms\r
390 // a low bit consists of a field off for 0.3ms and field on for 1.7ms\r
391 // initiate a charge time of 50ms (field on) then immediately start writing bits\r
392 // start by writing 0xBB (keyword) and 0xEB (password)\r
393 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)\r
394 // finally end with 0x0300 (write frame)\r
395 // all data is sent lsb firts\r
396 // finish with 15ms programming time\r
397\r
398 // modulate antenna\r
6949aca9 399 HIGH(GPIO_SSC_DOUT);\r
9bea179a 400 SpinDelay(50); // charge time\r
401\r
402 WriteTIbyte(0xbb); // keyword\r
403 WriteTIbyte(0xeb); // password\r
404 WriteTIbyte( (idlo )&0xff );\r
405 WriteTIbyte( (idlo>>8 )&0xff );\r
406 WriteTIbyte( (idlo>>16)&0xff );\r
407 WriteTIbyte( (idlo>>24)&0xff );\r
408 WriteTIbyte( (idhi )&0xff );\r
409 WriteTIbyte( (idhi>>8 )&0xff );\r
410 WriteTIbyte( (idhi>>16)&0xff );\r
411 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo\r
412 WriteTIbyte( (crc )&0xff ); // crc lo\r
413 WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
414 WriteTIbyte(0x00); // write frame lo\r
415 WriteTIbyte(0x03); // write frame hi\r
6949aca9 416 HIGH(GPIO_SSC_DOUT);\r
9bea179a 417 SpinDelay(50); // programming time\r
418\r
419 LED_A_OFF();\r
420\r
421 // get TI tag data into the buffer\r
422 AcquireTiType();\r
423\r
424 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
7381e8f2 425 DbpString("Now use tiread to check");\r
9bea179a 426}\r
427\r
428void SimulateTagLowFrequency(int period, int ledcontrol)\r
429{\r
430 int i;\r
431 BYTE *tab = (BYTE *)BigBuf;\r
432\r
433 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
434\r
6949aca9 435 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r
9bea179a 436\r
6949aca9 437 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
438 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r
9bea179a 439\r
440#define SHORT_COIL() LOW(GPIO_SSC_DOUT)\r
6949aca9 441#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
9bea179a 442\r
443 i = 0;\r
444 for(;;) {\r
6949aca9 445 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r
9bea179a 446 if(BUTTON_PRESS()) {\r
447 DbpString("Stopped");\r
448 return;\r
449 }\r
450 WDT_HIT();\r
451 }\r
452\r
453 if (ledcontrol)\r
454 LED_D_ON();\r
455\r
456 if(tab[i])\r
457 OPEN_COIL();\r
458 else\r
459 SHORT_COIL();\r
460\r
461 if (ledcontrol)\r
462 LED_D_OFF();\r
463\r
6949aca9 464 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r
9bea179a 465 if(BUTTON_PRESS()) {\r
466 DbpString("Stopped");\r
467 return;\r
468 }\r
469 WDT_HIT();\r
470 }\r
471\r
472 i++;\r
473 if(i == period) i = 0;\r
474 }\r
475}\r
476\r
0fa9ca5b 477/* Provides a framework for bidirectional LF tag communication\r
478 * Encoding is currently Hitag2, but the general idea can probably\r
479 * be transferred to other encodings.\r
480 * \r
481 * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME\r
482 * (PA15) a thresholded version of the signal from the ADC. Setting the\r
483 * ADC path to the low frequency peak detection signal, will enable a\r
484 * somewhat reasonable receiver for modulation on the carrier signal\r
485 * that is generated by the reader. The signal is low when the reader\r
486 * field is switched off, and high when the reader field is active. Due\r
487 * to the way that the signal looks like, mostly only the rising edge is\r
488 * useful, your mileage may vary.\r
489 * \r
490 * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also\r
491 * TIOA1, which can be used as the capture input for timer 1. This should\r
492 * make it possible to measure the exact edge-to-edge time, without processor\r
493 * intervention.\r
494 * \r
495 * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)\r
496 * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)\r
497 * \r
498 * The following defines are in carrier periods: \r
499 */\r
500#define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */ \r
501#define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */\r
502#define HITAG_T_EOF 40 /* T_EOF should be > 36 */\r
503#define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */\r
504\r
505static void hitag_handle_frame(int t0, int frame_len, char *frame);\r
506//#define DEBUG_RA_VALUES 1\r
507#define DEBUG_FRAME_CONTENTS 1\r
508void SimulateTagLowFrequencyBidir(int divisor, int t0)\r
509{\r
510#if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS\r
511 int i = 0;\r
512#endif\r
513 char frame[10];\r
514 int frame_pos=0;\r
515 \r
516 DbpString("Starting Hitag2 emulator, press button to end");\r
517 hitag2_init();\r
518 \r
519 /* Set up simulator mode, frequency divisor which will drive the FPGA\r
6949aca9 520 * and analog mux selection.\r
0fa9ca5b 521 */\r
522 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
523 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
524 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
525 RELAY_OFF();\r
526 \r
527 /* Set up Timer 1:\r
528 * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
529 * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
6949aca9 530 * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)\r
0fa9ca5b 531 */\r
532 \r
6949aca9 533 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r
534 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r
535 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r
536 AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |\r
537 AT91C_TC_ETRGEDG_RISING |\r
538 AT91C_TC_ABETRG |\r
539 AT91C_TC_LDRA_RISING |\r
540 AT91C_TC_LDRB_RISING;\r
541 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |\r
542 AT91C_TC_SWTRG;\r
0fa9ca5b 543 \r
544 /* calculate the new value for the carrier period in terms of TC1 values */\r
545 t0 = t0/2;\r
546 \r
547 int overflow = 0;\r
548 while(!BUTTON_PRESS()) {\r
549 WDT_HIT();\r
6949aca9 550 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r
551 int ra = AT91C_BASE_TC1->TC_RA;\r
0fa9ca5b 552 if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;\r
553#if DEBUG_RA_VALUES\r
554 if(ra > 255 || overflow) ra = 255;\r
555 ((char*)BigBuf)[i] = ra;\r
556 i = (i+1) % 8000;\r
557#endif\r
558 \r
559 if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {\r
560 /* Ignore */\r
561 } else if(ra >= t0*HITAG_T_1_MIN ) {\r
562 /* '1' bit */\r
563 if(frame_pos < 8*sizeof(frame)) {\r
564 frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );\r
565 frame_pos++;\r
566 }\r
567 } else if(ra >= t0*HITAG_T_0_MIN) {\r
568 /* '0' bit */\r
569 if(frame_pos < 8*sizeof(frame)) {\r
570 frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );\r
571 frame_pos++;\r
572 }\r
573 }\r
574 \r
575 overflow = 0;\r
576 LED_D_ON();\r
577 } else {\r
6949aca9 578 if(AT91C_BASE_TC1->TC_CV > t0*HITAG_T_EOF) {\r
0fa9ca5b 579 /* Minor nuisance: In Capture mode, the timer can not be\r
580 * stopped by a Compare C. There's no way to stop the clock\r
581 * in software, so we'll just have to note the fact that an\r
582 * overflow happened and the next loaded timer value might\r
583 * have wrapped. Also, this marks the end of frame, and the\r
584 * still running counter can be used to determine the correct\r
6949aca9 585 * time for the start of the reply.\r
0fa9ca5b 586 */ \r
587 overflow = 1;\r
588 \r
589 if(frame_pos > 0) {\r
590 /* Have a frame, do something with it */\r
591#if DEBUG_FRAME_CONTENTS\r
592 ((char*)BigBuf)[i++] = frame_pos;\r
593 memcpy( ((char*)BigBuf)+i, frame, 7);\r
594 i+=7;\r
595 i = i % sizeof(BigBuf);\r
596#endif\r
597 hitag_handle_frame(t0, frame_pos, frame);\r
598 memset(frame, 0, sizeof(frame));\r
599 }\r
600 frame_pos = 0;\r
601\r
602 }\r
603 LED_D_OFF();\r
604 }\r
605 }\r
606 DbpString("All done");\r
607}\r
608\r
609static void hitag_send_bit(int t0, int bit) {\r
610 if(bit == 1) {\r
611 /* Manchester: Loaded, then unloaded */\r
612 LED_A_ON();\r
613 SHORT_COIL();\r
6949aca9 614 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 615 OPEN_COIL();\r
6949aca9 616 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 617 LED_A_OFF();\r
618 } else if(bit == 0) {\r
619 /* Manchester: Unloaded, then loaded */\r
620 LED_B_ON();\r
621 OPEN_COIL();\r
6949aca9 622 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 623 SHORT_COIL();\r
6949aca9 624 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 625 LED_B_OFF();\r
626 }\r
6949aca9 627 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset clock for the next bit */\r
0fa9ca5b 628 \r
629}\r
630static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
631{\r
632 OPEN_COIL();\r
6949aca9 633 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
0fa9ca5b 634 \r
635 /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
636 * not that since the clock counts since the rising edge, but T_wresp is\r
637 * with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
6949aca9 638 * periods. The gap time T_g varies (4..10).\r
0fa9ca5b 639 */\r
6949aca9 640 while(AT91C_BASE_TC1->TC_CV < t0*(fdt-8));\r
0fa9ca5b 641\r
6949aca9 642 int saved_cmr = AT91C_BASE_TC1->TC_CMR;\r
643 AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */\r
644 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */\r
0fa9ca5b 645 \r
646 int i;\r
647 for(i=0; i<5; i++)\r
648 hitag_send_bit(t0, 1); /* Start of frame */\r
649 \r
650 for(i=0; i<frame_len; i++) {\r
651 hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );\r
652 }\r
653 \r
654 OPEN_COIL();\r
6949aca9 655 AT91C_BASE_TC1->TC_CMR = saved_cmr;\r
0fa9ca5b 656}\r
657\r
658/* Callback structure to cleanly separate tag emulation code from the radio layer. */\r
659static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)\r
660{\r
661 hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);\r
662 return 0;\r
663}\r
664/* Frame length in bits, frame contents in MSBit first format */\r
665static void hitag_handle_frame(int t0, int frame_len, char *frame)\r
666{\r
667 hitag2_handle_command(frame, frame_len, hitag_cb, &t0);\r
668}\r
669\r
9bea179a 670// compose fc/8 fc/10 waveform\r
671static void fc(int c, int *n) {\r
672 BYTE *dest = (BYTE *)BigBuf;\r
673 int idx;\r
674\r
675 // for when we want an fc8 pattern every 4 logical bits\r
676 if(c==0) {\r
677 dest[((*n)++)]=1;\r
678 dest[((*n)++)]=1;\r
679 dest[((*n)++)]=0;\r
680 dest[((*n)++)]=0;\r
681 dest[((*n)++)]=0;\r
682 dest[((*n)++)]=0;\r
683 dest[((*n)++)]=0;\r
684 dest[((*n)++)]=0;\r
685 }\r
686 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples\r
687 if(c==8) {\r
688 for (idx=0; idx<6; idx++) {\r
689 dest[((*n)++)]=1;\r
690 dest[((*n)++)]=1;\r
691 dest[((*n)++)]=0;\r
692 dest[((*n)++)]=0;\r
693 dest[((*n)++)]=0;\r
694 dest[((*n)++)]=0;\r
695 dest[((*n)++)]=0;\r
696 dest[((*n)++)]=0;\r
697 }\r
698 }\r
699\r
700 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples\r
701 if(c==10) {\r
702 for (idx=0; idx<5; idx++) {\r
703 dest[((*n)++)]=1;\r
704 dest[((*n)++)]=1;\r
705 dest[((*n)++)]=1;\r
706 dest[((*n)++)]=0;\r
707 dest[((*n)++)]=0;\r
708 dest[((*n)++)]=0;\r
709 dest[((*n)++)]=0;\r
710 dest[((*n)++)]=0;\r
711 dest[((*n)++)]=0;\r
712 dest[((*n)++)]=0;\r
713 }\r
714 }\r
715}\r
716\r
717// prepare a waveform pattern in the buffer based on the ID given then\r
718// simulate a HID tag until the button is pressed\r
719void CmdHIDsimTAG(int hi, int lo, int ledcontrol)\r
720{\r
721 int n=0, i=0;\r
722 /*\r
723 HID tag bitstream format\r
724 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits\r
725 A 1 bit is represented as 6 fc8 and 5 fc10 patterns\r
726 A 0 bit is represented as 5 fc10 and 6 fc8 patterns\r
727 A fc8 is inserted before every 4 bits\r
728 A special start of frame pattern is used consisting a0b0 where a and b are neither 0\r
729 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)\r
730 */\r
731\r
732 if (hi>0xFFF) {\r
733 DbpString("Tags can only have 44 bits.");\r
734 return;\r
735 }\r
736 fc(0,&n);\r
737 // special start of frame marker containing invalid bit sequences\r
738 fc(8, &n); fc(8, &n); // invalid\r
739 fc(8, &n); fc(10, &n); // logical 0\r
740 fc(10, &n); fc(10, &n); // invalid\r
741 fc(8, &n); fc(10, &n); // logical 0\r
742\r
743 WDT_HIT();\r
744 // manchester encode bits 43 to 32\r
745 for (i=11; i>=0; i--) {\r
746 if ((i%4)==3) fc(0,&n);\r
747 if ((hi>>i)&1) {\r
748 fc(10, &n); fc(8, &n); // low-high transition\r
749 } else {\r
750 fc(8, &n); fc(10, &n); // high-low transition\r
751 }\r
752 }\r
753\r
754 WDT_HIT();\r
755 // manchester encode bits 31 to 0\r
756 for (i=31; i>=0; i--) {\r
757 if ((i%4)==3) fc(0,&n);\r
758 if ((lo>>i)&1) {\r
759 fc(10, &n); fc(8, &n); // low-high transition\r
760 } else {\r
761 fc(8, &n); fc(10, &n); // high-low transition\r
762 }\r
763 }\r
764\r
765 if (ledcontrol)\r
766 LED_A_ON();\r
767 SimulateTagLowFrequency(n, ledcontrol);\r
768\r
769 if (ledcontrol)\r
770 LED_A_OFF();\r
771}\r
772\r
773\r
774// loop to capture raw HID waveform then FSK demodulate the TAG ID from it\r
775void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)\r
776{\r
777 BYTE *dest = (BYTE *)BigBuf;\r
778 int m=0, n=0, i=0, idx=0, found=0, lastval=0;\r
779 DWORD hi=0, lo=0;\r
780\r
781 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
782 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
783\r
784 // Connect the A/D to the peak-detected low-frequency path.\r
785 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
786\r
787 // Give it a bit of time for the resonant antenna to settle.\r
788 SpinDelay(50);\r
789\r
790 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
791 FpgaSetupSsc();\r
792\r
793 for(;;) {\r
794 WDT_HIT();\r
795 if (ledcontrol)\r
796 LED_A_ON();\r
797 if(BUTTON_PRESS()) {\r
798 DbpString("Stopped");\r
799 if (ledcontrol)\r
800 LED_A_OFF();\r
801 return;\r
802 }\r
803\r
804 i = 0;\r
805 m = sizeof(BigBuf);\r
806 memset(dest,128,m);\r
807 for(;;) {\r
6949aca9 808 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
809 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 810 if (ledcontrol)\r
811 LED_D_ON();\r
812 }\r
6949aca9 813 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
814 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 815 // we don't care about actual value, only if it's more or less than a\r
816 // threshold essentially we capture zero crossings for later analysis\r
817 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
818 i++;\r
819 if (ledcontrol)\r
820 LED_D_OFF();\r
821 if(i >= m) {\r
822 break;\r
823 }\r
824 }\r
825 }\r
826\r
827 // FSK demodulator\r
828\r
829 // sync to first lo-hi transition\r
830 for( idx=1; idx<m; idx++) {\r
831 if (dest[idx-1]<dest[idx])\r
832 lastval=idx;\r
833 break;\r
834 }\r
835 WDT_HIT();\r
836\r
837 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)\r
838 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere\r
839 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10\r
840 for( i=0; idx<m; idx++) {\r
841 if (dest[idx-1]<dest[idx]) {\r
842 dest[i]=idx-lastval;\r
843 if (dest[i] <= 8) {\r
844 dest[i]=1;\r
845 } else {\r
846 dest[i]=0;\r
847 }\r
848\r
849 lastval=idx;\r
850 i++;\r
851 }\r
852 }\r
853 m=i;\r
854 WDT_HIT();\r
855\r
856 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns\r
857 lastval=dest[0];\r
858 idx=0;\r
859 i=0;\r
860 n=0;\r
861 for( idx=0; idx<m; idx++) {\r
862 if (dest[idx]==lastval) {\r
863 n++;\r
864 } else {\r
865 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,\r
866 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets\r
867 // swallowed up by rounding\r
868 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding\r
869 // special start of frame markers use invalid manchester states (no transitions) by using sequences\r
870 // like 111000\r
871 if (dest[idx-1]) {\r
872 n=(n+1)/6; // fc/8 in sets of 6\r
873 } else {\r
874 n=(n+1)/5; // fc/10 in sets of 5\r
875 }\r
876 switch (n) { // stuff appropriate bits in buffer\r
877 case 0:\r
878 case 1: // one bit\r
879 dest[i++]=dest[idx-1];\r
880 break;\r
881 case 2: // two bits\r
882 dest[i++]=dest[idx-1];\r
883 dest[i++]=dest[idx-1];\r
884 break;\r
885 case 3: // 3 bit start of frame markers\r
886 dest[i++]=dest[idx-1];\r
887 dest[i++]=dest[idx-1];\r
888 dest[i++]=dest[idx-1];\r
889 break;\r
890 // When a logic 0 is immediately followed by the start of the next transmisson\r
891 // (special pattern) a pattern of 4 bit duration lengths is created.\r
892 case 4:\r
893 dest[i++]=dest[idx-1];\r
894 dest[i++]=dest[idx-1];\r
895 dest[i++]=dest[idx-1];\r
896 dest[i++]=dest[idx-1];\r
897 break;\r
898 default: // this shouldn't happen, don't stuff any bits\r
899 break;\r
900 }\r
901 n=0;\r
902 lastval=dest[idx];\r
903 }\r
904 }\r
905 m=i;\r
906 WDT_HIT();\r
907\r
908 // final loop, go over previously decoded manchester data and decode into usable tag ID\r
909 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0\r
910 for( idx=0; idx<m-6; idx++) {\r
911 // search for a start of frame marker\r
912 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
913 {\r
914 found=1;\r
915 idx+=6;\r
916 if (found && (hi|lo)) {\r
1e1b3030 917 Dbprintf("TAG ID: %x%08x (%d)",\r
6f5cb60c 918 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
9bea179a 919 /* if we're only looking for one tag */\r
920 if (findone)\r
921 {\r
922 *high = hi;\r
923 *low = lo;\r
924 return;\r
925 }\r
926 hi=0;\r
927 lo=0;\r
928 found=0;\r
929 }\r
930 }\r
931 if (found) {\r
932 if (dest[idx] && (!dest[idx+1]) ) {\r
933 hi=(hi<<1)|(lo>>31);\r
934 lo=(lo<<1)|0;\r
935 } else if ( (!dest[idx]) && dest[idx+1]) {\r
936 hi=(hi<<1)|(lo>>31);\r
937 lo=(lo<<1)|1;\r
938 } else {\r
939 found=0;\r
940 hi=0;\r
941 lo=0;\r
942 }\r
943 idx++;\r
944 }\r
945 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
946 {\r
947 found=1;\r
948 idx+=6;\r
949 if (found && (hi|lo)) {\r
1e1b3030 950 Dbprintf("TAG ID: %x%08x (%d)",\r
6f5cb60c 951 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
9bea179a 952 /* if we're only looking for one tag */\r
953 if (findone)\r
954 {\r
955 *high = hi;\r
956 *low = lo;\r
957 return;\r
958 }\r
959 hi=0;\r
960 lo=0;\r
961 found=0;\r
962 }\r
963 }\r
964 }\r
965 WDT_HIT();\r
966 }\r
967}\r
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