Added LF frequency adjustments from d18c7db, cleaned up code,

[proxmark3-svn] / fpga / lo_simulate.v

//-----------------------------------------------------------------------------\r
// The way that we connect things in low-frequency simulation mode. In this\r
// case just pass everything through to the ARM, which can bit-bang this\r
// (because it is so slow).\r
//\r
// Jonathan Westhues, April 2006\r
//-----------------------------------------------------------------------------\r
\r
module lo_simulate(\r
    pck0, ck_1356meg, ck_1356megb,\r
    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
    adc_d, adc_clk,\r
    ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
    cross_hi, cross_lo,\r
    dbg\r
);\r
    input pck0, ck_1356meg, ck_1356megb;\r
    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
    input [7:0] adc_d;\r
    output adc_clk;\r
    input ssp_dout;\r
    output ssp_frame, ssp_din, ssp_clk;\r
    input cross_hi, cross_lo;\r
    output dbg;\r
\r
// No logic, straight through.\r
assign pwr_oe3 = 1'b0;\r
assign pwr_oe1 = ssp_dout;\r
assign pwr_oe2 = ssp_dout;\r
assign pwr_oe4 = ssp_dout;\r
assign ssp_clk = cross_lo;\r
assign pwr_lo = 1'b0;\r
assign adc_clk = 1'b0;\r
assign pwr_hi = 1'b0;\r
assign dbg = cross_lo;\r
\r
endmodule\r