]> cvs.zerfleddert.de Git - proxmark3-svn/blame - armsrc/lfops.c
projects / proxmark3-svn / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
FIX: adding a test to see if we managed to get the correct demodulation from an...
[proxmark3-svn] / armsrc / lfops.c
CommitLineData
15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
15c4dc5a 6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
15c4dc5a 12#include "apps.h"
f7e3ed82 13#include "util.h"
15c4dc5a 14#include "hitag2.h"
15#include "crc16.h"
9ab7a6c7 16#include "string.h"
7db5f1ca 17#include "lfdemod.h"
31abe49f 18#include "lfsampling.h"
f7048dc8 19#include "usb_cdc.h"
15c4dc5a 20
b2256785
MHS		 21
22/**
31abe49f
MHS		 23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
7c676e72 28 */
f7e3ed82 29void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
15c4dc5a 30{
15c4dc5a 31
ae8e8a43
MHS		 32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
b2256785 34
ae8e8a43
MHS		 35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
15c4dc5a 37
31abe49f
MHS		 38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
15c4dc5a 40
2b61c242 41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
b2256785 45
31abe49f 46 LFSetupFPGAForADC(sc.divisor, 1);
b2256785 47
ae8e8a43
MHS		 48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
15c4dc5a 50
ae8e8a43
MHS		 51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
31abe49f 56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
15c4dc5a 57
ae8e8a43
MHS		 58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
31abe49f 68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
15c4dc5a 69
ae8e8a43 70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
15c4dc5a 71
ae8e8a43 72 // now do the read
31abe49f 73 DoAcquisition_config(false);
15c4dc5a 74}
75
76/* blank r/w tag data stream
77...0000000000000000 01111111
781010101010101010101010101010101010101010101010101010101010101010
790011010010100001
8001111111
81101010101010101[0]000...
82
83[5555fe852c5555555555555555fe0000]
84*/
85void ReadTItag(void)
86{
ae8e8a43
MHS		 87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
ba1a299c 91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
ae8e8a43 94
117d9ec2 95 signed char *dest = (signed char *)BigBuf_get_addr();
f71f4deb 96 uint16_t n = BigBuf_max_traceLen();
ae8e8a43
MHS		 97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
ba1a299c 178 if (shift3 & (1<<15) ) {
ae8e8a43
MHS		 179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
ba1a299c 181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
ae8e8a43
MHS		 182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x",
206 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
207 if (crc != (shift2&0xffff)) {
208 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
209 } else {
210 DbpString("Info: CRC is good");
211 }
212 }
15c4dc5a 213}
214
f7e3ed82 215void WriteTIbyte(uint8_t b)
15c4dc5a 216{
ae8e8a43
MHS		 217 int i = 0;
218
219 // modulate 8 bits out to the antenna
220 for (i=0; i<8; i++)
221 {
222 if (b&(1<<i)) {
223 // stop modulating antenna
224 LOW(GPIO_SSC_DOUT);
225 SpinDelayUs(1000);
226 // modulate antenna
227 HIGH(GPIO_SSC_DOUT);
228 SpinDelayUs(1000);
229 } else {
230 // stop modulating antenna
231 LOW(GPIO_SSC_DOUT);
232 SpinDelayUs(300);
233 // modulate antenna
234 HIGH(GPIO_SSC_DOUT);
235 SpinDelayUs(1700);
236 }
237 }
15c4dc5a 238}
239
240void AcquireTiType(void)
241{
ae8e8a43
MHS		 242 int i, j, n;
243 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
244 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
ba1a299c 245 #define TIBUFLEN 1250
ae8e8a43
MHS		 246
247 // clear buffer
117d9ec2 248 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
f71f4deb 249 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
ae8e8a43
MHS		 250
251 // Set up the synchronous serial port
252 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
253 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
254
255 // steal this pin from the SSP and use it to control the modulation
256 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
257 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
258
259 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
261
262 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
263 // 48/2 = 24 MHz clock must be divided by 12
264 AT91C_BASE_SSC->SSC_CMR = 12;
265
266 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
267 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
268 AT91C_BASE_SSC->SSC_TCMR = 0;
269 AT91C_BASE_SSC->SSC_TFMR = 0;
270
271 LED_D_ON();
272
273 // modulate antenna
274 HIGH(GPIO_SSC_DOUT);
275
276 // Charge TI tag for 50ms.
277 SpinDelay(50);
278
279 // stop modulating antenna and listen
280 LOW(GPIO_SSC_DOUT);
281
282 LED_D_OFF();
283
284 i = 0;
285 for(;;) {
286 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
287 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
288 i++; if(i >= TIBUFLEN) break;
289 }
290 WDT_HIT();
291 }
292
293 // return stolen pin to SSP
294 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
295 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
296
117d9ec2 297 char *dest = (char *)BigBuf_get_addr();
ae8e8a43
MHS		 298 n = TIBUFLEN*32;
299 // unpack buffer
300 for (i=TIBUFLEN-1; i>=0; i--) {
301 for (j=0; j<32; j++) {
302 if(BigBuf[i] & (1 << j)) {
303 dest[--n] = 1;
304 } else {
305 dest[--n] = -1;
306 }
307 }
308 }
15c4dc5a 309}
310
311// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
312// if crc provided, it will be written with the data verbatim (even if bogus)
313// if not provided a valid crc will be computed from the data and written.
f7e3ed82 314void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
15c4dc5a 315{
ae8e8a43
MHS		 316 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
317 if(crc == 0) {
318 crc = update_crc16(crc, (idlo)&0xff);
319 crc = update_crc16(crc, (idlo>>8)&0xff);
320 crc = update_crc16(crc, (idlo>>16)&0xff);
321 crc = update_crc16(crc, (idlo>>24)&0xff);
322 crc = update_crc16(crc, (idhi)&0xff);
323 crc = update_crc16(crc, (idhi>>8)&0xff);
324 crc = update_crc16(crc, (idhi>>16)&0xff);
325 crc = update_crc16(crc, (idhi>>24)&0xff);
326 }
327 Dbprintf("Writing to tag: %x%08x, crc=%x",
328 (unsigned int) idhi, (unsigned int) idlo, crc);
329
330 // TI tags charge at 134.2Khz
331 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
332 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
333 // connects to SSP_DIN and the SSP_DOUT logic level controls
334 // whether we're modulating the antenna (high)
335 // or listening to the antenna (low)
336 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
337 LED_A_ON();
338
339 // steal this pin from the SSP and use it to control the modulation
340 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
341 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
342
343 // writing algorithm:
344 // a high bit consists of a field off for 1ms and field on for 1ms
345 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
346 // initiate a charge time of 50ms (field on) then immediately start writing bits
347 // start by writing 0xBB (keyword) and 0xEB (password)
348 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
349 // finally end with 0x0300 (write frame)
350 // all data is sent lsb firts
351 // finish with 15ms programming time
352
353 // modulate antenna
354 HIGH(GPIO_SSC_DOUT);
355 SpinDelay(50); // charge time
356
357 WriteTIbyte(0xbb); // keyword
358 WriteTIbyte(0xeb); // password
359 WriteTIbyte( (idlo )&0xff );
360 WriteTIbyte( (idlo>>8 )&0xff );
361 WriteTIbyte( (idlo>>16)&0xff );
362 WriteTIbyte( (idlo>>24)&0xff );
363 WriteTIbyte( (idhi )&0xff );
364 WriteTIbyte( (idhi>>8 )&0xff );
365 WriteTIbyte( (idhi>>16)&0xff );
366 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
367 WriteTIbyte( (crc )&0xff ); // crc lo
368 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
369 WriteTIbyte(0x00); // write frame lo
370 WriteTIbyte(0x03); // write frame hi
371 HIGH(GPIO_SSC_DOUT);
372 SpinDelay(50); // programming time
373
374 LED_A_OFF();
375
376 // get TI tag data into the buffer
377 AcquireTiType();
378
379 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
380 DbpString("Now use tiread to check");
15c4dc5a 381}
382
385f3987 383void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)
15c4dc5a 384{
ae8e8a43 385 int i;
117d9ec2 386 uint8_t *tab = BigBuf_get_addr();
ba1a299c 387
ae8e8a43
MHS		 388 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
389 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
ba1a299c 390
ae8e8a43 391 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
ba1a299c 392
ae8e8a43
MHS		 393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
ba1a299c 395
e09f21fa 396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
ba1a299c 398
ae8e8a43
MHS		 399 i = 0;
400 for(;;) {
e09f21fa 401 //wait until SSC_CLK goes HIGH
ae8e8a43 402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
f7048dc8 403 if(BUTTON_PRESS() || usb_poll()) {
ae8e8a43
MHS		 404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
ae8e8a43
MHS		 409 if (ledcontrol)
410 LED_D_ON();
952a8bb5 411
ae8e8a43
MHS		 412 if(tab[i])
413 OPEN_COIL();
414 else
415 SHORT_COIL();
952a8bb5 416
ae8e8a43
MHS		 417 if (ledcontrol)
418 LED_D_OFF();
e09f21fa 419 //wait until SSC_CLK goes LOW
ae8e8a43
MHS		 420 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
421 if(BUTTON_PRESS()) {
422 DbpString("Stopped");
423 return;
424 }
425 WDT_HIT();
e09f21fa 426 }
427
ae8e8a43
MHS		 428 i++;
429 if(i == period) {
e09f21fa 430
ae8e8a43
MHS		 431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
15c4dc5a 438}
439
15c4dc5a 440#define DEBUG_FRAME_CONTENTS 1
441void SimulateTagLowFrequencyBidir(int divisor, int t0)
442{
15c4dc5a 443}
444
e09f21fa 445// compose fc/8 fc/10 waveform (FSK2)
446static void fc(int c, int *n)
447{
117d9ec2 448 uint8_t *dest = BigBuf_get_addr();
ae8e8a43
MHS		 449 int idx;
450
451 // for when we want an fc8 pattern every 4 logical bits
452 if(c==0) {
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
e09f21fa 455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
ae8e8a43
MHS		 457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 }
e09f21fa 462
712ebfa6 463 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
ae8e8a43
MHS		 464 if(c==8) {
465 for (idx=0; idx<6; idx++) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
e09f21fa 468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
ae8e8a43
MHS		 470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475 }
476
712ebfa6 477 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
ae8e8a43
MHS		 478 if(c==10) {
479 for (idx=0; idx<5; idx++) {
e09f21fa 480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
ae8e8a43
MHS		 482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
ae8e8a43
MHS		 490 }
491 }
15c4dc5a 492}
e09f21fa 493// compose fc/X fc/Y waveform (FSKx)
712ebfa6 494static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 495{
496 uint8_t *dest = BigBuf_get_addr();
712ebfa6 497 uint8_t halfFC = fc/2;
498 uint8_t wavesPerClock = clock/fc;
499 uint8_t mod = clock % fc; //modifier
500 uint8_t modAdj = fc/mod; //how often to apply modifier
501 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
e09f21fa 502 // loop through clock - step field clock
712ebfa6 503 for (uint8_t idx=0; idx < wavesPerClock; idx++){
504 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
506 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
507 *n += fc;
e09f21fa 508 }
509 if (mod>0) (*modCnt)++;
510 if ((mod>0) && modAdjOk){ //fsk2
511 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
712ebfa6 512 memset(dest+(*n), 0, fc-halfFC);
513 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
514 *n += fc;
e09f21fa 515 }
516 }
e09f21fa 517 if (mod>0 && !modAdjOk){ //fsk1
712ebfa6 518 memset(dest+(*n), 0, mod-(mod/2));
519 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
520 *n += mod;
e09f21fa 521 }
522}
15c4dc5a 523
524// prepare a waveform pattern in the buffer based on the ID given then
525// simulate a HID tag until the button is pressed
526void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
527{
ae8e8a43
MHS		 528 int n=0, i=0;
529 /*
530 HID tag bitstream format
531 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
532 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
533 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
534 A fc8 is inserted before every 4 bits
535 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
536 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
537 */
538
539 if (hi>0xFFF) {
78f5b1a7 540 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
ae8e8a43
MHS		 541 return;
542 }
543 fc(0,&n);
544 // special start of frame marker containing invalid bit sequences
545 fc(8, &n); fc(8, &n); // invalid
546 fc(8, &n); fc(10, &n); // logical 0
547 fc(10, &n); fc(10, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549
550 WDT_HIT();
551 // manchester encode bits 43 to 32
552 for (i=11; i>=0; i--) {
553 if ((i%4)==3) fc(0,&n);
554 if ((hi>>i)&1) {
555 fc(10, &n); fc(8, &n); // low-high transition
556 } else {
557 fc(8, &n); fc(10, &n); // high-low transition
558 }
559 }
560
561 WDT_HIT();
562 // manchester encode bits 31 to 0
563 for (i=31; i>=0; i--) {
564 if ((i%4)==3) fc(0,&n);
565 if ((lo>>i)&1) {
566 fc(10, &n); fc(8, &n); // low-high transition
567 } else {
568 fc(8, &n); fc(10, &n); // high-low transition
569 }
570 }
571
572 if (ledcontrol)
573 LED_A_ON();
574 SimulateTagLowFrequency(n, 0, ledcontrol);
575
576 if (ledcontrol)
577 LED_A_OFF();
15c4dc5a 578}
eb191de6 579
e09f21fa 580// prepare a waveform pattern in the buffer based on the ID given then
581// simulate a FSK tag until the button is pressed
582// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
583void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
584{
585 int ledcontrol=1;
586 int n=0, i=0;
587 uint8_t fcHigh = arg1 >> 8;
588 uint8_t fcLow = arg1 & 0xFF;
589 uint16_t modCnt = 0;
e09f21fa 590 uint8_t clk = arg2 & 0xFF;
591 uint8_t invert = (arg2 >> 8) & 1;
712ebfa6 592
e09f21fa 593 for (i=0; i<size; i++){
594 if (BitStream[i] == invert){
595 fcAll(fcLow, &n, clk, &modCnt);
596 } else {
597 fcAll(fcHigh, &n, clk, &modCnt);
598 }
599 }
600 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
712ebfa6 601 /*Dbprintf("DEBUG: First 32:");
e09f21fa 602 uint8_t *dest = BigBuf_get_addr();
603 i=0;
604 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
605 i+=16;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
78f5b1a7 607 */
e09f21fa 608 if (ledcontrol)
609 LED_A_ON();
712ebfa6 610
78f5b1a7 611 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 612
613 if (ledcontrol)
614 LED_A_OFF();
615}
616
617// compose ask waveform for one bit(ASK)
618static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
619{
620 uint8_t *dest = BigBuf_get_addr();
712ebfa6 621 uint8_t halfClk = clock/2;
e09f21fa 622 // c = current bit 1 or 0
712ebfa6 623 if (manchester){
624 memset(dest+(*n), c, halfClk);
625 memset(dest+(*n) + halfClk, c^1, halfClk);
e09f21fa 626 } else {
712ebfa6 627 memset(dest+(*n), c, clock);
e09f21fa 628 }
712ebfa6 629 *n += clock;
e09f21fa 630}
631
632// args clock, ask/man or askraw, invert, transmission separator
633void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
634{
635 int ledcontrol = 1;
636 int n=0, i=0;
637 uint8_t clk = (arg1 >> 8) & 0xFF;
638 uint8_t manchester = arg1 & 1;
639 uint8_t separator = arg2 & 1;
640 uint8_t invert = (arg2 >> 8) & 1;
e09f21fa 641 for (i=0; i<size; i++){
642 askSimBit(BitStream[i]^invert, &n, clk, manchester);
643 }
ada339a1 644 if (manchester==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
645 for (i=0; i<size; i++){
646 askSimBit(BitStream[i]^invert^1, &n, clk, manchester);
647 }
648 }
712ebfa6 649 if (separator==1) Dbprintf("sorry but separator option not yet available");
e09f21fa 650
651 Dbprintf("Simulating with clk: %d, invert: %d, manchester: %d, separator: %d, n: %d",clk, invert, manchester, separator, n);
652 //DEBUG
712ebfa6 653 //Dbprintf("First 32:");
e09f21fa 654 //uint8_t *dest = BigBuf_get_addr();
655 //i=0;
656 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
657 //i+=16;
658 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 659
660 if (ledcontrol)
661 LED_A_ON();
712ebfa6 662
78f5b1a7 663 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 664
665 if (ledcontrol)
666 LED_A_OFF();
667}
668
669//carrier can be 2,4 or 8
670static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
671{
672 uint8_t *dest = BigBuf_get_addr();
712ebfa6 673 uint8_t halfWave = waveLen/2;
674 //uint8_t idx;
e09f21fa 675 int i = 0;
676 if (phaseChg){
677 // write phase change
712ebfa6 678 memset(dest+(*n), *curPhase^1, halfWave);
679 memset(dest+(*n) + halfWave, *curPhase, halfWave);
680 *n += waveLen;
e09f21fa 681 *curPhase ^= 1;
712ebfa6 682 i += waveLen;
e09f21fa 683 }
684 //write each normal clock wave for the clock duration
685 for (; i < clk; i+=waveLen){
712ebfa6 686 memset(dest+(*n), *curPhase, halfWave);
687 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
688 *n += waveLen;
e09f21fa 689 }
690}
691
692// args clock, carrier, invert,
693void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
694{
695 int ledcontrol=1;
696 int n=0, i=0;
697 uint8_t clk = arg1 >> 8;
698 uint8_t carrier = arg1 & 0xFF;
699 uint8_t invert = arg2 & 0xFF;
78f5b1a7 700 uint8_t curPhase = 0;
e09f21fa 701 for (i=0; i<size; i++){
702 if (BitStream[i] == curPhase){
703 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
704 } else {
705 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
706 }
707 }
708 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
712ebfa6 709 //Dbprintf("DEBUG: First 32:");
710 //uint8_t *dest = BigBuf_get_addr();
711 //i=0;
712 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
713 //i+=16;
714 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 715
716 if (ledcontrol)
717 LED_A_ON();
78f5b1a7 718 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 719
720 if (ledcontrol)
721 LED_A_OFF();
722}
723
b3b70669 724// loop to get raw HID waveform then FSK demodulate the TAG ID from it
69d88ec4
MHS		 725void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
726{
117d9ec2 727 uint8_t *dest = BigBuf_get_addr();
08ebca68 728 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
729 size_t size = 0;
ae8e8a43 730 uint32_t hi2=0, hi=0, lo=0;
a1d17964 731 int idx=0;
ae8e8a43
MHS		 732 // Configure to go in 125Khz listen mode
733 LFSetupFPGAForADC(95, true);
734
735 while(!BUTTON_PRESS()) {
736
737 WDT_HIT();
738 if (ledcontrol) LED_A_ON();
739
31abe49f 740 DoAcquisition_default(-1,true);
ae8e8a43 741 // FSK demodulator
08ebca68 742 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
a1d17964 743 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
744
ec75f5c1 745 if (idx>0 && lo>0){
ae8e8a43
MHS		 746 // final loop, go over previously decoded manchester data and decode into usable tag ID
747 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
748 if (hi2 != 0){ //extra large HID tags
749 Dbprintf("TAG ID: %x%08x%08x (%d)",
750 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
751 }else { //standard HID tags <38 bits
752 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
753 uint8_t bitlen = 0;
754 uint32_t fc = 0;
755 uint32_t cardnum = 0;
ba1a299c 756 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
ae8e8a43
MHS		 757 uint32_t lo2=0;
758 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
759 uint8_t idx3 = 1;
ba1a299c 760 while(lo2 > 1){ //find last bit set to 1 (format len bit)
761 lo2=lo2 >> 1;
ae8e8a43
MHS		 762 idx3++;
763 }
ba1a299c 764 bitlen = idx3+19;
ae8e8a43
MHS		 765 fc =0;
766 cardnum=0;
ba1a299c 767 if(bitlen == 26){
ae8e8a43
MHS		 768 cardnum = (lo>>1)&0xFFFF;
769 fc = (lo>>17)&0xFF;
770 }
ba1a299c 771 if(bitlen == 37){
ae8e8a43
MHS		 772 cardnum = (lo>>1)&0x7FFFF;
773 fc = ((hi&0xF)<<12)|(lo>>20);
774 }
ba1a299c 775 if(bitlen == 34){
ae8e8a43
MHS		 776 cardnum = (lo>>1)&0xFFFF;
777 fc= ((hi&1)<<15)|(lo>>17);
778 }
ba1a299c 779 if(bitlen == 35){
ae8e8a43
MHS		 780 cardnum = (lo>>1)&0xFFFFF;
781 fc = ((hi&1)<<11)|(lo>>21);
782 }
783 }
784 else { //if bit 38 is not set then 37 bit format is used
785 bitlen= 37;
786 fc =0;
787 cardnum=0;
788 if(bitlen==37){
789 cardnum = (lo>>1)&0x7FFFF;
790 fc = ((hi&0xF)<<12)|(lo>>20);
791 }
792 }
793 //Dbprintf("TAG ID: %x%08x (%d)",
794 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
795 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
796 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
797 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
798 }
799 if (findone){
800 if (ledcontrol) LED_A_OFF();
0892b968 801 *high = hi;
802 *low = lo;
ae8e8a43
MHS		 803 return;
804 }
805 // reset
806 hi2 = hi = lo = 0;
807 }
808 WDT_HIT();
ae8e8a43
MHS		 809 }
810 DbpString("Stopped");
811 if (ledcontrol) LED_A_OFF();
eb191de6 812}
813
66707a3b 814void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
eb191de6 815{
117d9ec2 816 uint8_t *dest = BigBuf_get_addr();
ae8e8a43 817
ec75f5c1 818 size_t size=0, idx=0;
e770c648 819 int clk=0, invert=0, errCnt=0, maxErr=20;
ae8e8a43
MHS		 820 uint64_t lo=0;
821 // Configure to go in 125Khz listen mode
822 LFSetupFPGAForADC(95, true);
823
824 while(!BUTTON_PRESS()) {
825
826 WDT_HIT();
827 if (ledcontrol) LED_A_ON();
828
31abe49f 829 DoAcquisition_default(-1,true);
f71f4deb 830 size = BigBuf_max_traceLen();
ae8e8a43 831 //Dbprintf("DEBUG: Buffer got");
d91a31f9 832 //askdemod and manchester decode
e770c648 833 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
ae8e8a43
MHS		 834 //Dbprintf("DEBUG: ASK Got");
835 WDT_HIT();
836
837 if (errCnt>=0){
ec75f5c1 838 lo = Em410xDecode(dest, &size, &idx);
ae8e8a43 839 //Dbprintf("DEBUG: EM GOT");
ae8e8a43 840 if (lo>0){
d91a31f9 841 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
842 (uint32_t)(lo>>32),
843 (uint32_t)lo,
844 (uint32_t)(lo&0xFFFF),
845 (uint32_t)((lo>>16LL) & 0xFF),
846 (uint32_t)(lo & 0xFFFFFF));
ae8e8a43
MHS		 847 }
848 if (findone){
849 if (ledcontrol) LED_A_OFF();
0892b968 850 *high=lo>>32;
851 *low=lo & 0xFFFFFFFF;
ae8e8a43
MHS		 852 return;
853 }
854 } else{
855 //Dbprintf("DEBUG: No Tag");
856 }
857 WDT_HIT();
858 lo = 0;
859 clk=0;
860 invert=0;
861 errCnt=0;
862 size=0;
ae8e8a43
MHS		 863 }
864 DbpString("Stopped");
865 if (ledcontrol) LED_A_OFF();
15c4dc5a 866}
69d88ec4 867
a1f3bb12 868void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
eb191de6 869{
117d9ec2 870 uint8_t *dest = BigBuf_get_addr();
ae8e8a43
MHS		 871 int idx=0;
872 uint32_t code=0, code2=0;
873 uint8_t version=0;
874 uint8_t facilitycode=0;
875 uint16_t number=0;
876 // Configure to go in 125Khz listen mode
877 LFSetupFPGAForADC(95, true);
878
879 while(!BUTTON_PRESS()) {
880 WDT_HIT();
881 if (ledcontrol) LED_A_ON();
31abe49f 882 DoAcquisition_default(-1,true);
ae8e8a43
MHS		 883 //fskdemod and get start index
884 WDT_HIT();
f71f4deb 885 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
ae8e8a43
MHS		 886 if (idx>0){
887 //valid tag found
888
889 //Index map
890 //0 10 20 30 40 50 60
891 //| | | | | | |
892 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
893 //-----------------------------------------------------------------------------
894 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
895 //
896 //XSF(version)facility:codeone+codetwo
897 //Handle the data
898 if(findone){ //only print binary if we are doing one
899 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
900 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
901 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
902 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
903 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
904 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
905 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
906 }
907 code = bytebits_to_byte(dest+idx,32);
908 code2 = bytebits_to_byte(dest+idx+32,32);
909 version = bytebits_to_byte(dest+idx+27,8); //14,4
910 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
911 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
912
913 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
914 // if we're only looking for one tag
915 if (findone){
916 if (ledcontrol) LED_A_OFF();
917 //LED_A_OFF();
0892b968 918 *high=code;
919 *low=code2;
ae8e8a43
MHS		 920 return;
921 }
922 code=code2=0;
923 version=facilitycode=0;
924 number=0;
925 idx=0;
926 }
927 WDT_HIT();
928 }
929 DbpString("Stopped");
930 if (ledcontrol) LED_A_OFF();
eb191de6 931}
a1f3bb12 932
2d4eae76 933/*------------------------------
934 * T5555/T5557/T5567 routines
935 *------------------------------
936 */
937
938/* T55x7 configuration register definitions */
939#define T55x7_POR_DELAY 0x00000001
940#define T55x7_ST_TERMINATOR 0x00000008
941#define T55x7_PWD 0x00000010
942#define T55x7_MAXBLOCK_SHIFT 5
943#define T55x7_AOR 0x00000200
944#define T55x7_PSKCF_RF_2 0
945#define T55x7_PSKCF_RF_4 0x00000400
946#define T55x7_PSKCF_RF_8 0x00000800
947#define T55x7_MODULATION_DIRECT 0
948#define T55x7_MODULATION_PSK1 0x00001000
949#define T55x7_MODULATION_PSK2 0x00002000
950#define T55x7_MODULATION_PSK3 0x00003000
951#define T55x7_MODULATION_FSK1 0x00004000
952#define T55x7_MODULATION_FSK2 0x00005000
953#define T55x7_MODULATION_FSK1a 0x00006000
954#define T55x7_MODULATION_FSK2a 0x00007000
955#define T55x7_MODULATION_MANCHESTER 0x00008000
956#define T55x7_MODULATION_BIPHASE 0x00010000
957#define T55x7_BITRATE_RF_8 0
958#define T55x7_BITRATE_RF_16 0x00040000
959#define T55x7_BITRATE_RF_32 0x00080000
960#define T55x7_BITRATE_RF_40 0x000C0000
961#define T55x7_BITRATE_RF_50 0x00100000
962#define T55x7_BITRATE_RF_64 0x00140000
963#define T55x7_BITRATE_RF_100 0x00180000
964#define T55x7_BITRATE_RF_128 0x001C0000
965
966/* T5555 (Q5) configuration register definitions */
967#define T5555_ST_TERMINATOR 0x00000001
968#define T5555_MAXBLOCK_SHIFT 0x00000001
969#define T5555_MODULATION_MANCHESTER 0
970#define T5555_MODULATION_PSK1 0x00000010
971#define T5555_MODULATION_PSK2 0x00000020
972#define T5555_MODULATION_PSK3 0x00000030
973#define T5555_MODULATION_FSK1 0x00000040
974#define T5555_MODULATION_FSK2 0x00000050
975#define T5555_MODULATION_BIPHASE 0x00000060
976#define T5555_MODULATION_DIRECT 0x00000070
977#define T5555_INVERT_OUTPUT 0x00000080
978#define T5555_PSK_RF_2 0
979#define T5555_PSK_RF_4 0x00000100
980#define T5555_PSK_RF_8 0x00000200
981#define T5555_USE_PWD 0x00000400
982#define T5555_USE_AOR 0x00000800
983#define T5555_BITRATE_SHIFT 12
984#define T5555_FAST_WRITE 0x00004000
985#define T5555_PAGE_SELECT 0x00008000
986
987/*
988 * Relevant times in microsecond
989 * To compensate antenna falling times shorten the write times
990 * and enlarge the gap ones.
991 */
385f3987 992#define START_GAP 30*8 // 10 - 50fc 250
993#define WRITE_GAP 20*8 // 8 - 30fc
994#define WRITE_0 24*8 // 16 - 31fc 24fc 192
995#define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
996
997// VALUES TAKEN FROM EM4x function: SendForward
998// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
999// WRITE_GAP = 128; (16*8)
1000// WRITE_1 = 256 32*8; (32*8)
1001
1002// These timings work for 4469/4269/4305 (with the 55*8 above)
1003// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1004
1005#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
2d4eae76 1006
1007// Write one bit to card
1008void T55xxWriteBit(int bit)
ec09b62d 1009{
ae8e8a43
MHS		 1010 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1011 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1012 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
385f3987 1013 if (!bit)
ae8e8a43
MHS		 1014 SpinDelayUs(WRITE_0);
1015 else
1016 SpinDelayUs(WRITE_1);
1017 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1018 SpinDelayUs(WRITE_GAP);
ec09b62d 1019}
1020
2d4eae76 1021// Write one card block in page 0, no lock
54a942b0 1022void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 1023{
385f3987 1024 uint32_t i = 0;
ae8e8a43 1025
385f3987 1026 // Set up FPGA, 125kHz
1027 // Wait for config.. (192+8190xPOW)x8 == 67ms
1028 LFSetupFPGAForADC(0, true);
ae8e8a43
MHS		 1029
1030 // Now start writting
1031 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1032 SpinDelayUs(START_GAP);
1033
1034 // Opcode
1035 T55xxWriteBit(1);
1036 T55xxWriteBit(0); //Page 0
1037 if (PwdMode == 1){
1038 // Pwd
1039 for (i = 0x80000000; i != 0; i >>= 1)
1040 T55xxWriteBit(Pwd & i);
1041 }
1042 // Lock bit
1043 T55xxWriteBit(0);
1044
1045 // Data
54a942b0 1046 for (i = 0x80000000; i != 0; i >>= 1)
ae8e8a43
MHS		 1047 T55xxWriteBit(Data & i);
1048
1049 // Block
1050 for (i = 0x04; i != 0; i >>= 1)
1051 T55xxWriteBit(Block & i);
1052
1053 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1054 // so wait a little more)
1055 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1056 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1057 SpinDelay(20);
1058 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
ec09b62d 1059}
1060
54a942b0 1061// Read one card block in page 0
1062void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 1063{
385f3987 1064 uint32_t i = 0;
68008fb5 1065 uint8_t *dest = BigBuf_get_addr();
1066 uint16_t bufferlength = BigBuf_max_traceLen();
1067 if ( bufferlength > T55xx_SAMPLES_SIZE )
1068 bufferlength = T55xx_SAMPLES_SIZE;
1069
1070 memset(dest, 0x80, bufferlength);
385f3987 1071
1072 // Set up FPGA, 125kHz
1073 // Wait for config.. (192+8190xPOW)x8 == 67ms
1074 LFSetupFPGAForADC(0, true);
ae8e8a43
MHS		 1075 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1076 SpinDelayUs(START_GAP);
1077
1078 // Opcode
1079 T55xxWriteBit(1);
1080 T55xxWriteBit(0); //Page 0
1081 if (PwdMode == 1){
1082 // Pwd
1083 for (i = 0x80000000; i != 0; i >>= 1)
1084 T55xxWriteBit(Pwd & i);
1085 }
1086 // Lock bit
1087 T55xxWriteBit(0);
1088 // Block
1089 for (i = 0x04; i != 0; i >>= 1)
1090 T55xxWriteBit(Block & i);
1091
1092 // Turn field on to read the response
385f3987 1093 TurnReadLFOn();
ae8e8a43
MHS		 1094
1095 // Now do the acquisition
1096 i = 0;
1097 for(;;) {
1098 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1099 AT91C_BASE_SSC->SSC_THR = 0x43;
385f3987 1100 LED_D_ON();
ae8e8a43
MHS		 1101 }
1102 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1103 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
385f3987 1104 ++i;
1105 LED_D_OFF();
1106 if (i >= bufferlength) break;
ae8e8a43
MHS		 1107 }
1108 }
1109
385f3987 1110 cmd_send(CMD_ACK,0,0,0,0,0);
ae8e8a43
MHS		 1111 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1112 LED_D_OFF();
54a942b0 1113}
2d4eae76 1114
54a942b0 1115// Read card traceability data (page 1)
1116void T55xxReadTrace(void){
68008fb5 1117
385f3987 1118 uint32_t i = 0;
68008fb5 1119 uint8_t *dest = BigBuf_get_addr();
1120 uint16_t bufferlength = BigBuf_max_traceLen();
1121 if ( bufferlength > T55xx_SAMPLES_SIZE )
1122 bufferlength = T55xx_SAMPLES_SIZE;
385f3987 1123
385f3987 1124 memset(dest, 0x80, bufferlength);
1125
1126 LFSetupFPGAForADC(0, true);
ae8e8a43
MHS		 1127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1128 SpinDelayUs(START_GAP);
1129
1130 // Opcode
1131 T55xxWriteBit(1);
1132 T55xxWriteBit(1); //Page 1
1133
1134 // Turn field on to read the response
385f3987 1135 TurnReadLFOn();
ae8e8a43
MHS		 1136
1137 // Now do the acquisition
ae8e8a43
MHS		 1138 for(;;) {
1139 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1140 AT91C_BASE_SSC->SSC_THR = 0x43;
385f3987 1141 LED_D_ON();
ae8e8a43
MHS		 1142 }
1143 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1144 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
385f3987 1145 ++i;
1146 LED_D_OFF();
1147
1148 if (i >= bufferlength) break;
1149 }
1150 }
1151
1152 cmd_send(CMD_ACK,0,0,0,0,0);
ae8e8a43
MHS		 1153 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1154 LED_D_OFF();
385f3987 1155}
1156
1157void TurnReadLFOn(){
68008fb5 1158 //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
385f3987 1159 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1160 // Give it a bit of time for the resonant antenna to settle.
1161 //SpinDelay(30);
0310364d 1162 SpinDelayUs(9*150);
54a942b0 1163}
ec09b62d 1164
54a942b0 1165/*-------------- Cloning routines -----------*/
1166// Copy HID id to card and setup block 0 config
1167void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1168{
ae8e8a43
MHS		 1169 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1170 int last_block = 0;
1171
1172 if (longFMT){
1173 // Ensure no more than 84 bits supplied
1174 if (hi2>0xFFFFF) {
1175 DbpString("Tags can only have 84 bits.");
1176 return;
1177 }
1178 // Build the 6 data blocks for supplied 84bit ID
1179 last_block = 6;
1180 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1181 for (int i=0;i<4;i++) {
1182 if (hi2 & (1<<(19-i)))
1183 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1184 else
1185 data1 |= (1<<((3-i)*2)); // 0 -> 01
1186 }
1187
1188 data2 = 0;
1189 for (int i=0;i<16;i++) {
1190 if (hi2 & (1<<(15-i)))
1191 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1192 else
1193 data2 |= (1<<((15-i)*2)); // 0 -> 01
1194 }
1195
1196 data3 = 0;
1197 for (int i=0;i<16;i++) {
1198 if (hi & (1<<(31-i)))
1199 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1200 else
1201 data3 |= (1<<((15-i)*2)); // 0 -> 01
1202 }
1203
1204 data4 = 0;
1205 for (int i=0;i<16;i++) {
1206 if (hi & (1<<(15-i)))
1207 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1208 else
1209 data4 |= (1<<((15-i)*2)); // 0 -> 01
1210 }
1211
1212 data5 = 0;
1213 for (int i=0;i<16;i++) {
1214 if (lo & (1<<(31-i)))
1215 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1216 else
1217 data5 |= (1<<((15-i)*2)); // 0 -> 01
1218 }
1219
1220 data6 = 0;
1221 for (int i=0;i<16;i++) {
1222 if (lo & (1<<(15-i)))
1223 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1224 else
1225 data6 |= (1<<((15-i)*2)); // 0 -> 01
1226 }
54a942b0 1227 }
ae8e8a43
MHS		 1228 else {
1229 // Ensure no more than 44 bits supplied
1230 if (hi>0xFFF) {
1231 DbpString("Tags can only have 44 bits.");
1232 return;
1233 }
1234
1235 // Build the 3 data blocks for supplied 44bit ID
1236 last_block = 3;
1237
1238 data1 = 0x1D000000; // load preamble
1239
1240 for (int i=0;i<12;i++) {
1241 if (hi & (1<<(11-i)))
1242 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1243 else
1244 data1 |= (1<<((11-i)*2)); // 0 -> 01
1245 }
1246
1247 data2 = 0;
1248 for (int i=0;i<16;i++) {
1249 if (lo & (1<<(31-i)))
1250 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1251 else
1252 data2 |= (1<<((15-i)*2)); // 0 -> 01
1253 }
1254
1255 data3 = 0;
1256 for (int i=0;i<16;i++) {
1257 if (lo & (1<<(15-i)))
1258 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1259 else
1260 data3 |= (1<<((15-i)*2)); // 0 -> 01
1261 }
54a942b0 1262 }
ae8e8a43
MHS		 1263
1264 LED_D_ON();
1265 // Program the data blocks for supplied ID
1266 // and the block 0 for HID format
1267 T55xxWriteBlock(data1,1,0,0);
1268 T55xxWriteBlock(data2,2,0,0);
1269 T55xxWriteBlock(data3,3,0,0);
1270
1271 if (longFMT) { // if long format there are 6 blocks
1272 T55xxWriteBlock(data4,4,0,0);
1273 T55xxWriteBlock(data5,5,0,0);
1274 T55xxWriteBlock(data6,6,0,0);
54a942b0 1275 }
ae8e8a43
MHS		 1276
1277 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1278 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1279 T55x7_MODULATION_FSK2a |
1280 last_block << T55x7_MAXBLOCK_SHIFT,
1281 0,0,0);
1282
1283 LED_D_OFF();
1284
1285 DbpString("DONE!");
2d4eae76 1286}
ec09b62d 1287
a1f3bb12 1288void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1289{
ae8e8a43
MHS		 1290 int data1=0, data2=0; //up to six blocks for long format
1291
a1f3bb12 1292 data1 = hi; // load preamble
1293 data2 = lo;
ba1a299c 1294
a1f3bb12 1295 LED_D_ON();
1296 // Program the data blocks for supplied ID
1297 // and the block 0 for HID format
1298 T55xxWriteBlock(data1,1,0,0);
1299 T55xxWriteBlock(data2,2,0,0);
ae8e8a43 1300
a1f3bb12 1301 //Config Block
1302 T55xxWriteBlock(0x00147040,0,0,0);
1303 LED_D_OFF();
ae8e8a43 1304
a1f3bb12 1305 DbpString("DONE!");
1306}
1307
2d4eae76 1308// Define 9bit header for EM410x tags
1309#define EM410X_HEADER 0x1FF
1310#define EM410X_ID_LENGTH 40
ec09b62d 1311
2d4eae76 1312void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1313{
ae8e8a43
MHS		 1314 int i, id_bit;
1315 uint64_t id = EM410X_HEADER;
1316 uint64_t rev_id = 0; // reversed ID
1317 int c_parity[4]; // column parity
1318 int r_parity = 0; // row parity
1319 uint32_t clock = 0;
1320
1321 // Reverse ID bits given as parameter (for simpler operations)
1322 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1323 if (i < 32) {
1324 rev_id = (rev_id << 1) | (id_lo & 1);
1325 id_lo >>= 1;
1326 } else {
1327 rev_id = (rev_id << 1) | (id_hi & 1);
1328 id_hi >>= 1;
1329 }
1330 }
1331
1332 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1333 id_bit = rev_id & 1;
1334
1335 if (i % 4 == 0) {
1336 // Don't write row parity bit at start of parsing
1337 if (i)
1338 id = (id << 1) | r_parity;
1339 // Start counting parity for new row
1340 r_parity = id_bit;
1341 } else {
1342 // Count row parity
1343 r_parity ^= id_bit;
1344 }
1345
1346 // First elements in column?
1347 if (i < 4)
1348 // Fill out first elements
1349 c_parity[i] = id_bit;
1350 else
1351 // Count column parity
1352 c_parity[i % 4] ^= id_bit;
1353
1354 // Insert ID bit
1355 id = (id << 1) | id_bit;
1356 rev_id >>= 1;
1357 }
1358
1359 // Insert parity bit of last row
1360 id = (id << 1) | r_parity;
1361
1362 // Fill out column parity at the end of tag
1363 for (i = 0; i < 4; ++i)
1364 id = (id << 1) | c_parity[i];
1365
1366 // Add stop bit
1367 id <<= 1;
1368
1369 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1370 LED_D_ON();
1371
1372 // Write EM410x ID
1373 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1374 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1375
1376 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1377 if (card) {
1378 // Clock rate is stored in bits 8-15 of the card value
1379 clock = (card & 0xFF00) >> 8;
1380 Dbprintf("Clock rate: %d", clock);
1381 switch (clock)
1382 {
1383 case 32:
1384 clock = T55x7_BITRATE_RF_32;
1385 break;
1386 case 16:
1387 clock = T55x7_BITRATE_RF_16;
1388 break;
1389 case 0:
1390 // A value of 0 is assumed to be 64 for backwards-compatibility
1391 // Fall through...
1392 case 64:
1393 clock = T55x7_BITRATE_RF_64;
1394 break;
1395 default:
1396 Dbprintf("Invalid clock rate: %d", clock);
1397 return;
1398 }
1399
1400 // Writing configuration for T55x7 tag
1401 T55xxWriteBlock(clock |
1402 T55x7_MODULATION_MANCHESTER |
1403 2 << T55x7_MAXBLOCK_SHIFT,
1404 0, 0, 0);
1405 }
1406 else
1407 // Writing configuration for T5555(Q5) tag
1408 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1409 T5555_MODULATION_MANCHESTER |
1410 2 << T5555_MAXBLOCK_SHIFT,
1411 0, 0, 0);
1412
1413 LED_D_OFF();
1414 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1415 (uint32_t)(id >> 32), (uint32_t)id);
2d4eae76 1416}
2414f978 1417
1418// Clone Indala 64-bit tag by UID to T55x7
1419void CopyIndala64toT55x7(int hi, int lo)
1420{
2414f978 1421
ae8e8a43
MHS		 1422 //Program the 2 data blocks for supplied 64bit UID
1423 // and the block 0 for Indala64 format
1424 T55xxWriteBlock(hi,1,0,0);
1425 T55xxWriteBlock(lo,2,0,0);
1426 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1427 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1428 T55x7_MODULATION_PSK1 |
1429 2 << T55x7_MAXBLOCK_SHIFT,
1430 0, 0, 0);
1431 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1432 // T5567WriteBlock(0x603E1042,0);
2414f978 1433
ae8e8a43 1434 DbpString("DONE!");
4118b74d 1435
ba1a299c 1436}
2414f978 1437
1438void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1439{
ae8e8a43 1440
ae8e8a43
MHS		 1441 //Program the 7 data blocks for supplied 224bit UID
1442 // and the block 0 for Indala224 format
1443 T55xxWriteBlock(uid1,1,0,0);
1444 T55xxWriteBlock(uid2,2,0,0);
1445 T55xxWriteBlock(uid3,3,0,0);
1446 T55xxWriteBlock(uid4,4,0,0);
1447 T55xxWriteBlock(uid5,5,0,0);
1448 T55xxWriteBlock(uid6,6,0,0);
1449 T55xxWriteBlock(uid7,7,0,0);
1450 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1451 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1452 T55x7_MODULATION_PSK1 |
1453 7 << T55x7_MAXBLOCK_SHIFT,
1454 0,0,0);
1455 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1456 // T5567WriteBlock(0x603E10E2,0);
1457
1458 DbpString("DONE!");
4118b74d 1459
2414f978 1460}
54a942b0 1461
1462
1463#define abs(x) ( ((x)<0) ? -(x) : (x) )
1464#define max(x,y) ( x<y ? y:x)
1465
1466int DemodPCF7931(uint8_t **outBlocks) {
d716ca2f 1467
1468 uint8_t BitStream[256] = {0x00};
5ff3c401 1469 uint8_t Blocks[8][16];
d716ca2f 1470 uint8_t *dest = BigBuf_get_addr();
f71f4deb 1471 int GraphTraceLen = BigBuf_max_traceLen();
ae8e8a43
MHS		 1472 int i, j, lastval, bitidx, half_switch;
1473 int clock = 64;
1474 int tolerance = clock / 8;
1475 int pmc, block_done;
1476 int lc, warnings = 0;
1477 int num_blocks = 0;
1478 int lmin=128, lmax=128;
1479 uint8_t dir;
1480
31abe49f 1481 LFSetupFPGAForADC(95, true);
d716ca2f 1482 DoAcquisition_default(0, true);
ae8e8a43
MHS		 1483
1484 lmin = 64;
1485 lmax = 192;
1486
1487 i = 2;
1488
1489 /* Find first local max/min */
d716ca2f 1490 if(dest[1] > dest[0]) {
ae8e8a43 1491 while(i < GraphTraceLen) {
d716ca2f 1492 if( !(dest[i] > dest[i-1]) && dest[i] > lmax)
ae8e8a43
MHS		 1493 break;
1494 i++;
1495 }
1496 dir = 0;
54a942b0 1497 }
ae8e8a43
MHS		 1498 else {
1499 while(i < GraphTraceLen) {
5ff3c401 1500 if( !(dest[i] < dest[i-1]) && dest[i] < lmin)
ae8e8a43
MHS		 1501 break;
1502 i++;
1503 }
1504 dir = 1;
54a942b0 1505 }
ae8e8a43
MHS		 1506
1507 lastval = i++;
1508 half_switch = 0;
1509 pmc = 0;
1510 block_done = 0;
1511
1512 for (bitidx = 0; i < GraphTraceLen; i++)
1513 {
d716ca2f 1514 if ( (dest[i-1] > dest[i] && dir == 1 && dest[i] > lmax) || (dest[i-1] < dest[i] && dir == 0 && dest[i] < lmin))
ae8e8a43
MHS		 1515 {
1516 lc = i - lastval;
1517 lastval = i;
1518
1519 // Switch depending on lc length:
1520 // Tolerance is 1/8 of clock rate (arbitrary)
1521 if (abs(lc-clock/4) < tolerance) {
1522 // 16T0
1523 if((i - pmc) == lc) { /* 16T0 was previous one */
1524 /* It's a PMC ! */
1525 i += (128+127+16+32+33+16)-1;
1526 lastval = i;
1527 pmc = 0;
1528 block_done = 1;
1529 }
1530 else {
1531 pmc = i;
1532 }
1533 } else if (abs(lc-clock/2) < tolerance) {
1534 // 32TO
1535 if((i - pmc) == lc) { /* 16T0 was previous one */
1536 /* It's a PMC ! */
1537 i += (128+127+16+32+33)-1;
1538 lastval = i;
1539 pmc = 0;
1540 block_done = 1;
1541 }
1542 else if(half_switch == 1) {
1543 BitStream[bitidx++] = 0;
1544 half_switch = 0;
1545 }
1546 else
1547 half_switch++;
1548 } else if (abs(lc-clock) < tolerance) {
1549 // 64TO
1550 BitStream[bitidx++] = 1;
1551 } else {
1552 // Error
1553 warnings++;
1554 if (warnings > 10)
1555 {
1556 Dbprintf("Error: too many detection errors, aborting.");
1557 return 0;
1558 }
1559 }
1560
1561 if(block_done == 1) {
1562 if(bitidx == 128) {
1563 for(j=0; j<16; j++) {
1564 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1565 64*BitStream[j*8+6]+
1566 32*BitStream[j*8+5]+
1567 16*BitStream[j*8+4]+
1568 8*BitStream[j*8+3]+
1569 4*BitStream[j*8+2]+
1570 2*BitStream[j*8+1]+
1571 BitStream[j*8];
1572 }
1573 num_blocks++;
1574 }
1575 bitidx = 0;
1576 block_done = 0;
1577 half_switch = 0;
1578 }
1579 if(i < GraphTraceLen)
1580 {
d716ca2f 1581 if (dest[i-1] > dest[i]) dir=0;
ae8e8a43
MHS		 1582 else dir = 1;
1583 }
1584 }
1585 if(bitidx==255)
1586 bitidx=0;
1587 warnings = 0;
1588 if(num_blocks == 4) break;
1589 }
1590 memcpy(outBlocks, Blocks, 16*num_blocks);
1591 return num_blocks;
54a942b0 1592}
1593
1594int IsBlock0PCF7931(uint8_t *Block) {
ae8e8a43
MHS		 1595 // Assume RFU means 0 :)
1596 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1597 return 1;
1598 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1599 return 1;
1600 return 0;
54a942b0 1601}
1602
1603int IsBlock1PCF7931(uint8_t *Block) {
ae8e8a43
MHS		 1604 // Assume RFU means 0 :)
1605 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1606 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1607 return 1;
1608
1609 return 0;
54a942b0 1610}
d91a31f9 1611
54a942b0 1612#define ALLOC 16
1613
1614void ReadPCF7931() {
ae8e8a43
MHS		 1615 uint8_t Blocks[8][17];
1616 uint8_t tmpBlocks[4][16];
1617 int i, j, ind, ind2, n;
1618 int num_blocks = 0;
1619 int max_blocks = 8;
1620 int ident = 0;
1621 int error = 0;
1622 int tries = 0;
1623
1624 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1625
1626 do {
1627 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1628 n = DemodPCF7931((uint8_t**)tmpBlocks);
1629 if(!n)
1630 error++;
1631 if(error==10 && num_blocks == 0) {
1632 Dbprintf("Error, no tag or bad tag");
1633 return;
54a942b0 1634 }
ae8e8a43
MHS		 1635 else if (tries==20 || error==10) {
1636 Dbprintf("Error reading the tag");
1637 Dbprintf("Here is the partial content");
1638 goto end;
1639 }
1640
1641 for(i=0; i<n; i++)
1642 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1643 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1644 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1645 if(!ident) {
1646 for(i=0; i<n; i++) {
1647 if(IsBlock0PCF7931(tmpBlocks[i])) {
1648 // Found block 0 ?
1649 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1650 // Found block 1!
1651 // \o/
1652 ident = 1;
1653 memcpy(Blocks[0], tmpBlocks[i], 16);
1654 Blocks[0][ALLOC] = 1;
1655 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1656 Blocks[1][ALLOC] = 1;
1657 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1658 // Debug print
1659 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1660 num_blocks = 2;
1661 // Handle following blocks
1662 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1663 if(j==n) j=0;
1664 if(j==i) break;
1665 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1666 Blocks[ind2][ALLOC] = 1;
1667 }
1668 break;
1669 }
54a942b0 1670 }
ae8e8a43
MHS		 1671 }
1672 }
1673 else {
1674 for(i=0; i<n; i++) { // Look for identical block in known blocks
1675 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1676 for(j=0; j<max_blocks; j++) {
1677 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1678 // Found an identical block
1679 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1680 if(ind2 < 0)
1681 ind2 = max_blocks;
1682 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1683 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1684 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1685 Blocks[ind2][ALLOC] = 1;
1686 num_blocks++;
1687 if(num_blocks == max_blocks) goto end;
1688 }
1689 }
1690 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1691 if(ind2 > max_blocks)
1692 ind2 = 0;
1693 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1694 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1695 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1696 Blocks[ind2][ALLOC] = 1;
1697 num_blocks++;
1698 if(num_blocks == max_blocks) goto end;
1699 }
1700 }
1701 }
1702 }
54a942b0 1703 }
54a942b0 1704 }
54a942b0 1705 }
ae8e8a43
MHS		 1706 tries++;
1707 if (BUTTON_PRESS()) return;
1708 } while (num_blocks != max_blocks);
e09f21fa 1709 end:
ae8e8a43
MHS		 1710 Dbprintf("-----------------------------------------");
1711 Dbprintf("Memory content:");
1712 Dbprintf("-----------------------------------------");
1713 for(i=0; i<max_blocks; i++) {
1714 if(Blocks[i][ALLOC]==1)
1715 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1716 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1717 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1718 else
1719 Dbprintf("<missing block %d>", i);
1720 }
1721 Dbprintf("-----------------------------------------");
1722
1723 return ;
54a942b0 1724}
1725
1726
1727//-----------------------------------
1728// EM4469 / EM4305 routines
1729//-----------------------------------
1730#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1731#define FWD_CMD_WRITE 0xA
1732#define FWD_CMD_READ 0x9
1733#define FWD_CMD_DISABLE 0x5
1734
1735
1736uint8_t forwardLink_data[64]; //array of forwarded bits
1737uint8_t * forward_ptr; //ptr for forward message preparation
1738uint8_t fwd_bit_sz; //forwardlink bit counter
1739uint8_t * fwd_write_ptr; //forwardlink bit pointer
1740
1741//====================================================================
1742// prepares command bits
1743// see EM4469 spec
1744//====================================================================
1745//--------------------------------------------------------------------
1746uint8_t Prepare_Cmd( uint8_t cmd ) {
ae8e8a43
MHS		 1747 //--------------------------------------------------------------------
1748
1749 *forward_ptr++ = 0; //start bit
1750 *forward_ptr++ = 0; //second pause for 4050 code
1751
1752 *forward_ptr++ = cmd;
1753 cmd >>= 1;
1754 *forward_ptr++ = cmd;
1755 cmd >>= 1;
1756 *forward_ptr++ = cmd;
1757 cmd >>= 1;
1758 *forward_ptr++ = cmd;
1759
1760 return 6; //return number of emited bits
54a942b0 1761}
1762
1763//====================================================================
1764// prepares address bits
1765// see EM4469 spec
1766//====================================================================
1767
1768//--------------------------------------------------------------------
1769uint8_t Prepare_Addr( uint8_t addr ) {
ae8e8a43
MHS		 1770 //--------------------------------------------------------------------
1771
1772 register uint8_t line_parity;
1773
1774 uint8_t i;
1775 line_parity = 0;
1776 for(i=0;i<6;i++) {
1777 *forward_ptr++ = addr;
1778 line_parity ^= addr;
1779 addr >>= 1;
1780 }
1781
1782 *forward_ptr++ = (line_parity & 1);
1783
1784 return 7; //return number of emited bits
54a942b0 1785}
1786
1787//====================================================================
1788// prepares data bits intreleaved with parity bits
1789// see EM4469 spec
1790//====================================================================
1791
1792//--------------------------------------------------------------------
1793uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
ae8e8a43
MHS		 1794 //--------------------------------------------------------------------
1795
1796 register uint8_t line_parity;
1797 register uint8_t column_parity;
1798 register uint8_t i, j;
1799 register uint16_t data;
1800
1801 data = data_low;
1802 column_parity = 0;
1803
1804 for(i=0; i<4; i++) {
1805 line_parity = 0;
1806 for(j=0; j<8; j++) {
1807 line_parity ^= data;
1808 column_parity ^= (data & 1) << j;
1809 *forward_ptr++ = data;
1810 data >>= 1;
1811 }
1812 *forward_ptr++ = line_parity;
1813 if(i == 1)
1814 data = data_hi;
1815 }
1816
54a942b0 1817 for(j=0; j<8; j++) {
ae8e8a43
MHS		 1818 *forward_ptr++ = column_parity;
1819 column_parity >>= 1;
54a942b0 1820 }
ae8e8a43
MHS		 1821 *forward_ptr = 0;
1822
1823 return 45; //return number of emited bits
54a942b0 1824}
1825
1826//====================================================================
1827// Forward Link send function
1828// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1829// fwd_bit_count set with number of bits to be sent
1830//====================================================================
1831void SendForward(uint8_t fwd_bit_count) {
ae8e8a43
MHS		 1832
1833 fwd_write_ptr = forwardLink_data;
1834 fwd_bit_sz = fwd_bit_count;
1835
1836 LED_D_ON();
1837
1838 //Field on
1839 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1840 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1841 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1842
1843 // Give it a bit of time for the resonant antenna to settle.
1844 // And for the tag to fully power up
1845 SpinDelay(150);
1846
1847 // force 1st mod pulse (start gap must be longer for 4305)
1848 fwd_bit_sz--; //prepare next bit modulation
1849 fwd_write_ptr++;
1850 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1851 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1852 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1853 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1854 SpinDelayUs(16*8); //16 cycles on (8us each)
1855
1856 // now start writting
1857 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1858 if(((*fwd_write_ptr++) & 1) == 1)
1859 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1860 else {
1861 //These timings work for 4469/4269/4305 (with the 55*8 above)
1862 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1863 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1864 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1865 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1866 SpinDelayUs(9*8); //16 cycles on (8us each)
1867 }
54a942b0 1868 }
54a942b0 1869}
1870
1871void EM4xLogin(uint32_t Password) {
ae8e8a43
MHS		 1872
1873 uint8_t fwd_bit_count;
1874
1875 forward_ptr = forwardLink_data;
1876 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1877 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1878
1879 SendForward(fwd_bit_count);
1880
1881 //Wait for command to complete
1882 SpinDelay(20);
1883
54a942b0 1884}
1885
1886void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
ae8e8a43 1887
385f3987 1888 uint8_t *dest = BigBuf_get_addr();
1889 uint16_t bufferlength = BigBuf_max_traceLen();
1890 uint32_t i = 0;
1891
1892 // Clear destination buffer before sending the command 0x80 = average.
1893 memset(dest, 0x80, bufferlength);
1894
ae8e8a43 1895 uint8_t fwd_bit_count;
ae8e8a43
MHS		 1896
1897 //If password mode do login
1898 if (PwdMode == 1) EM4xLogin(Pwd);
1899
1900 forward_ptr = forwardLink_data;
1901 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1902 fwd_bit_count += Prepare_Addr( Address );
1903
ae8e8a43
MHS		 1904 // Connect the A/D to the peak-detected low-frequency path.
1905 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1906 // Now set up the SSC to get the ADC samples that are now streaming at us.
1907 FpgaSetupSsc();
1908
1909 SendForward(fwd_bit_count);
1910
1911 // Now do the acquisition
1912 i = 0;
1913 for(;;) {
1914 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1915 AT91C_BASE_SSC->SSC_THR = 0x43;
1916 }
1917 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1918 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
385f3987 1919 ++i;
1920 if (i >= bufferlength) break;
1921 }
1922 }
1923
1924 cmd_send(CMD_ACK,0,0,0,0,0);
ae8e8a43
MHS		 1925 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1926 LED_D_OFF();
54a942b0 1927}
1928
1929void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
ae8e8a43
MHS		 1930
1931 uint8_t fwd_bit_count;
1932
1933 //If password mode do login
1934 if (PwdMode == 1) EM4xLogin(Pwd);
1935
1936 forward_ptr = forwardLink_data;
1937 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1938 fwd_bit_count += Prepare_Addr( Address );
1939 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1940
1941 SendForward(fwd_bit_count);
1942
1943 //Wait for write to complete
1944 SpinDelay(20);
1945 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1946 LED_D_OFF();
54a942b0 1947}
Proxmark3 GIT tracking
Impressum, Datenschutz