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fixing iso14443b (issue #103):
[proxmark3-svn] / armsrc / iso14443b.c
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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// Jonathan Westhues, split Nov 2006
3//
4// This code is licensed to you under the terms of the GNU GPL, version 2 or,
5// at your option, any later version. See the LICENSE.txt file for the text of
6// the license.
7//-----------------------------------------------------------------------------
51d4f6f1 8// Routines to support ISO 14443B. This includes both the reader software and
9// the `fake tag' modes.
15c4dc5a 10//-----------------------------------------------------------------------------
bd20f8f4 11
e30c654b 12#include "proxmark3.h"
15c4dc5a 13#include "apps.h"
f7e3ed82 14#include "util.h"
9ab7a6c7 15#include "string.h"
15c4dc5a 16
f7e3ed82 17#include "iso14443crc.h"
15c4dc5a 18
0d9a86c7 19#define RECEIVE_SAMPLES_TIMEOUT 2000
20
15c4dc5a 21//=============================================================================
22// An ISO 14443 Type B tag. We listen for commands from the reader, using
23// a UART kind of thing that's implemented in software. When we get a
24// frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
25// If it's good, then we can do something appropriate with it, and send
26// a response.
27//=============================================================================
28
29//-----------------------------------------------------------------------------
30// Code up a string of octets at layer 2 (including CRC, we don't generate
31// that here) so that they can be transmitted to the reader. Doesn't transmit
32// them yet, just leaves them ready to send in ToSend[].
33//-----------------------------------------------------------------------------
f7e3ed82 34static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
15c4dc5a 35{
7d5ebac9
MHS
36 int i;
37
38 ToSendReset();
39
40 // Transmit a burst of ones, as the initial thing that lets the
41 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
42 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
43 // so I will too.
44 for(i = 0; i < 20; i++) {
45 ToSendStuffBit(1);
46 ToSendStuffBit(1);
47 ToSendStuffBit(1);
48 ToSendStuffBit(1);
49 }
50
51 // Send SOF.
52 for(i = 0; i < 10; i++) {
53 ToSendStuffBit(0);
54 ToSendStuffBit(0);
55 ToSendStuffBit(0);
56 ToSendStuffBit(0);
57 }
58 for(i = 0; i < 2; i++) {
59 ToSendStuffBit(1);
60 ToSendStuffBit(1);
61 ToSendStuffBit(1);
62 ToSendStuffBit(1);
63 }
64
65 for(i = 0; i < len; i++) {
66 int j;
67 uint8_t b = cmd[i];
68
69 // Start bit
70 ToSendStuffBit(0);
71 ToSendStuffBit(0);
72 ToSendStuffBit(0);
73 ToSendStuffBit(0);
74
75 // Data bits
76 for(j = 0; j < 8; j++) {
77 if(b & 1) {
78 ToSendStuffBit(1);
79 ToSendStuffBit(1);
80 ToSendStuffBit(1);
81 ToSendStuffBit(1);
82 } else {
83 ToSendStuffBit(0);
84 ToSendStuffBit(0);
85 ToSendStuffBit(0);
86 ToSendStuffBit(0);
87 }
88 b >>= 1;
89 }
90
91 // Stop bit
92 ToSendStuffBit(1);
93 ToSendStuffBit(1);
94 ToSendStuffBit(1);
95 ToSendStuffBit(1);
96 }
97
51d4f6f1 98 // Send EOF.
7d5ebac9
MHS
99 for(i = 0; i < 10; i++) {
100 ToSendStuffBit(0);
101 ToSendStuffBit(0);
102 ToSendStuffBit(0);
103 ToSendStuffBit(0);
104 }
51d4f6f1 105 for(i = 0; i < 2; i++) {
7d5ebac9
MHS
106 ToSendStuffBit(1);
107 ToSendStuffBit(1);
108 ToSendStuffBit(1);
109 ToSendStuffBit(1);
110 }
111
112 // Convert from last byte pos to length
113 ToSendMax++;
15c4dc5a 114}
115
116//-----------------------------------------------------------------------------
117// The software UART that receives commands from the reader, and its state
118// variables.
119//-----------------------------------------------------------------------------
120static struct {
7d5ebac9
MHS
121 enum {
122 STATE_UNSYNCD,
123 STATE_GOT_FALLING_EDGE_OF_SOF,
124 STATE_AWAITING_START_BIT,
46734099 125 STATE_RECEIVING_DATA
7d5ebac9
MHS
126 } state;
127 uint16_t shiftReg;
128 int bitCnt;
129 int byteCnt;
130 int byteCntMax;
131 int posCnt;
132 uint8_t *output;
15c4dc5a 133} Uart;
134
135/* Receive & handle a bit coming from the reader.
51d4f6f1 136 *
137 * This function is called 4 times per bit (every 2 subcarrier cycles).
138 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
15c4dc5a 139 *
140 * LED handling:
141 * LED A -> ON once we have received the SOF and are expecting the rest.
142 * LED A -> OFF once we have received EOF or are in error state or unsynced
143 *
144 * Returns: true if we received a EOF
145 * false if we are still waiting for some more
146 */
46734099 147static RAMFUNC int Handle14443bUartBit(uint8_t bit)
15c4dc5a 148{
7d5ebac9 149 switch(Uart.state) {
03dc1740 150 case STATE_UNSYNCD:
7d5ebac9
MHS
151 if(!bit) {
152 // we went low, so this could be the beginning
153 // of an SOF
154 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
155 Uart.posCnt = 0;
156 Uart.bitCnt = 0;
157 }
158 break;
159
160 case STATE_GOT_FALLING_EDGE_OF_SOF:
161 Uart.posCnt++;
51d4f6f1 162 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
7d5ebac9 163 if(bit) {
51d4f6f1 164 if(Uart.bitCnt > 9) {
7d5ebac9
MHS
165 // we've seen enough consecutive
166 // zeros that it's a valid SOF
167 Uart.posCnt = 0;
168 Uart.byteCnt = 0;
169 Uart.state = STATE_AWAITING_START_BIT;
170 LED_A_ON(); // Indicate we got a valid SOF
171 } else {
172 // didn't stay down long enough
173 // before going high, error
46734099 174 Uart.state = STATE_UNSYNCD;
7d5ebac9
MHS
175 }
176 } else {
177 // do nothing, keep waiting
178 }
179 Uart.bitCnt++;
180 }
181 if(Uart.posCnt >= 4) Uart.posCnt = 0;
51d4f6f1 182 if(Uart.bitCnt > 12) {
7d5ebac9
MHS
183 // Give up if we see too many zeros without
184 // a one, too.
46734099 185 LED_A_OFF();
186 Uart.state = STATE_UNSYNCD;
7d5ebac9
MHS
187 }
188 break;
189
190 case STATE_AWAITING_START_BIT:
191 Uart.posCnt++;
192 if(bit) {
51d4f6f1 193 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
7d5ebac9
MHS
194 // stayed high for too long between
195 // characters, error
46734099 196 Uart.state = STATE_UNSYNCD;
7d5ebac9
MHS
197 }
198 } else {
199 // falling edge, this starts the data byte
200 Uart.posCnt = 0;
201 Uart.bitCnt = 0;
202 Uart.shiftReg = 0;
203 Uart.state = STATE_RECEIVING_DATA;
7d5ebac9
MHS
204 }
205 break;
206
207 case STATE_RECEIVING_DATA:
208 Uart.posCnt++;
209 if(Uart.posCnt == 2) {
210 // time to sample a bit
211 Uart.shiftReg >>= 1;
212 if(bit) {
213 Uart.shiftReg |= 0x200;
214 }
215 Uart.bitCnt++;
216 }
217 if(Uart.posCnt >= 4) {
218 Uart.posCnt = 0;
219 }
220 if(Uart.bitCnt == 10) {
221 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
222 {
223 // this is a data byte, with correct
224 // start and stop bits
225 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
226 Uart.byteCnt++;
227
228 if(Uart.byteCnt >= Uart.byteCntMax) {
229 // Buffer overflowed, give up
46734099 230 LED_A_OFF();
231 Uart.state = STATE_UNSYNCD;
7d5ebac9
MHS
232 } else {
233 // so get the next byte now
234 Uart.posCnt = 0;
235 Uart.state = STATE_AWAITING_START_BIT;
236 }
46734099 237 } else if (Uart.shiftReg == 0x000) {
7d5ebac9
MHS
238 // this is an EOF byte
239 LED_A_OFF(); // Finished receiving
46734099 240 Uart.state = STATE_UNSYNCD;
132a0217 241 if (Uart.byteCnt != 0) {
242 return TRUE;
243 }
7d5ebac9
MHS
244 } else {
245 // this is an error
46734099 246 LED_A_OFF();
247 Uart.state = STATE_UNSYNCD;
7d5ebac9
MHS
248 }
249 }
250 break;
251
7d5ebac9 252 default:
46734099 253 LED_A_OFF();
7d5ebac9
MHS
254 Uart.state = STATE_UNSYNCD;
255 break;
256 }
257
7d5ebac9 258 return FALSE;
15c4dc5a 259}
260
46734099 261
262static void UartReset()
263{
264 Uart.byteCntMax = MAX_FRAME_SIZE;
265 Uart.state = STATE_UNSYNCD;
266 Uart.byteCnt = 0;
267 Uart.bitCnt = 0;
268}
269
270
271static void UartInit(uint8_t *data)
272{
273 Uart.output = data;
274 UartReset();
275}
276
277
15c4dc5a 278//-----------------------------------------------------------------------------
279// Receive a command (from the reader to us, where we are the simulated tag),
280// and store it in the given buffer, up to the given maximum length. Keeps
281// spinning, waiting for a well-framed command, until either we get one
282// (returns TRUE) or someone presses the pushbutton on the board (FALSE).
283//
284// Assume that we're called with the SSC (to the FPGA) and ADC path set
285// correctly.
286//-----------------------------------------------------------------------------
46734099 287static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
15c4dc5a 288{
51d4f6f1 289 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
7d5ebac9
MHS
290 // only, since we are receiving, not transmitting).
291 // Signal field is off with the appropriate LED
292 LED_D_OFF();
293 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
294
7d5ebac9 295 // Now run a `software UART' on the stream of incoming samples.
46734099 296 UartInit(received);
7d5ebac9
MHS
297
298 for(;;) {
299 WDT_HIT();
300
301 if(BUTTON_PRESS()) return FALSE;
302
7d5ebac9
MHS
303 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
304 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
46734099 305 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
306 if(Handle14443bUartBit(b & mask)) {
7d5ebac9
MHS
307 *len = Uart.byteCnt;
308 return TRUE;
309 }
310 }
311 }
312 }
46734099 313
314 return FALSE;
15c4dc5a 315}
316
317//-----------------------------------------------------------------------------
318// Main loop of simulated tag: receive commands from reader, decide what
319// response to send, and send it.
320//-----------------------------------------------------------------------------
51d4f6f1 321void SimulateIso14443bTag(void)
15c4dc5a 322{
46734099 323 // the only commands we understand is REQB, AFI=0, Select All, N=0:
7d5ebac9 324 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
46734099 325 // ... and REQB, AFI=0, Normal Request, N=0:
326 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF };
327
328 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
51d4f6f1 329 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
330 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
7d5ebac9
MHS
331 static const uint8_t response1[] = {
332 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
333 0x00, 0x21, 0x85, 0x5e, 0xd7
334 };
15c4dc5a 335
46734099 336 clear_trace();
337 set_tracing(TRUE);
338
339 const uint8_t *resp;
340 uint8_t *respCode;
341 uint16_t respLen, respCodeLen;
15c4dc5a 342
51d4f6f1 343 // allocate command receive buffer
344 BigBuf_free();
345 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
15c4dc5a 346
46734099 347 uint16_t len;
348 uint16_t cmdsRecvd = 0;
15c4dc5a 349
7d5ebac9 350 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
15c4dc5a 351
51d4f6f1 352 // prepare the (only one) tag answer:
7d5ebac9 353 CodeIso14443bAsTag(response1, sizeof(response1));
46734099 354 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
355 memcpy(resp1Code, ToSend, ToSendMax);
356 uint16_t resp1CodeLen = ToSendMax;
15c4dc5a 357
7d5ebac9
MHS
358 // We need to listen to the high-frequency, peak-detected path.
359 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
360 FpgaSetupSsc();
15c4dc5a 361
7d5ebac9 362 cmdsRecvd = 0;
15c4dc5a 363
7d5ebac9 364 for(;;) {
15c4dc5a 365
46734099 366 if(!GetIso14443bCommandFromReader(receivedCmd, &len)) {
51d4f6f1 367 Dbprintf("button pressed, received %d commands", cmdsRecvd);
368 break;
46734099 369 }
7d5ebac9 370
46734099 371 if (tracing) {
372 uint8_t parity[MAX_PARITY_SIZE];
373 LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
374 }
7d5ebac9 375
46734099 376 // Good, look at the command now.
377 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
378 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
379 resp = response1;
380 respLen = sizeof(response1);
381 respCode = resp1Code;
382 respCodeLen = resp1CodeLen;
7d5ebac9
MHS
383 } else {
384 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
385 // And print whether the CRC fails, just for good measure
46734099 386 uint8_t b1, b2;
7d5ebac9
MHS
387 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
388 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
389 // Not so good, try again.
390 DbpString("+++CRC fail");
391 } else {
392 DbpString("CRC passes");
393 }
394 break;
395 }
396
7d5ebac9
MHS
397 cmdsRecvd++;
398
399 if(cmdsRecvd > 0x30) {
400 DbpString("many commands later...");
401 break;
402 }
403
46734099 404 if(respCodeLen <= 0) continue;
7d5ebac9
MHS
405
406 // Modulate BPSK
407 // Signal field is off with the appropriate LED
408 LED_D_OFF();
409 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
410 AT91C_BASE_SSC->SSC_THR = 0xff;
411 FpgaSetupSsc();
412
413 // Transmit the response.
46734099 414 uint16_t i = 0;
7d5ebac9
MHS
415 for(;;) {
416 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
46734099 417 uint8_t b = respCode[i];
7d5ebac9
MHS
418
419 AT91C_BASE_SSC->SSC_THR = b;
420
421 i++;
46734099 422 if(i > respCodeLen) {
7d5ebac9
MHS
423 break;
424 }
425 }
426 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
427 volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
428 (void)b;
429 }
430 }
46734099 431
432 // trace the response:
433 if (tracing) {
434 uint8_t parity[MAX_PARITY_SIZE];
435 LogTrace(resp, respLen, 0, 0, parity, FALSE);
436 }
437
7d5ebac9 438 }
15c4dc5a 439}
440
441//=============================================================================
442// An ISO 14443 Type B reader. We take layer two commands, code them
443// appropriately, and then send them to the tag. We then listen for the
444// tag's response, which we leave in the buffer to be demodulated on the
445// PC side.
446//=============================================================================
447
448static struct {
7d5ebac9
MHS
449 enum {
450 DEMOD_UNSYNCD,
451 DEMOD_PHASE_REF_TRAINING,
452 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
453 DEMOD_GOT_FALLING_EDGE_OF_SOF,
454 DEMOD_AWAITING_START_BIT,
46734099 455 DEMOD_RECEIVING_DATA
7d5ebac9
MHS
456 } state;
457 int bitCount;
458 int posCount;
459 int thisBit;
51d4f6f1 460/* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
7d5ebac9
MHS
461 int metric;
462 int metricN;
51d4f6f1 463*/
7d5ebac9
MHS
464 uint16_t shiftReg;
465 uint8_t *output;
466 int len;
467 int sumI;
468 int sumQ;
15c4dc5a 469} Demod;
470
471/*
472 * Handles reception of a bit from the tag
473 *
51d4f6f1 474 * This function is called 2 times per bit (every 4 subcarrier cycles).
475 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
476 *
15c4dc5a 477 * LED handling:
478 * LED C -> ON once we have received the SOF and are expecting the rest.
479 * LED C -> OFF once we have received EOF or are unsynced
480 *
481 * Returns: true if we received a EOF
482 * false if we are still waiting for some more
483 *
484 */
51d4f6f1 485static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
15c4dc5a 486{
7d5ebac9 487 int v;
15c4dc5a 488
51d4f6f1 489// The soft decision on the bit uses an estimate of just the
490// quadrant of the reference angle, not the exact angle.
15c4dc5a 491#define MAKE_SOFT_DECISION() { \
7d5ebac9
MHS
492 if(Demod.sumI > 0) { \
493 v = ci; \
494 } else { \
495 v = -ci; \
496 } \
497 if(Demod.sumQ > 0) { \
498 v += cq; \
499 } else { \
500 v -= cq; \
501 } \
502 }
15c4dc5a 503
51d4f6f1 504#define SUBCARRIER_DETECT_THRESHOLD 8
505
506// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
507/* #define CHECK_FOR_SUBCARRIER() { \
508 v = ci; \
509 if(v < 0) v = -v; \
510 if(cq > 0) { \
511 v += cq; \
512 } else { \
513 v -= cq; \
514 } \
515 }
516 */
517// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
518#define CHECK_FOR_SUBCARRIER() { \
519 if(ci < 0) { \
520 if(cq < 0) { /* ci < 0, cq < 0 */ \
521 if (cq < ci) { \
522 v = -cq - (ci >> 1); \
523 } else { \
524 v = -ci - (cq >> 1); \
525 } \
526 } else { /* ci < 0, cq >= 0 */ \
527 if (cq < -ci) { \
528 v = -ci + (cq >> 1); \
529 } else { \
530 v = cq - (ci >> 1); \
531 } \
532 } \
533 } else { \
534 if(cq < 0) { /* ci >= 0, cq < 0 */ \
535 if (-cq < ci) { \
536 v = ci - (cq >> 1); \
537 } else { \
538 v = -cq + (ci >> 1); \
539 } \
540 } else { /* ci >= 0, cq >= 0 */ \
541 if (cq < ci) { \
542 v = ci + (cq >> 1); \
543 } else { \
544 v = cq + (ci >> 1); \
545 } \
546 } \
547 } \
548 }
549
7d5ebac9
MHS
550 switch(Demod.state) {
551 case DEMOD_UNSYNCD:
51d4f6f1 552 CHECK_FOR_SUBCARRIER();
553 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
7d5ebac9 554 Demod.state = DEMOD_PHASE_REF_TRAINING;
51d4f6f1 555 Demod.sumI = ci;
556 Demod.sumQ = cq;
557 Demod.posCount = 1;
558 }
7d5ebac9
MHS
559 break;
560
561 case DEMOD_PHASE_REF_TRAINING:
562 if(Demod.posCount < 8) {
51d4f6f1 563 CHECK_FOR_SUBCARRIER();
564 if (v > SUBCARRIER_DETECT_THRESHOLD) {
565 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
566 // note: synchronization time > 80 1/fs
567 Demod.sumI += ci;
568 Demod.sumQ += cq;
569 Demod.posCount++;
570 } else { // subcarrier lost
571 Demod.state = DEMOD_UNSYNCD;
7d5ebac9 572 }
51d4f6f1 573 } else {
574 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
7d5ebac9 575 }
7d5ebac9
MHS
576 break;
577
578 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
579 MAKE_SOFT_DECISION();
51d4f6f1 580 if(v < 0) { // logic '0' detected
7d5ebac9 581 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
51d4f6f1 582 Demod.posCount = 0; // start of SOF sequence
7d5ebac9 583 } else {
51d4f6f1 584 if(Demod.posCount > 200/4) { // maximum length of TR1 = 200 1/fs
7d5ebac9
MHS
585 Demod.state = DEMOD_UNSYNCD;
586 }
587 }
588 Demod.posCount++;
589 break;
590
591 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
51d4f6f1 592 Demod.posCount++;
7d5ebac9
MHS
593 MAKE_SOFT_DECISION();
594 if(v > 0) {
51d4f6f1 595 if(Demod.posCount < 9*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
7d5ebac9
MHS
596 Demod.state = DEMOD_UNSYNCD;
597 } else {
598 LED_C_ON(); // Got SOF
599 Demod.state = DEMOD_AWAITING_START_BIT;
600 Demod.posCount = 0;
601 Demod.len = 0;
51d4f6f1 602/* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
7d5ebac9
MHS
603 Demod.metricN = 0;
604 Demod.metric = 0;
51d4f6f1 605*/
7d5ebac9
MHS
606 }
607 } else {
51d4f6f1 608 if(Demod.posCount > 12*2) { // low phase of SOF too long (> 12 etu)
7d5ebac9 609 Demod.state = DEMOD_UNSYNCD;
09c66f1f 610 LED_C_OFF();
7d5ebac9
MHS
611 }
612 }
7d5ebac9
MHS
613 break;
614
615 case DEMOD_AWAITING_START_BIT:
51d4f6f1 616 Demod.posCount++;
7d5ebac9
MHS
617 MAKE_SOFT_DECISION();
618 if(v > 0) {
51d4f6f1 619 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
7d5ebac9 620 Demod.state = DEMOD_UNSYNCD;
09c66f1f 621 LED_C_OFF();
7d5ebac9 622 }
51d4f6f1 623 } else { // start bit detected
7d5ebac9 624 Demod.bitCount = 0;
51d4f6f1 625 Demod.posCount = 1; // this was the first half
7d5ebac9
MHS
626 Demod.thisBit = v;
627 Demod.shiftReg = 0;
628 Demod.state = DEMOD_RECEIVING_DATA;
629 }
630 break;
631
632 case DEMOD_RECEIVING_DATA:
633 MAKE_SOFT_DECISION();
51d4f6f1 634 if(Demod.posCount == 0) { // first half of bit
7d5ebac9
MHS
635 Demod.thisBit = v;
636 Demod.posCount = 1;
51d4f6f1 637 } else { // second half of bit
7d5ebac9
MHS
638 Demod.thisBit += v;
639
51d4f6f1 640/* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
7d5ebac9
MHS
641 if(Demod.thisBit > 0) {
642 Demod.metric += Demod.thisBit;
643 } else {
644 Demod.metric -= Demod.thisBit;
645 }
646 (Demod.metricN)++;
51d4f6f1 647*/
7d5ebac9
MHS
648
649 Demod.shiftReg >>= 1;
51d4f6f1 650 if(Demod.thisBit > 0) { // logic '1'
7d5ebac9
MHS
651 Demod.shiftReg |= 0x200;
652 }
653
654 Demod.bitCount++;
655 if(Demod.bitCount == 10) {
656 uint16_t s = Demod.shiftReg;
51d4f6f1 657 if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
7d5ebac9
MHS
658 uint8_t b = (s >> 1);
659 Demod.output[Demod.len] = b;
660 Demod.len++;
661 Demod.state = DEMOD_AWAITING_START_BIT;
7d5ebac9
MHS
662 } else {
663 Demod.state = DEMOD_UNSYNCD;
09c66f1f 664 LED_C_OFF();
665 if(s == 0x000) {
51d4f6f1 666 // This is EOF (start, stop and all data bits == '0'
09c66f1f 667 return TRUE;
668 }
7d5ebac9
MHS
669 }
670 }
671 Demod.posCount = 0;
672 }
673 break;
674
675 default:
676 Demod.state = DEMOD_UNSYNCD;
09c66f1f 677 LED_C_OFF();
7d5ebac9
MHS
678 break;
679 }
680
7d5ebac9
MHS
681 return FALSE;
682}
67ac4bf7 683
684
aeadbdb2
MHS
685static void DemodReset()
686{
687 // Clear out the state of the "UART" that receives from the tag.
aeadbdb2
MHS
688 Demod.len = 0;
689 Demod.state = DEMOD_UNSYNCD;
51d4f6f1 690 Demod.posCount = 0;
aeadbdb2 691 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
7d5ebac9 692}
67ac4bf7 693
694
7d5ebac9
MHS
695static void DemodInit(uint8_t *data)
696{
697 Demod.output = data;
698 DemodReset();
aeadbdb2
MHS
699}
700
67ac4bf7 701
15c4dc5a 702/*
355c8b4a 703 * Demodulate the samples we received from the tag, also log to tracebuffer
15c4dc5a 704 * quiet: set to 'TRUE' to disable debug output
705 */
51d4f6f1 706static void GetSamplesFor14443bDemod(int n, bool quiet)
15c4dc5a 707{
7d5ebac9 708 int max = 0;
51d4f6f1 709 bool gotFrame = FALSE;
7d5ebac9
MHS
710 int lastRxCounter, ci, cq, samples = 0;
711
712 // Allocate memory from BigBuf for some buffers
713 // free all previous allocations first
714 BigBuf_free();
715
7d5ebac9
MHS
716 // The response (tag -> reader) that we're receiving.
717 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
718
719 // The DMA buffer, used to stream samples from the FPGA
132a0217 720 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(DMA_BUFFER_SIZE);
15c4dc5a 721
7d5ebac9
MHS
722 // Set up the demodulator for tag -> reader responses.
723 DemodInit(receivedResponse);
15c4dc5a 724
7d5ebac9 725 // Setup and start DMA.
132a0217 726 FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE);
15c4dc5a 727
67ac4bf7 728 int8_t *upTo = dmaBuf;
132a0217 729 lastRxCounter = DMA_BUFFER_SIZE;
15c4dc5a 730
7d5ebac9 731 // Signal field is ON with the appropriate LED:
51d4f6f1 732 LED_D_ON();
7d5ebac9 733 // And put the FPGA in the appropriate mode
da586b17 734 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
15c4dc5a 735
7d5ebac9
MHS
736 for(;;) {
737 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
738 if(behindBy > max) max = behindBy;
15c4dc5a 739
132a0217 740 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (DMA_BUFFER_SIZE-1)) > 2) {
7d5ebac9
MHS
741 ci = upTo[0];
742 cq = upTo[1];
743 upTo += 2;
132a0217 744 if(upTo >= dmaBuf + DMA_BUFFER_SIZE) {
0d9a86c7 745 upTo = dmaBuf;
7d5ebac9 746 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
132a0217 747 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
7d5ebac9
MHS
748 }
749 lastRxCounter -= 2;
750 if(lastRxCounter <= 0) {
132a0217 751 lastRxCounter += DMA_BUFFER_SIZE;
7d5ebac9 752 }
15c4dc5a 753
7d5ebac9 754 samples += 2;
15c4dc5a 755
51d4f6f1 756 if(Handle14443bSamplesDemod(ci, cq)) {
757 gotFrame = TRUE;
758 break;
7d5ebac9
MHS
759 }
760 }
15c4dc5a 761
51d4f6f1 762 if(samples > n || gotFrame) {
7d5ebac9
MHS
763 break;
764 }
765 }
51d4f6f1 766
7d5ebac9 767 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
51d4f6f1 768
769 if (!quiet) Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", max, samples, gotFrame, Demod.len, Demod.sumI, Demod.sumQ);
355c8b4a
MHS
770 //Tracing
771 if (tracing && Demod.len > 0) {
772 uint8_t parity[MAX_PARITY_SIZE];
d5875804 773 //GetParity(Demod.output, Demod.len, parity);
0d9a86c7 774 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
355c8b4a 775 }
15c4dc5a 776}
777
67ac4bf7 778
15c4dc5a 779//-----------------------------------------------------------------------------
780// Transmit the command (to the tag) that was placed in ToSend[].
781//-----------------------------------------------------------------------------
51d4f6f1 782static void TransmitFor14443b(void)
15c4dc5a 783{
7d5ebac9 784 int c;
15c4dc5a 785
7d5ebac9 786 FpgaSetupSsc();
15c4dc5a 787
7d5ebac9
MHS
788 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
789 AT91C_BASE_SSC->SSC_THR = 0xff;
790 }
15c4dc5a 791
7d5ebac9 792 // Signal field is ON with the appropriate Red LED
15c4dc5a 793 LED_D_ON();
794 // Signal we are transmitting with the Green LED
795 LED_B_ON();
51d4f6f1 796 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
7d5ebac9
MHS
797
798 for(c = 0; c < 10;) {
799 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
800 AT91C_BASE_SSC->SSC_THR = 0xff;
801 c++;
802 }
803 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
804 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
805 (void)r;
806 }
807 WDT_HIT();
808 }
809
810 c = 0;
811 for(;;) {
812 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
813 AT91C_BASE_SSC->SSC_THR = ToSend[c];
814 c++;
815 if(c >= ToSendMax) {
816 break;
817 }
818 }
819 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
820 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
821 (void)r;
822 }
823 WDT_HIT();
824 }
825 LED_B_OFF(); // Finished sending
15c4dc5a 826}
827
67ac4bf7 828
15c4dc5a 829//-----------------------------------------------------------------------------
830// Code a layer 2 command (string of octets, including CRC) into ToSend[],
51d4f6f1 831// so that it is ready to transmit to the tag using TransmitFor14443b().
15c4dc5a 832//-----------------------------------------------------------------------------
7cf3ef20 833static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
15c4dc5a 834{
7d5ebac9
MHS
835 int i, j;
836 uint8_t b;
837
838 ToSendReset();
839
840 // Establish initial reference level
841 for(i = 0; i < 40; i++) {
842 ToSendStuffBit(1);
843 }
844 // Send SOF
845 for(i = 0; i < 10; i++) {
846 ToSendStuffBit(0);
847 }
848
849 for(i = 0; i < len; i++) {
850 // Stop bits/EGT
851 ToSendStuffBit(1);
852 ToSendStuffBit(1);
853 // Start bit
854 ToSendStuffBit(0);
855 // Data bits
856 b = cmd[i];
857 for(j = 0; j < 8; j++) {
858 if(b & 1) {
859 ToSendStuffBit(1);
860 } else {
861 ToSendStuffBit(0);
862 }
863 b >>= 1;
864 }
865 }
866 // Send EOF
867 ToSendStuffBit(1);
868 for(i = 0; i < 10; i++) {
869 ToSendStuffBit(0);
870 }
871 for(i = 0; i < 8; i++) {
872 ToSendStuffBit(1);
873 }
874
875 // And then a little more, to make sure that the last character makes
876 // it out before we switch to rx mode.
877 for(i = 0; i < 24; i++) {
878 ToSendStuffBit(1);
879 }
880
881 // Convert from last character reference to length
882 ToSendMax++;
15c4dc5a 883}
884
67ac4bf7 885
355c8b4a
MHS
886/**
887 Convenience function to encode, transmit and trace iso 14443b comms
888 **/
889static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
890{
891 CodeIso14443bAsReader(cmd, len);
51d4f6f1 892 TransmitFor14443b();
355c8b4a
MHS
893 if (tracing) {
894 uint8_t parity[MAX_PARITY_SIZE];
895 GetParity(cmd, len, parity);
896 LogTrace(cmd,len, 0, 0, parity, TRUE);
897 }
898}
899
67ac4bf7 900
15c4dc5a 901//-----------------------------------------------------------------------------
51d4f6f1 902// Read a SRI512 ISO 14443B tag.
15c4dc5a 903//
904// SRI512 tags are just simple memory tags, here we're looking at making a dump
905// of the contents of the memory. No anticollision algorithm is done, we assume
906// we have a single tag in the field.
907//
908// I tried to be systematic and check every answer of the tag, every CRC, etc...
909//-----------------------------------------------------------------------------
51d4f6f1 910void ReadSTMemoryIso14443b(uint32_t dwLast)
15c4dc5a 911{
355c8b4a
MHS
912 clear_trace();
913 set_tracing(TRUE);
914
7d5ebac9 915 uint8_t i = 0x00;
15c4dc5a 916
7d5ebac9
MHS
917 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
918 // Make sure that we start from off, since the tags are stateful;
919 // confusing things will happen if we don't reset them between reads.
920 LED_D_OFF();
921 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
922 SpinDelay(200);
15c4dc5a 923
7d5ebac9
MHS
924 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
925 FpgaSetupSsc();
15c4dc5a 926
7d5ebac9
MHS
927 // Now give it time to spin up.
928 // Signal field is on with the appropriate LED
929 LED_D_ON();
930 FpgaWriteConfWord(
da586b17 931 FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
7d5ebac9 932 SpinDelay(200);
15c4dc5a 933
7d5ebac9 934 // First command: wake up the tag using the INITIATE command
51d4f6f1 935 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
355c8b4a
MHS
936
937 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
15c4dc5a 938// LED_A_ON();
51d4f6f1 939 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
15c4dc5a 940// LED_A_OFF();
941
7d5ebac9 942 if (Demod.len == 0) {
15c4dc5a 943 DbpString("No response from tag");
944 return;
7d5ebac9 945 } else {
132a0217 946 Dbprintf("Randomly generated UID from tag (+ 2 byte CRC): %02x %02x %02x",
51d4f6f1 947 Demod.output[0], Demod.output[1], Demod.output[2]);
7d5ebac9
MHS
948 }
949 // There is a response, SELECT the uid
950 DbpString("Now SELECT tag:");
951 cmd1[0] = 0x0E; // 0x0E is SELECT
952 cmd1[1] = Demod.output[0];
953 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
355c8b4a
MHS
954 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
955
15c4dc5a 956// LED_A_ON();
51d4f6f1 957 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
15c4dc5a 958// LED_A_OFF();
7d5ebac9 959 if (Demod.len != 3) {
51d4f6f1 960 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
961 return;
7d5ebac9
MHS
962 }
963 // Check the CRC of the answer:
964 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
965 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
51d4f6f1 966 DbpString("CRC Error reading select response.");
967 return;
7d5ebac9
MHS
968 }
969 // Check response from the tag: should be the same UID as the command we just sent:
970 if (cmd1[1] != Demod.output[0]) {
132a0217 971 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
51d4f6f1 972 return;
7d5ebac9
MHS
973 }
974 // Tag is now selected,
975 // First get the tag's UID:
976 cmd1[0] = 0x0B;
977 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
355c8b4a
MHS
978 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
979
15c4dc5a 980// LED_A_ON();
51d4f6f1 981 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
15c4dc5a 982// LED_A_OFF();
7d5ebac9 983 if (Demod.len != 10) {
51d4f6f1 984 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
985 return;
7d5ebac9
MHS
986 }
987 // The check the CRC of the answer (use cmd1 as temporary variable):
988 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
51d4f6f1 989 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
132a0217 990 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
51d4f6f1 991 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
992 // Do not return;, let's go on... (we should retry, maybe ?)
7d5ebac9
MHS
993 }
994 Dbprintf("Tag UID (64 bits): %08x %08x",
51d4f6f1 995 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
996 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
15c4dc5a 997
7d5ebac9 998 // Now loop to read all 16 blocks, address from 0 to last block
132a0217 999 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
7d5ebac9
MHS
1000 cmd1[0] = 0x08;
1001 i = 0x00;
1002 dwLast++;
1003 for (;;) {
51d4f6f1 1004 if (i == dwLast) {
7d5ebac9
MHS
1005 DbpString("System area block (0xff):");
1006 i = 0xff;
1007 }
1008 cmd1[1] = i;
1009 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
355c8b4a
MHS
1010 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1011
15c4dc5a 1012// LED_A_ON();
51d4f6f1 1013 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
15c4dc5a 1014// LED_A_OFF();
7d5ebac9 1015 if (Demod.len != 6) { // Check if we got an answer from the tag
51d4f6f1 1016 DbpString("Expected 6 bytes from tag, got less...");
1017 return;
7d5ebac9
MHS
1018 }
1019 // The check the CRC of the answer (use cmd1 as temporary variable):
1020 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
51d4f6f1 1021 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
132a0217 1022 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
51d4f6f1 1023 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1024 // Do not return;, let's go on... (we should retry, maybe ?)
7d5ebac9
MHS
1025 }
1026 // Now print out the memory location:
132a0217 1027 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
51d4f6f1 1028 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1029 (Demod.output[4]<<8)+Demod.output[5]);
7d5ebac9 1030 if (i == 0xff) {
51d4f6f1 1031 break;
7d5ebac9
MHS
1032 }
1033 i++;
1034 }
15c4dc5a 1035}
1036
1037
1038//=============================================================================
1039// Finally, the `sniffer' combines elements from both the reader and
1040// simulated tag, to show both sides of the conversation.
1041//=============================================================================
1042
1043//-----------------------------------------------------------------------------
1044// Record the sequence of commands sent by the reader to the tag, with
1045// triggering so that we start recording at the point that the tag is moved
1046// near the reader.
1047//-----------------------------------------------------------------------------
1048/*
1049 * Memory usage for this function, (within BigBuf)
5b95953d 1050 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1051 * Last Received command (tag->reader) - MAX_FRAME_SIZE
132a0217 1052 * DMA Buffer - DMA_BUFFER_SIZE
5b95953d 1053 * Demodulated samples received - all the rest
15c4dc5a 1054 */
51d4f6f1 1055void RAMFUNC SnoopIso14443b(void)
15c4dc5a 1056{
7d5ebac9
MHS
1057 // We won't start recording the frames that we acquire until we trigger;
1058 // a good trigger condition to get started is probably when we see a
1059 // response from the tag.
5b95953d 1060 int triggered = TRUE; // TODO: set and evaluate trigger condition
15c4dc5a 1061
7d5ebac9 1062 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
f71f4deb 1063 BigBuf_free();
15c4dc5a 1064
aeadbdb2
MHS
1065 clear_trace();
1066 set_tracing(TRUE);
1067
7d5ebac9 1068 // The DMA buffer, used to stream samples from the FPGA
132a0217 1069 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(DMA_BUFFER_SIZE);
7d5ebac9 1070 int lastRxCounter;
67ac4bf7 1071 int8_t *upTo;
7d5ebac9
MHS
1072 int ci, cq;
1073 int maxBehindBy = 0;
1074
1075 // Count of samples received so far, so that we can include timing
1076 // information in the trace buffer.
1077 int samples = 0;
15c4dc5a 1078
7d5ebac9
MHS
1079 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1080 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
15c4dc5a 1081
7d5ebac9
MHS
1082 // Print some debug information about the buffer sizes
1083 Dbprintf("Snooping buffers initialized:");
1084 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
aeadbdb2
MHS
1085 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1086 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
132a0217 1087 Dbprintf(" DMA: %i bytes", DMA_BUFFER_SIZE);
e30c654b 1088
51d4f6f1 1089 // Signal field is off, no reader signal, no tag signal
1090 LEDsoff();
aeadbdb2
MHS
1091
1092 // And put the FPGA in the appropriate mode
da586b17 1093 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
7d5ebac9
MHS
1094 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1095
1096 // Setup for the DMA.
1097 FpgaSetupSsc();
1098 upTo = dmaBuf;
132a0217 1099 lastRxCounter = DMA_BUFFER_SIZE;
1100 FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE);
aeadbdb2 1101 uint8_t parity[MAX_PARITY_SIZE];
5b95953d 1102
1103 bool TagIsActive = FALSE;
1104 bool ReaderIsActive = FALSE;
1105
7d5ebac9
MHS
1106 // And now we loop, receiving samples.
1107 for(;;) {
1108 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
132a0217 1109 (DMA_BUFFER_SIZE-1);
7d5ebac9
MHS
1110 if(behindBy > maxBehindBy) {
1111 maxBehindBy = behindBy;
7d5ebac9 1112 }
51d4f6f1 1113
7d5ebac9
MHS
1114 if(behindBy < 2) continue;
1115
1116 ci = upTo[0];
1117 cq = upTo[1];
1118 upTo += 2;
1119 lastRxCounter -= 2;
132a0217 1120 if(upTo >= dmaBuf + DMA_BUFFER_SIZE) {
0d9a86c7 1121 upTo = dmaBuf;
132a0217 1122 lastRxCounter += DMA_BUFFER_SIZE;
0d9a86c7 1123 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
132a0217 1124 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
51d4f6f1 1125 WDT_HIT();
132a0217 1126 if(behindBy > (9*DMA_BUFFER_SIZE/10)) { // TODO: understand whether we can increase/decrease as we want or not?
1127 Dbprintf("blew circular buffer! behindBy=%d", behindBy);
51d4f6f1 1128 break;
1129 }
1130 if(!tracing) {
1131 DbpString("Reached trace limit");
1132 break;
1133 }
1134 if(BUTTON_PRESS()) {
1135 DbpString("cancelled");
1136 break;
1137 }
7d5ebac9 1138 }
15c4dc5a 1139
7d5ebac9 1140 samples += 2;
15c4dc5a 1141
5b95953d 1142 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
51d4f6f1 1143 if(Handle14443bUartBit(ci & 0x01)) {
5b95953d 1144 if(triggered && tracing) {
d5875804 1145 //GetParity(Uart.output, Uart.byteCnt, parity);
51d4f6f1 1146 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
5b95953d 1147 }
5b95953d 1148 /* And ready to receive another command. */
1149 UartReset();
1150 /* And also reset the demod code, which might have been */
1151 /* false-triggered by the commands from the reader. */
1152 DemodReset();
aeadbdb2 1153 }
51d4f6f1 1154 if(Handle14443bUartBit(cq & 0x01)) {
5b95953d 1155 if(triggered && tracing) {
d5875804 1156 //GetParity(Uart.output, Uart.byteCnt, parity);
51d4f6f1 1157 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
5b95953d 1158 }
5b95953d 1159 /* And ready to receive another command. */
1160 UartReset();
1161 /* And also reset the demod code, which might have been */
1162 /* false-triggered by the commands from the reader. */
1163 DemodReset();
1164 }
46734099 1165 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
aeadbdb2 1166 }
15c4dc5a 1167
5b95953d 1168 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
46734099 1169 if(Handle14443bSamplesDemod(ci | 0x01, cq | 0x01)) {
15c4dc5a 1170
5b95953d 1171 //Use samples as a time measurement
1172 if(tracing)
1173 {
1174 uint8_t parity[MAX_PARITY_SIZE];
d5875804 1175 //GetParity(Demod.output, Demod.len, parity);
09c66f1f 1176 LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
5b95953d 1177 }
1178 triggered = TRUE;
15c4dc5a 1179
5b95953d 1180 // And ready to receive another response.
1181 DemodReset();
1182 }
d5875804 1183 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
aeadbdb2 1184 }
15c4dc5a 1185
7d5ebac9 1186 }
51d4f6f1 1187
aeadbdb2 1188 FpgaDisableSscDma();
51d4f6f1 1189 LEDsoff();
aeadbdb2 1190 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
15c4dc5a 1191 DbpString("Snoop statistics:");
355c8b4a 1192 Dbprintf(" Max behind by: %i", maxBehindBy);
15c4dc5a 1193 Dbprintf(" Uart State: %x", Uart.state);
1194 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1195 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
3000dc4e 1196 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
15c4dc5a 1197}
7cf3ef20 1198
67ac4bf7 1199
7cf3ef20 1200/*
1201 * Send raw command to tag ISO14443B
1202 * @Input
1203 * datalen len of buffer data
1204 * recv bool when true wait for data from tag and send to client
1205 * powerfield bool leave the field on when true
1206 * data buffer with byte to send
1207 *
1208 * @Output
1209 * none
1210 *
1211 */
67ac4bf7 1212void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
7cf3ef20 1213{
7d5ebac9 1214 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
51d4f6f1 1215 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1216 FpgaSetupSsc();
1217
1218 set_tracing(TRUE);
1219
1220/* if(!powerfield) {
7d5ebac9
MHS
1221 // Make sure that we start from off, since the tags are stateful;
1222 // confusing things will happen if we don't reset them between reads.
1223 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1224 LED_D_OFF();
1225 SpinDelay(200);
1226 }
51d4f6f1 1227 */
7d5ebac9 1228
51d4f6f1 1229 // if(!GETBIT(GPIO_LED_D)) { // if field is off
da586b17 1230 // FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
51d4f6f1 1231 // // Signal field is on with the appropriate LED
1232 // LED_D_ON();
1233 // SpinDelay(200);
1234 // }
7cf3ef20 1235
355c8b4a
MHS
1236 CodeAndTransmit14443bAsReader(data, datalen);
1237
51d4f6f1 1238 if(recv) {
1239 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1240 uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1241 cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
7d5ebac9 1242 }
51d4f6f1 1243
1244 if(!powerfield) {
7d5ebac9
MHS
1245 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1246 LED_D_OFF();
1247 }
7cf3ef20 1248}
1249
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