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New FPGA code for bidirectional LF emulation
[proxmark3-svn] / fpga / hi_read_tx.v
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6658905f 1//-----------------------------------------------------------------------------\r
2// The way that we connect things when transmitting a command to an ISO\r
3// 15693 tag, using 100% modulation only for now.\r
4//\r
5// Jonathan Westhues, April 2006\r
6//-----------------------------------------------------------------------------\r
7\r
8module hi_read_tx(\r
9 pck0, ck_1356meg, ck_1356megb,\r
10 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
11 adc_d, adc_clk,\r
12 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
13 cross_hi, cross_lo,\r
14 dbg,\r
15 shallow_modulation\r
16);\r
17 input pck0, ck_1356meg, ck_1356megb;\r
18 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
19 input [7:0] adc_d;\r
20 output adc_clk;\r
21 input ssp_dout;\r
22 output ssp_frame, ssp_din, ssp_clk;\r
23 input cross_hi, cross_lo;\r
24 output dbg;\r
25 input shallow_modulation;\r
26\r
27// The high-frequency stuff. For now, for testing, just bring out the carrier,\r
28// and allow the ARM to modulate it over the SSP.\r
29reg pwr_hi;\r
30reg pwr_oe1;\r
31reg pwr_oe2;\r
32reg pwr_oe3;\r
33reg pwr_oe4;\r
34always @(ck_1356megb or ssp_dout or shallow_modulation)\r
35begin\r
36 if(shallow_modulation)\r
37 begin\r
38 pwr_hi <= ck_1356megb;\r
39 pwr_oe1 <= ~ssp_dout;\r
40 pwr_oe2 <= ~ssp_dout;\r
41 pwr_oe3 <= ~ssp_dout;\r
42 pwr_oe4 <= 1'b0;\r
43 end\r
44 else\r
45 begin\r
46 pwr_hi <= ck_1356megb & ssp_dout;\r
47 pwr_oe1 <= 1'b0;\r
48 pwr_oe2 <= 1'b0;\r
49 pwr_oe3 <= 1'b0;\r
50 pwr_oe4 <= 1'b0;\r
51 end\r
52end\r
53\r
54// Then just divide the 13.56 MHz clock down to produce appropriate clocks\r
55// for the synchronous serial port.\r
56\r
57reg [6:0] hi_div_by_128;\r
58\r
59always @(posedge ck_1356meg)\r
60 hi_div_by_128 <= hi_div_by_128 + 1;\r
61\r
62assign ssp_clk = hi_div_by_128[6];\r
63\r
64reg [2:0] hi_byte_div;\r
65\r
66always @(negedge ssp_clk)\r
67 hi_byte_div <= hi_byte_div + 1;\r
68\r
69assign ssp_frame = (hi_byte_div == 3'b000);\r
70\r
71assign ssp_din = 1'b0;\r
72\r
73assign pwr_lo = 1'b0;\r
74assign dbg = ssp_frame;\r
75\r
76endmodule\r
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