New FPGA code for bidirectional LF emulation

diff --git a/fpga/fpga.bit b/fpga/fpga.bit
index d3a418089f1e52de233b83eec20819cbef352b10..503f041fb85c92101a5a0ae945b9d228b73ee4d0 100644 (file)
Binary files a/fpga/fpga.bit and b/fpga/fpga.bit differ

diff --git a/fpga/fpga.v b/fpga/fpga.v
index 8f8f38250c6a8039df43c79e2f0fa3d0e662d492..b22c9d5c70ff66fd67ec37029f46e8fcd78cb1c6 100644 (file)
--- a/fpga/fpga.v
+++ b/fpga/fpga.v
@@ -138,7 +138,7 @@ lo_simulate ls(
        adc_d, ls_adc_clk,\r
        ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,\r
        cross_hi, cross_lo,\r
-       ls_dbg\r
+       ls_dbg, divisor\r
 );\r
 \r
 hi_read_tx ht(\r

diff --git a/fpga/lo_simulate.v b/fpga/lo_simulate.v
index 7eb910ba1db014b2ba2f01c317eb686dcec2e11a..9e3cd50abe79f3a541be3a69c65f5eb8e27f0c4f 100644 (file)
--- a/fpga/lo_simulate.v
+++ b/fpga/lo_simulate.v
@@ -12,7 +12,8 @@ module lo_simulate(
     adc_d, adc_clk,\r
     ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
     cross_hi, cross_lo,\r
-    dbg\r
+    dbg,
+        divisor\r
 );\r
     input pck0, ck_1356meg, ck_1356megb;\r
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
@@ -21,7 +22,8 @@ module lo_simulate(
     input ssp_dout;\r
     output ssp_frame, ssp_din, ssp_clk;\r
     input cross_hi, cross_lo;\r
-    output dbg;\r
+    output dbg;
+        input [7:0] divisor;\r
 \r
 // No logic, straight through.\r
 assign pwr_oe3 = 1'b0;\r
@@ -30,8 +32,51 @@ assign pwr_oe2 = ssp_dout;
 assign pwr_oe4 = ssp_dout;\r
 assign ssp_clk = cross_lo;\r
 assign pwr_lo = 1'b0;\r
-assign adc_clk = 1'b0;\r
 assign pwr_hi = 1'b0;\r
-assign dbg = cross_lo;\r
+assign dbg = ssp_frame;\r
+
+// Divide the clock to be used for the ADC
+reg [7:0] pck_divider;
+reg clk_state;
+\r
+always @(posedge pck0)\r
+begin\r
+       if(pck_divider == divisor[7:0])\r
+               begin\r
+                       pck_divider <= 8'd0;
+                       clk_state = !clk_state;\r
+               end\r
+       else\r
+       begin\r
+               pck_divider <= pck_divider + 1;\r
+       end\r
+end\r
+
+assign adc_clk = ~clk_state;
+
+// Toggle the output with hysteresis
+//  Set to high if the ADC value is above 200
+//  Set to low if the ADC value is below 64
+reg is_high;
+reg is_low;
+reg output_state;
+
+always @(posedge pck0)\r
+begin\r
+       if((pck_divider == 8'd7) && !clk_state) begin
+               is_high = (adc_d >= 8'd200);
+               is_low = (adc_d <= 8'd64);
+       end
+end
+
+always @(posedge is_high or posedge is_low)
+begin
+       if(is_high)
+               output_state <= 1'd1;
+       else if(is_low)
+               output_state <= 1'd0;
+end
+
+assign ssp_frame = output_state;
 \r
 endmodule\r