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[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18
19 #include "iso14443crc.h"
20 #include "iso14443a.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23 #include "BigBuf.h"
24 static uint32_t iso14a_timeout;
25 int rsamples = 0;
26 uint8_t trigger = 0;
27 // the block number for the ISO14443-4 PCB
28 static uint8_t iso14_pcb_blocknum = 0;
29
30 //
31 // ISO14443 timing:
32 //
33 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
34 #define REQUEST_GUARD_TIME (7000/16 + 1)
35 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
36 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
37 // bool LastCommandWasRequest = FALSE;
38
39 //
40 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
41 //
42 // When the PM acts as reader and is receiving tag data, it takes
43 // 3 ticks delay in the AD converter
44 // 16 ticks until the modulation detector completes and sets curbit
45 // 8 ticks until bit_to_arm is assigned from curbit
46 // 8*16 ticks for the transfer from FPGA to ARM
47 // 4*16 ticks until we measure the time
48 // - 8*16 ticks because we measure the time of the previous transfer
49 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
50
51 // When the PM acts as a reader and is sending, it takes
52 // 4*16 ticks until we can write data to the sending hold register
53 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
54 // 8 ticks until the first transfer starts
55 // 8 ticks later the FPGA samples the data
56 // 1 tick to assign mod_sig_coil
57 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
58
59 // When the PM acts as tag and is receiving it takes
60 // 2 ticks delay in the RF part (for the first falling edge),
61 // 3 ticks for the A/D conversion,
62 // 8 ticks on average until the start of the SSC transfer,
63 // 8 ticks until the SSC samples the first data
64 // 7*16 ticks to complete the transfer from FPGA to ARM
65 // 8 ticks until the next ssp_clk rising edge
66 // 4*16 ticks until we measure the time
67 // - 8*16 ticks because we measure the time of the previous transfer
68 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
69
70 // The FPGA will report its internal sending delay in
71 uint16_t FpgaSendQueueDelay;
72 // the 5 first bits are the number of bits buffered in mod_sig_buf
73 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
74 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
75
76 // When the PM acts as tag and is sending, it takes
77 // 4*16 ticks until we can write data to the sending hold register
78 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
79 // 8 ticks until the first transfer starts
80 // 8 ticks later the FPGA samples the data
81 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
82 // + 1 tick to assign mod_sig_coil
83 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
84
85 // When the PM acts as sniffer and is receiving tag data, it takes
86 // 3 ticks A/D conversion
87 // 14 ticks to complete the modulation detection
88 // 8 ticks (on average) until the result is stored in to_arm
89 // + the delays in transferring data - which is the same for
90 // sniffing reader and tag data and therefore not relevant
91 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
92
93 // When the PM acts as sniffer and is receiving reader data, it takes
94 // 2 ticks delay in analogue RF receiver (for the falling edge of the
95 // start bit, which marks the start of the communication)
96 // 3 ticks A/D conversion
97 // 8 ticks on average until the data is stored in to_arm.
98 // + the delays in transferring data - which is the same for
99 // sniffing reader and tag data and therefore not relevant
100 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
101
102 //variables used for timing purposes:
103 //these are in ssp_clk cycles:
104 static uint32_t NextTransferTime;
105 static uint32_t LastTimeProxToAirStart;
106 static uint32_t LastProxToAirDuration;
107
108
109
110 // CARD TO READER - manchester
111 // Sequence D: 11110000 modulation with subcarrier during first half
112 // Sequence E: 00001111 modulation with subcarrier during second half
113 // Sequence F: 00000000 no modulation with subcarrier
114 // READER TO CARD - miller
115 // Sequence X: 00001100 drop after half a period
116 // Sequence Y: 00000000 no drop
117 // Sequence Z: 11000000 drop at start
118 #define SEC_D 0xf0
119 #define SEC_E 0x0f
120 #define SEC_F 0x00
121 #define SEC_X 0x0c
122 #define SEC_Y 0x00
123 #define SEC_Z 0xc0
124
125 const uint8_t OddByteParity[256] = {
126 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
142 };
143
144
145 void iso14a_set_trigger(bool enable) {
146 trigger = enable;
147 }
148
149
150 void iso14a_set_timeout(uint32_t timeout) {
151 iso14a_timeout = timeout;
152 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
153 }
154
155
156 void iso14a_set_ATS_timeout(uint8_t *ats) {
157
158 uint8_t tb1;
159 uint8_t fwi;
160 uint32_t fwt;
161
162 if (ats[0] > 1) { // there is a format byte T0
163 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
164 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
165 tb1 = ats[3];
166 } else {
167 tb1 = ats[2];
168 }
169 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
170 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
171
172 iso14a_set_timeout(fwt/(8*16));
173 }
174 }
175 }
176
177
178 //-----------------------------------------------------------------------------
179 // Generate the parity value for a byte sequence
180 //
181 //-----------------------------------------------------------------------------
182 byte_t oddparity (const byte_t bt)
183 {
184 return OddByteParity[bt];
185 }
186
187 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
188 {
189 uint16_t paritybit_cnt = 0;
190 uint16_t paritybyte_cnt = 0;
191 uint8_t parityBits = 0;
192
193 for (uint16_t i = 0; i < iLen; i++) {
194 // Generate the parity bits
195 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
196 if (paritybit_cnt == 7) {
197 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
198 parityBits = 0; // and advance to next Parity Byte
199 paritybyte_cnt++;
200 paritybit_cnt = 0;
201 } else {
202 paritybit_cnt++;
203 }
204 }
205
206 // save remaining parity bits
207 par[paritybyte_cnt] = parityBits;
208
209 }
210
211 void AppendCrc14443a(uint8_t* data, int len)
212 {
213 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
214 }
215
216 //=============================================================================
217 // ISO 14443 Type A - Miller decoder
218 //=============================================================================
219 // Basics:
220 // This decoder is used when the PM3 acts as a tag.
221 // The reader will generate "pauses" by temporarily switching of the field.
222 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
223 // The FPGA does a comparison with a threshold and would deliver e.g.:
224 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
225 // The Miller decoder needs to identify the following sequences:
226 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
227 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
228 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
229 // Note 1: the bitstream may start at any time. We therefore need to sync.
230 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
231 //-----------------------------------------------------------------------------
232 static tUart Uart;
233
234 // Lookup-Table to decide if 4 raw bits are a modulation.
235 // We accept two or three consecutive "0" in any position with the rest "1"
236 const bool Mod_Miller_LUT[] = {
237 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
238 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
239 };
240 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
241 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
242
243 void UartReset()
244 {
245 Uart.state = STATE_UNSYNCD;
246 Uart.bitCount = 0;
247 Uart.len = 0; // number of decoded data bytes
248 Uart.parityLen = 0; // number of decoded parity bytes
249 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
250 Uart.parityBits = 0; // holds 8 parity bits
251 Uart.twoBits = 0x0000; // buffer for 2 Bits
252 Uart.highCnt = 0;
253 Uart.startTime = 0;
254 Uart.endTime = 0;
255 }
256
257 void UartInit(uint8_t *data, uint8_t *parity)
258 {
259 Uart.output = data;
260 Uart.parity = parity;
261 UartReset();
262 }
263
264 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
265 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
266 {
267
268 Uart.twoBits = (Uart.twoBits << 8) | bit;
269
270 if (Uart.state == STATE_UNSYNCD) { // not yet synced
271
272 if (Uart.highCnt < 2) { // wait for a stable unmodulated signal
273 if (Uart.twoBits == 0xffff) {
274 Uart.highCnt++;
275 } else {
276 Uart.highCnt = 0;
277 }
278 } else {
279 Uart.syncBit = 0xFFFF; // not set
280 // we look for a ...1111111100x11111xxxxxx pattern (the start bit)
281 if ((Uart.twoBits & 0xDF00) == 0x1F00) Uart.syncBit = 8; // mask is 11x11111 xxxxxxxx,
282 // check for 00x11111 xxxxxxxx
283 else if ((Uart.twoBits & 0xEF80) == 0x8F80) Uart.syncBit = 7; // both masks shifted right one bit, left padded with '1'
284 else if ((Uart.twoBits & 0xF7C0) == 0xC7C0) Uart.syncBit = 6; // ...
285 else if ((Uart.twoBits & 0xFBE0) == 0xE3E0) Uart.syncBit = 5;
286 else if ((Uart.twoBits & 0xFDF0) == 0xF1F0) Uart.syncBit = 4;
287 else if ((Uart.twoBits & 0xFEF8) == 0xF8F8) Uart.syncBit = 3;
288 else if ((Uart.twoBits & 0xFF7C) == 0xFC7C) Uart.syncBit = 2;
289 else if ((Uart.twoBits & 0xFFBE) == 0xFE3E) Uart.syncBit = 1;
290 if (Uart.syncBit != 0xFFFF) { // found a sync bit
291 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
292 Uart.startTime -= Uart.syncBit;
293 Uart.endTime = Uart.startTime;
294 Uart.state = STATE_START_OF_COMMUNICATION;
295 }
296 }
297
298 } else {
299
300 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
301 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
302 UartReset();
303 } else { // Modulation in first half = Sequence Z = logic "0"
304 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
305 UartReset();
306 } else {
307 Uart.bitCount++;
308 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
309 Uart.state = STATE_MILLER_Z;
310 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
311 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
312 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
313 Uart.parityBits <<= 1; // make room for the parity bit
314 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
315 Uart.bitCount = 0;
316 Uart.shiftReg = 0;
317 if((Uart.len&0x0007) == 0) { // every 8 data bytes
318 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
319 Uart.parityBits = 0;
320 }
321 }
322 }
323 }
324 } else {
325 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
326 Uart.bitCount++;
327 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
328 Uart.state = STATE_MILLER_X;
329 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
330 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
331 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
332 Uart.parityBits <<= 1; // make room for the new parity bit
333 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
334 Uart.bitCount = 0;
335 Uart.shiftReg = 0;
336 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
337 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
338 Uart.parityBits = 0;
339 }
340 }
341 } else { // no modulation in both halves - Sequence Y
342 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
343 Uart.state = STATE_UNSYNCD;
344 Uart.bitCount--; // last "0" was part of EOC sequence
345 Uart.shiftReg <<= 1; // drop it
346 if(Uart.bitCount > 0) { // if we decoded some bits
347 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
348 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
349 Uart.parityBits <<= 1; // add a (void) parity bit
350 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
351 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
352 return TRUE;
353 } else if (Uart.len & 0x0007) { // there are some parity bits to store
354 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
355 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
356 }
357 if (Uart.len) {
358 return TRUE; // we are finished with decoding the raw data sequence
359 } else {
360 UartReset(); // Nothing received - start over
361 Uart.highCnt = 1;
362 }
363 }
364 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
365 UartReset();
366 Uart.highCnt = 1;
367 } else { // a logic "0"
368 Uart.bitCount++;
369 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
370 Uart.state = STATE_MILLER_Y;
371 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
372 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
373 Uart.parityBits <<= 1; // make room for the parity bit
374 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
375 Uart.bitCount = 0;
376 Uart.shiftReg = 0;
377 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
378 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
379 Uart.parityBits = 0;
380 }
381 }
382 }
383 }
384 }
385
386 }
387
388 return FALSE; // not finished yet, need more data
389 }
390
391
392
393 //=============================================================================
394 // ISO 14443 Type A - Manchester decoder
395 //=============================================================================
396 // Basics:
397 // This decoder is used when the PM3 acts as a reader.
398 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
399 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
400 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
401 // The Manchester decoder needs to identify the following sequences:
402 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
403 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
404 // 8 ticks unmodulated: Sequence F = end of communication
405 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
406 // Note 1: the bitstream may start at any time. We therefore need to sync.
407 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
408 static tDemod Demod;
409
410 // Lookup-Table to decide if 4 raw bits are a modulation.
411 // We accept three or four "1" in any position
412 const bool Mod_Manchester_LUT[] = {
413 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
414 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
415 };
416
417 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
418 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
419
420
421 void DemodReset()
422 {
423 Demod.state = DEMOD_UNSYNCD;
424 Demod.len = 0; // number of decoded data bytes
425 Demod.parityLen = 0;
426 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
427 Demod.parityBits = 0; //
428 Demod.collisionPos = 0; // Position of collision bit
429 Demod.twoBits = 0xffff; // buffer for 2 Bits
430 Demod.highCnt = 0;
431 Demod.startTime = 0;
432 Demod.endTime = 0;
433 }
434
435 void DemodInit(uint8_t *data, uint8_t *parity)
436 {
437 Demod.output = data;
438 Demod.parity = parity;
439 DemodReset();
440 }
441
442 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
443 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
444 {
445
446 Demod.twoBits = (Demod.twoBits << 8) | bit;
447
448 if (Demod.state == DEMOD_UNSYNCD) {
449
450 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
451 if (Demod.twoBits == 0x0000) {
452 Demod.highCnt++;
453 } else {
454 Demod.highCnt = 0;
455 }
456 } else {
457 Demod.syncBit = 0xFFFF; // not set
458 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
459 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
460 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
461 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
462 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
463 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
464 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
465 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
466 if (Demod.syncBit != 0xFFFF) {
467 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
468 Demod.startTime -= Demod.syncBit;
469 Demod.bitCount = offset; // number of decoded data bits
470 Demod.state = DEMOD_MANCHESTER_DATA;
471 }
472 }
473
474 } else {
475
476 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
477 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
478 if (!Demod.collisionPos) {
479 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
480 }
481 } // modulation in first half only - Sequence D = 1
482 Demod.bitCount++;
483 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
484 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
485 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
486 Demod.parityBits <<= 1; // make room for the parity bit
487 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
488 Demod.bitCount = 0;
489 Demod.shiftReg = 0;
490 if((Demod.len&0x0007) == 0) { // every 8 data bytes
491 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
492 Demod.parityBits = 0;
493 }
494 }
495 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
496 } else { // no modulation in first half
497 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
498 Demod.bitCount++;
499 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
500 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
501 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
502 Demod.parityBits <<= 1; // make room for the new parity bit
503 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
504 Demod.bitCount = 0;
505 Demod.shiftReg = 0;
506 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
507 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
508 Demod.parityBits = 0;
509 }
510 }
511 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
512 } else { // no modulation in both halves - End of communication
513 if(Demod.bitCount > 0) { // there are some remaining data bits
514 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
515 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
516 Demod.parityBits <<= 1; // add a (void) parity bit
517 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
518 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
519 return TRUE;
520 } else if (Demod.len & 0x0007) { // there are some parity bits to store
521 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
522 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
523 }
524 if (Demod.len) {
525 return TRUE; // we are finished with decoding the raw data sequence
526 } else { // nothing received. Start over
527 DemodReset();
528 }
529 }
530 }
531
532 }
533
534 return FALSE; // not finished yet, need more data
535 }
536
537 //=============================================================================
538 // Finally, a `sniffer' for ISO 14443 Type A
539 // Both sides of communication!
540 //=============================================================================
541
542 //-----------------------------------------------------------------------------
543 // Record the sequence of commands sent by the reader to the tag, with
544 // triggering so that we start recording at the point that the tag is moved
545 // near the reader.
546 //-----------------------------------------------------------------------------
547 void RAMFUNC SnoopIso14443a(uint8_t param) {
548 // param:
549 // bit 0 - trigger from first card answer
550 // bit 1 - trigger from first reader 7-bit request
551
552 LEDsoff();
553
554 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
555
556 // Allocate memory from BigBuf for some buffers
557 // free all previous allocations first
558 BigBuf_free();
559
560 // The command (reader -> tag) that we're receiving.
561 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
562 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
563
564 // The response (tag -> reader) that we're receiving.
565 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
566 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
567
568 // The DMA buffer, used to stream samples from the FPGA
569 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
570
571 // init trace buffer
572 clear_trace();
573 set_tracing(TRUE);
574
575 uint8_t *data = dmaBuf;
576 uint8_t previous_data = 0;
577 int maxDataLen = 0;
578 int dataLen = 0;
579 bool TagIsActive = FALSE;
580 bool ReaderIsActive = FALSE;
581
582 // Set up the demodulator for tag -> reader responses.
583 DemodInit(receivedResponse, receivedResponsePar);
584
585 // Set up the demodulator for the reader -> tag commands
586 UartInit(receivedCmd, receivedCmdPar);
587
588 // Setup and start DMA.
589 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
590
591 // We won't start recording the frames that we acquire until we trigger;
592 // a good trigger condition to get started is probably when we see a
593 // response from the tag.
594 // triggered == FALSE -- to wait first for card
595 bool triggered = !(param & 0x03);
596
597 // And now we loop, receiving samples.
598 for(uint32_t rsamples = 0; TRUE; ) {
599
600 if(BUTTON_PRESS()) {
601 DbpString("cancelled by button");
602 break;
603 }
604
605 LED_A_ON();
606 WDT_HIT();
607
608 int register readBufDataP = data - dmaBuf;
609 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
610 if (readBufDataP <= dmaBufDataP){
611 dataLen = dmaBufDataP - readBufDataP;
612 } else {
613 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
614 }
615 // test for length of buffer
616 if(dataLen > maxDataLen) {
617 maxDataLen = dataLen;
618 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
619 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
620 break;
621 }
622 }
623 if(dataLen < 1) continue;
624
625 // primary buffer was stopped( <-- we lost data!
626 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
627 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
628 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
629 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
630 }
631 // secondary buffer sets as primary, secondary buffer was stopped
632 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
633 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
634 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
635 }
636
637 LED_A_OFF();
638
639 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
640
641 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
642 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
643 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
644 LED_C_ON();
645
646 // check - if there is a short 7bit request from reader
647 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
648
649 if(triggered) {
650 if (!LogTrace(receivedCmd,
651 Uart.len,
652 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
653 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
654 Uart.parity,
655 TRUE)) break;
656 }
657 /* And ready to receive another command. */
658 UartReset();
659 /* And also reset the demod code, which might have been */
660 /* false-triggered by the commands from the reader. */
661 DemodReset();
662 LED_B_OFF();
663 }
664 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
665 }
666
667 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
668 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
669 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
670 LED_B_ON();
671
672 if (!LogTrace(receivedResponse,
673 Demod.len,
674 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
675 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
676 Demod.parity,
677 FALSE)) break;
678
679 if ((!triggered) && (param & 0x01)) triggered = TRUE;
680
681 // And ready to receive another response.
682 DemodReset();
683 LED_C_OFF();
684 }
685 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
686 }
687 }
688
689 previous_data = *data;
690 rsamples++;
691 data++;
692 if(data == dmaBuf + DMA_BUFFER_SIZE) {
693 data = dmaBuf;
694 }
695 } // main cycle
696
697 DbpString("COMMAND FINISHED");
698
699 FpgaDisableSscDma();
700 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
701 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
702 LEDsoff();
703 }
704
705 //-----------------------------------------------------------------------------
706 // Prepare tag messages
707 //-----------------------------------------------------------------------------
708 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
709 {
710 ToSendReset();
711
712 // Correction bit, might be removed when not needed
713 ToSendStuffBit(0);
714 ToSendStuffBit(0);
715 ToSendStuffBit(0);
716 ToSendStuffBit(0);
717 ToSendStuffBit(1); // 1
718 ToSendStuffBit(0);
719 ToSendStuffBit(0);
720 ToSendStuffBit(0);
721
722 // Send startbit
723 ToSend[++ToSendMax] = SEC_D;
724 LastProxToAirDuration = 8 * ToSendMax - 4;
725
726 for(uint16_t i = 0; i < len; i++) {
727 uint8_t b = cmd[i];
728
729 // Data bits
730 for(uint16_t j = 0; j < 8; j++) {
731 if(b & 1) {
732 ToSend[++ToSendMax] = SEC_D;
733 } else {
734 ToSend[++ToSendMax] = SEC_E;
735 }
736 b >>= 1;
737 }
738
739 // Get the parity bit
740 if (parity[i>>3] & (0x80>>(i&0x0007))) {
741 ToSend[++ToSendMax] = SEC_D;
742 LastProxToAirDuration = 8 * ToSendMax - 4;
743 } else {
744 ToSend[++ToSendMax] = SEC_E;
745 LastProxToAirDuration = 8 * ToSendMax;
746 }
747 }
748
749 // Send stopbit
750 ToSend[++ToSendMax] = SEC_F;
751
752 // Convert from last byte pos to length
753 ToSendMax++;
754 }
755
756 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
757 {
758 uint8_t par[MAX_PARITY_SIZE];
759
760 GetParity(cmd, len, par);
761 CodeIso14443aAsTagPar(cmd, len, par);
762 }
763
764
765 static void Code4bitAnswerAsTag(uint8_t cmd)
766 {
767 int i;
768
769 ToSendReset();
770
771 // Correction bit, might be removed when not needed
772 ToSendStuffBit(0);
773 ToSendStuffBit(0);
774 ToSendStuffBit(0);
775 ToSendStuffBit(0);
776 ToSendStuffBit(1); // 1
777 ToSendStuffBit(0);
778 ToSendStuffBit(0);
779 ToSendStuffBit(0);
780
781 // Send startbit
782 ToSend[++ToSendMax] = SEC_D;
783
784 uint8_t b = cmd;
785 for(i = 0; i < 4; i++) {
786 if(b & 1) {
787 ToSend[++ToSendMax] = SEC_D;
788 LastProxToAirDuration = 8 * ToSendMax - 4;
789 } else {
790 ToSend[++ToSendMax] = SEC_E;
791 LastProxToAirDuration = 8 * ToSendMax;
792 }
793 b >>= 1;
794 }
795
796 // Send stopbit
797 ToSend[++ToSendMax] = SEC_F;
798
799 // Convert from last byte pos to length
800 ToSendMax++;
801 }
802
803 //-----------------------------------------------------------------------------
804 // Wait for commands from reader
805 // Stop when button is pressed
806 // Or return TRUE when command is captured
807 //-----------------------------------------------------------------------------
808 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
809 {
810 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
811 // only, since we are receiving, not transmitting).
812 // Signal field is off with the appropriate LED
813 LED_D_OFF();
814 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
815
816 // Now run a `software UART' on the stream of incoming samples.
817 UartInit(received, parity);
818
819 // clear RXRDY:
820 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
821
822 for(;;) {
823 WDT_HIT();
824
825 if(BUTTON_PRESS()) return FALSE;
826
827 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
828 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
829 if(MillerDecoding(b, 0)) {
830 *len = Uart.len;
831 return TRUE;
832 }
833 }
834 }
835 }
836
837 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
838 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
839 int EmSend4bit(uint8_t resp);
840 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
841 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
842 int EmSendCmd(uint8_t *resp, uint16_t respLen);
843 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
844 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
845 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
846
847 static uint8_t* free_buffer_pointer;
848
849 typedef struct {
850 uint8_t* response;
851 size_t response_n;
852 uint8_t* modulation;
853 size_t modulation_n;
854 uint32_t ProxToAirDuration;
855 } tag_response_info_t;
856
857 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
858 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
859 // This will need the following byte array for a modulation sequence
860 // 144 data bits (18 * 8)
861 // 18 parity bits
862 // 2 Start and stop
863 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
864 // 1 just for the case
865 // ----------- +
866 // 166 bytes, since every bit that needs to be send costs us a byte
867 //
868
869
870 // Prepare the tag modulation bits from the message
871 CodeIso14443aAsTag(response_info->response,response_info->response_n);
872
873 // Make sure we do not exceed the free buffer space
874 if (ToSendMax > max_buffer_size) {
875 Dbprintf("Out of memory, when modulating bits for tag answer:");
876 Dbhexdump(response_info->response_n,response_info->response,false);
877 return false;
878 }
879
880 // Copy the byte array, used for this modulation to the buffer position
881 memcpy(response_info->modulation,ToSend,ToSendMax);
882
883 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
884 response_info->modulation_n = ToSendMax;
885 response_info->ProxToAirDuration = LastProxToAirDuration;
886
887 return true;
888 }
889
890
891 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
892 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
893 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
894 // -> need 273 bytes buffer
895 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
896
897 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
898 // Retrieve and store the current buffer index
899 response_info->modulation = free_buffer_pointer;
900
901 // Determine the maximum size we can use from our buffer
902 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
903
904 // Forward the prepare tag modulation function to the inner function
905 if (prepare_tag_modulation(response_info, max_buffer_size)) {
906 // Update the free buffer offset
907 free_buffer_pointer += ToSendMax;
908 return true;
909 } else {
910 return false;
911 }
912 }
913
914 //-----------------------------------------------------------------------------
915 // Main loop of simulated tag: receive commands from reader, decide what
916 // response to send, and send it.
917 //-----------------------------------------------------------------------------
918 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
919 {
920 uint8_t sak;
921
922 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
923 uint8_t response1[2];
924
925 switch (tagType) {
926 case 1: { // MIFARE Classic
927 // Says: I am Mifare 1k - original line
928 response1[0] = 0x04;
929 response1[1] = 0x00;
930 sak = 0x08;
931 } break;
932 case 2: { // MIFARE Ultralight
933 // Says: I am a stupid memory tag, no crypto
934 response1[0] = 0x04;
935 response1[1] = 0x00;
936 sak = 0x00;
937 } break;
938 case 3: { // MIFARE DESFire
939 // Says: I am a DESFire tag, ph33r me
940 response1[0] = 0x04;
941 response1[1] = 0x03;
942 sak = 0x20;
943 } break;
944 case 4: { // ISO/IEC 14443-4
945 // Says: I am a javacard (JCOP)
946 response1[0] = 0x04;
947 response1[1] = 0x00;
948 sak = 0x28;
949 } break;
950 case 5: { // MIFARE TNP3XXX
951 // Says: I am a toy
952 response1[0] = 0x01;
953 response1[1] = 0x0f;
954 sak = 0x01;
955 } break;
956 default: {
957 Dbprintf("Error: unkown tagtype (%d)",tagType);
958 return;
959 } break;
960 }
961
962 // The second response contains the (mandatory) first 24 bits of the UID
963 uint8_t response2[5] = {0x00};
964
965 // Check if the uid uses the (optional) part
966 uint8_t response2a[5] = {0x00};
967
968 if (uid_2nd) {
969 response2[0] = 0x88;
970 num_to_bytes(uid_1st,3,response2+1);
971 num_to_bytes(uid_2nd,4,response2a);
972 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
973
974 // Configure the ATQA and SAK accordingly
975 response1[0] |= 0x40;
976 sak |= 0x04;
977 } else {
978 num_to_bytes(uid_1st,4,response2);
979 // Configure the ATQA and SAK accordingly
980 response1[0] &= 0xBF;
981 sak &= 0xFB;
982 }
983
984 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
985 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
986
987 // Prepare the mandatory SAK (for 4 and 7 byte UID)
988 uint8_t response3[3] = {0x00};
989 response3[0] = sak;
990 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
991
992 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
993 uint8_t response3a[3] = {0x00};
994 response3a[0] = sak & 0xFB;
995 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
996
997 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
998 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
999 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1000 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1001 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1002 // TC(1) = 0x02: CID supported, NAD not supported
1003 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1004
1005 #define TAG_RESPONSE_COUNT 7
1006 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1007 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1008 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1009 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1010 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1011 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1012 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1013 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1014 };
1015
1016 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1017 // Such a response is less time critical, so we can prepare them on the fly
1018 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1019 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1020 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1021 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1022 tag_response_info_t dynamic_response_info = {
1023 .response = dynamic_response_buffer,
1024 .response_n = 0,
1025 .modulation = dynamic_modulation_buffer,
1026 .modulation_n = 0
1027 };
1028
1029 // We need to listen to the high-frequency, peak-detected path.
1030 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1031
1032 BigBuf_free_keep_EM();
1033
1034 // allocate buffers:
1035 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1036 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1037 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1038
1039 // clear trace
1040 clear_trace();
1041 set_tracing(TRUE);
1042
1043 // Prepare the responses of the anticollision phase
1044 // there will be not enough time to do this at the moment the reader sends it REQA
1045 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1046 prepare_allocated_tag_modulation(&responses[i]);
1047 }
1048
1049 int len = 0;
1050
1051 // To control where we are in the protocol
1052 int order = 0;
1053 int lastorder;
1054
1055 // Just to allow some checks
1056 int happened = 0;
1057 int happened2 = 0;
1058 int cmdsRecvd = 0;
1059
1060 cmdsRecvd = 0;
1061 tag_response_info_t* p_response;
1062
1063 LED_A_ON();
1064 for(;;) {
1065 // Clean receive command buffer
1066 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1067 DbpString("Button press");
1068 break;
1069 }
1070
1071 p_response = NULL;
1072
1073 // Okay, look at the command now.
1074 lastorder = order;
1075 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1076 p_response = &responses[0]; order = 1;
1077 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1078 p_response = &responses[0]; order = 6;
1079 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1080 p_response = &responses[1]; order = 2;
1081 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1082 p_response = &responses[2]; order = 20;
1083 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1084 p_response = &responses[3]; order = 3;
1085 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1086 p_response = &responses[4]; order = 30;
1087 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1088 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1089 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1090 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1091 p_response = NULL;
1092 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1093
1094 if (tracing) {
1095 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1096 }
1097 p_response = NULL;
1098 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1099 p_response = &responses[5]; order = 7;
1100 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1101 if (tagType == 1 || tagType == 2) { // RATS not supported
1102 EmSend4bit(CARD_NACK_NA);
1103 p_response = NULL;
1104 } else {
1105 p_response = &responses[6]; order = 70;
1106 }
1107 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1108 if (tracing) {
1109 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1110 }
1111 uint32_t nr = bytes_to_num(receivedCmd,4);
1112 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1113 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1114 } else {
1115 // Check for ISO 14443A-4 compliant commands, look at left nibble
1116 switch (receivedCmd[0]) {
1117
1118 case 0x0B:
1119 case 0x0A: { // IBlock (command)
1120 dynamic_response_info.response[0] = receivedCmd[0];
1121 dynamic_response_info.response[1] = 0x00;
1122 dynamic_response_info.response[2] = 0x90;
1123 dynamic_response_info.response[3] = 0x00;
1124 dynamic_response_info.response_n = 4;
1125 } break;
1126
1127 case 0x1A:
1128 case 0x1B: { // Chaining command
1129 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1130 dynamic_response_info.response_n = 2;
1131 } break;
1132
1133 case 0xaa:
1134 case 0xbb: {
1135 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1136 dynamic_response_info.response_n = 2;
1137 } break;
1138
1139 case 0xBA: { //
1140 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1141 dynamic_response_info.response_n = 2;
1142 } break;
1143
1144 case 0xCA:
1145 case 0xC2: { // Readers sends deselect command
1146 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1147 dynamic_response_info.response_n = 2;
1148 } break;
1149
1150 default: {
1151 // Never seen this command before
1152 if (tracing) {
1153 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1154 }
1155 Dbprintf("Received unknown command (len=%d):",len);
1156 Dbhexdump(len,receivedCmd,false);
1157 // Do not respond
1158 dynamic_response_info.response_n = 0;
1159 } break;
1160 }
1161
1162 if (dynamic_response_info.response_n > 0) {
1163 // Copy the CID from the reader query
1164 dynamic_response_info.response[1] = receivedCmd[1];
1165
1166 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1167 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1168 dynamic_response_info.response_n += 2;
1169
1170 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1171 Dbprintf("Error preparing tag response");
1172 if (tracing) {
1173 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1174 }
1175 break;
1176 }
1177 p_response = &dynamic_response_info;
1178 }
1179 }
1180
1181 // Count number of wakeups received after a halt
1182 if(order == 6 && lastorder == 5) { happened++; }
1183
1184 // Count number of other messages after a halt
1185 if(order != 6 && lastorder == 5) { happened2++; }
1186
1187 if(cmdsRecvd > 999) {
1188 DbpString("1000 commands later...");
1189 break;
1190 }
1191 cmdsRecvd++;
1192
1193 if (p_response != NULL) {
1194 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1195 // do the tracing for the previous reader request and this tag answer:
1196 uint8_t par[MAX_PARITY_SIZE];
1197 GetParity(p_response->response, p_response->response_n, par);
1198
1199 EmLogTrace(Uart.output,
1200 Uart.len,
1201 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1202 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1203 Uart.parity,
1204 p_response->response,
1205 p_response->response_n,
1206 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1207 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1208 par);
1209 }
1210
1211 if (!tracing) {
1212 Dbprintf("Trace Full. Simulation stopped.");
1213 break;
1214 }
1215 }
1216
1217 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1218 LED_A_OFF();
1219 BigBuf_free_keep_EM();
1220 }
1221
1222
1223 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1224 // of bits specified in the delay parameter.
1225 void PrepareDelayedTransfer(uint16_t delay)
1226 {
1227 uint8_t bitmask = 0;
1228 uint8_t bits_to_shift = 0;
1229 uint8_t bits_shifted = 0;
1230
1231 delay &= 0x07;
1232 if (delay) {
1233 for (uint16_t i = 0; i < delay; i++) {
1234 bitmask |= (0x01 << i);
1235 }
1236 ToSend[ToSendMax++] = 0x00;
1237 for (uint16_t i = 0; i < ToSendMax; i++) {
1238 bits_to_shift = ToSend[i] & bitmask;
1239 ToSend[i] = ToSend[i] >> delay;
1240 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1241 bits_shifted = bits_to_shift;
1242 }
1243 }
1244 }
1245
1246
1247 //-------------------------------------------------------------------------------------
1248 // Transmit the command (to the tag) that was placed in ToSend[].
1249 // Parameter timing:
1250 // if NULL: transfer at next possible time, taking into account
1251 // request guard time and frame delay time
1252 // if == 0: transfer immediately and return time of transfer
1253 // if != 0: delay transfer until time specified
1254 //-------------------------------------------------------------------------------------
1255 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1256 {
1257
1258 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1259
1260 uint32_t ThisTransferTime = 0;
1261
1262 if (timing) {
1263 if(*timing == 0) { // Measure time
1264 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1265 } else {
1266 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1267 }
1268 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1269 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1270 LastTimeProxToAirStart = *timing;
1271 } else {
1272 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1273 while(GetCountSspClk() < ThisTransferTime);
1274 LastTimeProxToAirStart = ThisTransferTime;
1275 }
1276
1277 // clear TXRDY
1278 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1279
1280 uint16_t c = 0;
1281 for(;;) {
1282 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1283 AT91C_BASE_SSC->SSC_THR = cmd[c];
1284 c++;
1285 if(c >= len) {
1286 break;
1287 }
1288 }
1289 }
1290
1291 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1292 }
1293
1294
1295 //-----------------------------------------------------------------------------
1296 // Prepare reader command (in bits, support short frames) to send to FPGA
1297 //-----------------------------------------------------------------------------
1298 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1299 {
1300 int i, j;
1301 int last;
1302 uint8_t b;
1303
1304 ToSendReset();
1305
1306 // Start of Communication (Seq. Z)
1307 ToSend[++ToSendMax] = SEC_Z;
1308 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1309 last = 0;
1310
1311 size_t bytecount = nbytes(bits);
1312 // Generate send structure for the data bits
1313 for (i = 0; i < bytecount; i++) {
1314 // Get the current byte to send
1315 b = cmd[i];
1316 size_t bitsleft = MIN((bits-(i*8)),8);
1317
1318 for (j = 0; j < bitsleft; j++) {
1319 if (b & 1) {
1320 // Sequence X
1321 ToSend[++ToSendMax] = SEC_X;
1322 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1323 last = 1;
1324 } else {
1325 if (last == 0) {
1326 // Sequence Z
1327 ToSend[++ToSendMax] = SEC_Z;
1328 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1329 } else {
1330 // Sequence Y
1331 ToSend[++ToSendMax] = SEC_Y;
1332 last = 0;
1333 }
1334 }
1335 b >>= 1;
1336 }
1337
1338 // Only transmit parity bit if we transmitted a complete byte
1339 if (j == 8) {
1340 // Get the parity bit
1341 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1342 // Sequence X
1343 ToSend[++ToSendMax] = SEC_X;
1344 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1345 last = 1;
1346 } else {
1347 if (last == 0) {
1348 // Sequence Z
1349 ToSend[++ToSendMax] = SEC_Z;
1350 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1351 } else {
1352 // Sequence Y
1353 ToSend[++ToSendMax] = SEC_Y;
1354 last = 0;
1355 }
1356 }
1357 }
1358 }
1359
1360 // End of Communication: Logic 0 followed by Sequence Y
1361 if (last == 0) {
1362 // Sequence Z
1363 ToSend[++ToSendMax] = SEC_Z;
1364 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1365 } else {
1366 // Sequence Y
1367 ToSend[++ToSendMax] = SEC_Y;
1368 last = 0;
1369 }
1370 ToSend[++ToSendMax] = SEC_Y;
1371
1372 // Convert to length of command:
1373 ToSendMax++;
1374 }
1375
1376 //-----------------------------------------------------------------------------
1377 // Prepare reader command to send to FPGA
1378 //-----------------------------------------------------------------------------
1379 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1380 {
1381 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1382 }
1383
1384
1385 //-----------------------------------------------------------------------------
1386 // Wait for commands from reader
1387 // Stop when button is pressed (return 1) or field was gone (return 2)
1388 // Or return 0 when command is captured
1389 //-----------------------------------------------------------------------------
1390 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1391 {
1392 *len = 0;
1393
1394 uint32_t timer = 0, vtime = 0;
1395 int analogCnt = 0;
1396 int analogAVG = 0;
1397
1398 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1399 // only, since we are receiving, not transmitting).
1400 // Signal field is off with the appropriate LED
1401 LED_D_OFF();
1402 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1403
1404 // Set ADC to read field strength
1405 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1406 AT91C_BASE_ADC->ADC_MR =
1407 ADC_MODE_PRESCALE(63) |
1408 ADC_MODE_STARTUP_TIME(1) |
1409 ADC_MODE_SAMPLE_HOLD_TIME(15);
1410 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1411 // start ADC
1412 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1413
1414 // Now run a 'software UART' on the stream of incoming samples.
1415 UartInit(received, parity);
1416
1417 // Clear RXRDY:
1418 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1419
1420 for(;;) {
1421 WDT_HIT();
1422
1423 if (BUTTON_PRESS()) return 1;
1424
1425 // test if the field exists
1426 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1427 analogCnt++;
1428 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1429 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1430 if (analogCnt >= 32) {
1431 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1432 vtime = GetTickCount();
1433 if (!timer) timer = vtime;
1434 // 50ms no field --> card to idle state
1435 if (vtime - timer > 50) return 2;
1436 } else
1437 if (timer) timer = 0;
1438 analogCnt = 0;
1439 analogAVG = 0;
1440 }
1441 }
1442
1443 // receive and test the miller decoding
1444 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1445 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1446 if(MillerDecoding(b, 0)) {
1447 *len = Uart.len;
1448 return 0;
1449 }
1450 }
1451
1452 }
1453 }
1454
1455
1456 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1457 {
1458 uint8_t b;
1459 uint16_t i = 0;
1460 uint32_t ThisTransferTime;
1461
1462 // Modulate Manchester
1463 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1464
1465 // include correction bit if necessary
1466 if (Uart.parityBits & 0x01) {
1467 correctionNeeded = TRUE;
1468 }
1469 if(correctionNeeded) {
1470 // 1236, so correction bit needed
1471 i = 0;
1472 } else {
1473 i = 1;
1474 }
1475
1476 // clear receiving shift register and holding register
1477 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1478 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1479 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1480 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1481
1482 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1483 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1484 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1485 if (AT91C_BASE_SSC->SSC_RHR) break;
1486 }
1487
1488 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1489
1490 // Clear TXRDY:
1491 AT91C_BASE_SSC->SSC_THR = SEC_F;
1492
1493 // send cycle
1494 for(; i < respLen; ) {
1495 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1496 AT91C_BASE_SSC->SSC_THR = resp[i++];
1497 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1498 }
1499
1500 if(BUTTON_PRESS()) {
1501 break;
1502 }
1503 }
1504
1505 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1506 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1507 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1508 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1509 AT91C_BASE_SSC->SSC_THR = SEC_F;
1510 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1511 i++;
1512 }
1513 }
1514
1515 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1516
1517 return 0;
1518 }
1519
1520 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1521 Code4bitAnswerAsTag(resp);
1522 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1523 // do the tracing for the previous reader request and this tag answer:
1524 uint8_t par[1];
1525 GetParity(&resp, 1, par);
1526 EmLogTrace(Uart.output,
1527 Uart.len,
1528 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1529 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1530 Uart.parity,
1531 &resp,
1532 1,
1533 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1534 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1535 par);
1536 return res;
1537 }
1538
1539 int EmSend4bit(uint8_t resp){
1540 return EmSend4bitEx(resp, false);
1541 }
1542
1543 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1544 CodeIso14443aAsTagPar(resp, respLen, par);
1545 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1546 // do the tracing for the previous reader request and this tag answer:
1547 EmLogTrace(Uart.output,
1548 Uart.len,
1549 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1550 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1551 Uart.parity,
1552 resp,
1553 respLen,
1554 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1555 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1556 par);
1557 return res;
1558 }
1559
1560 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1561 uint8_t par[MAX_PARITY_SIZE];
1562 GetParity(resp, respLen, par);
1563 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1564 }
1565
1566 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1567 uint8_t par[MAX_PARITY_SIZE];
1568 GetParity(resp, respLen, par);
1569 return EmSendCmdExPar(resp, respLen, false, par);
1570 }
1571
1572 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1573 return EmSendCmdExPar(resp, respLen, false, par);
1574 }
1575
1576 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1577 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1578 {
1579 if (tracing) {
1580 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1581 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1582 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1583 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1584 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1585 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1586 reader_EndTime = tag_StartTime - exact_fdt;
1587 reader_StartTime = reader_EndTime - reader_modlen;
1588 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1589 return FALSE;
1590 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1591 } else {
1592 return TRUE;
1593 }
1594 }
1595
1596 //-----------------------------------------------------------------------------
1597 // Wait a certain time for tag response
1598 // If a response is captured return TRUE
1599 // If it takes too long return FALSE
1600 //-----------------------------------------------------------------------------
1601 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1602 {
1603 uint32_t c;
1604
1605 // Set FPGA mode to "reader listen mode", no modulation (listen
1606 // only, since we are receiving, not transmitting).
1607 // Signal field is on with the appropriate LED
1608 LED_D_ON();
1609 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1610
1611 // Now get the answer from the card
1612 DemodInit(receivedResponse, receivedResponsePar);
1613
1614 // clear RXRDY:
1615 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1616
1617 c = 0;
1618 for(;;) {
1619 WDT_HIT();
1620
1621 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1622 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1623 if(ManchesterDecoding(b, offset, 0)) {
1624 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1625 return TRUE;
1626 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1627 return FALSE;
1628 }
1629 }
1630 }
1631 }
1632
1633 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1634 {
1635 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1636
1637 // Send command to tag
1638 TransmitFor14443a(ToSend, ToSendMax, timing);
1639 if(trigger)
1640 LED_A_ON();
1641
1642 // Log reader command in trace buffer
1643 if (tracing) {
1644 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1645 }
1646 }
1647
1648 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1649 {
1650 ReaderTransmitBitsPar(frame, len*8, par, timing);
1651 }
1652
1653 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1654 {
1655 // Generate parity and redirect
1656 uint8_t par[MAX_PARITY_SIZE];
1657 GetParity(frame, len/8, par);
1658 ReaderTransmitBitsPar(frame, len, par, timing);
1659 }
1660
1661 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1662 {
1663 // Generate parity and redirect
1664 uint8_t par[MAX_PARITY_SIZE];
1665 GetParity(frame, len, par);
1666 ReaderTransmitBitsPar(frame, len*8, par, timing);
1667 }
1668
1669 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1670 {
1671 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1672 if (tracing) {
1673 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1674 }
1675 return Demod.len;
1676 }
1677
1678 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1679 {
1680 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1681 if (tracing) {
1682 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1683 }
1684 return Demod.len;
1685 }
1686
1687 /* performs iso14443a anticollision procedure
1688 * fills the uid pointer unless NULL
1689 * fills resp_data unless NULL */
1690 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1691 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1692 uint8_t sel_all[] = { 0x93,0x20 };
1693 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1694 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1695 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1696 uint8_t resp_par[MAX_PARITY_SIZE];
1697 byte_t uid_resp[4];
1698 size_t uid_resp_len;
1699
1700 uint8_t sak = 0x04; // cascade uid
1701 int cascade_level = 0;
1702 int len;
1703
1704 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1705 ReaderTransmitBitsPar(wupa,7,0, NULL);
1706
1707 // Receive the ATQA
1708 if(!ReaderReceive(resp, resp_par)) return 0;
1709
1710 if(p_hi14a_card) {
1711 memcpy(p_hi14a_card->atqa, resp, 2);
1712 p_hi14a_card->uidlen = 0;
1713 memset(p_hi14a_card->uid,0,10);
1714 }
1715
1716 // clear uid
1717 if (uid_ptr) {
1718 memset(uid_ptr,0,10);
1719 }
1720
1721 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1722 // which case we need to make a cascade 2 request and select - this is a long UID
1723 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1724 for(; sak & 0x04; cascade_level++) {
1725 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1726 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1727
1728 // SELECT_ALL
1729 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1730 if (!ReaderReceive(resp, resp_par)) return 0;
1731
1732 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1733 memset(uid_resp, 0, 4);
1734 uint16_t uid_resp_bits = 0;
1735 uint16_t collision_answer_offset = 0;
1736 // anti-collision-loop:
1737 while (Demod.collisionPos) {
1738 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1739 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1740 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1741 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1742 }
1743 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1744 uid_resp_bits++;
1745 // construct anticollosion command:
1746 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1747 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1748 sel_uid[2+i] = uid_resp[i];
1749 }
1750 collision_answer_offset = uid_resp_bits%8;
1751 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1752 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1753 }
1754 // finally, add the last bits and BCC of the UID
1755 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1756 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1757 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1758 }
1759
1760 } else { // no collision, use the response to SELECT_ALL as current uid
1761 memcpy(uid_resp, resp, 4);
1762 }
1763 uid_resp_len = 4;
1764
1765 // calculate crypto UID. Always use last 4 Bytes.
1766 if(cuid_ptr) {
1767 *cuid_ptr = bytes_to_num(uid_resp, 4);
1768 }
1769
1770 // Construct SELECT UID command
1771 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1772 memcpy(sel_uid+2, uid_resp, 4); // the UID
1773 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1774 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1775 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1776
1777 // Receive the SAK
1778 if (!ReaderReceive(resp, resp_par)) return 0;
1779 sak = resp[0];
1780
1781 // Test if more parts of the uid are coming
1782 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1783 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1784 // http://www.nxp.com/documents/application_note/AN10927.pdf
1785 uid_resp[0] = uid_resp[1];
1786 uid_resp[1] = uid_resp[2];
1787 uid_resp[2] = uid_resp[3];
1788
1789 uid_resp_len = 3;
1790 }
1791
1792 if(uid_ptr) {
1793 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1794 }
1795
1796 if(p_hi14a_card) {
1797 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1798 p_hi14a_card->uidlen += uid_resp_len;
1799 }
1800 }
1801
1802 if(p_hi14a_card) {
1803 p_hi14a_card->sak = sak;
1804 p_hi14a_card->ats_len = 0;
1805 }
1806
1807 // non iso14443a compliant tag
1808 if( (sak & 0x20) == 0) return 2;
1809
1810 // Request for answer to select
1811 AppendCrc14443a(rats, 2);
1812 ReaderTransmit(rats, sizeof(rats), NULL);
1813
1814 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1815
1816
1817 if(p_hi14a_card) {
1818 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1819 p_hi14a_card->ats_len = len;
1820 }
1821
1822 // reset the PCB block number
1823 iso14_pcb_blocknum = 0;
1824
1825 // set default timeout based on ATS
1826 iso14a_set_ATS_timeout(resp);
1827
1828 return 1;
1829 }
1830
1831 void iso14443a_setup(uint8_t fpga_minor_mode) {
1832 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1833 // Set up the synchronous serial port
1834 FpgaSetupSsc();
1835 // connect Demodulated Signal to ADC:
1836 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1837
1838 // Signal field is on with the appropriate LED
1839 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1840 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1841 LED_D_ON();
1842 } else {
1843 LED_D_OFF();
1844 }
1845 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1846
1847 // Start the timer
1848 StartCountSspClk();
1849
1850 DemodReset();
1851 UartReset();
1852 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1853 iso14a_set_timeout(1050); // 10ms default
1854 }
1855
1856 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1857 uint8_t parity[MAX_PARITY_SIZE];
1858 uint8_t real_cmd[cmd_len+4];
1859 real_cmd[0] = 0x0a; //I-Block
1860 // put block number into the PCB
1861 real_cmd[0] |= iso14_pcb_blocknum;
1862 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1863 memcpy(real_cmd+2, cmd, cmd_len);
1864 AppendCrc14443a(real_cmd,cmd_len+2);
1865
1866 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1867 size_t len = ReaderReceive(data, parity);
1868 uint8_t *data_bytes = (uint8_t *) data;
1869 if (!len)
1870 return 0; //DATA LINK ERROR
1871 // if we received an I- or R(ACK)-Block with a block number equal to the
1872 // current block number, toggle the current block number
1873 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1874 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1875 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1876 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1877 {
1878 iso14_pcb_blocknum ^= 1;
1879 }
1880
1881 return len;
1882 }
1883
1884 //-----------------------------------------------------------------------------
1885 // Read an ISO 14443a tag. Send out commands and store answers.
1886 //
1887 //-----------------------------------------------------------------------------
1888 void ReaderIso14443a(UsbCommand *c)
1889 {
1890 iso14a_command_t param = c->arg[0];
1891 uint8_t *cmd = c->d.asBytes;
1892 size_t len = c->arg[1] & 0xffff;
1893 size_t lenbits = c->arg[1] >> 16;
1894 uint32_t timeout = c->arg[2];
1895 uint32_t arg0 = 0;
1896 byte_t buf[USB_CMD_DATA_SIZE];
1897 uint8_t par[MAX_PARITY_SIZE];
1898
1899 if(param & ISO14A_CONNECT) {
1900 clear_trace();
1901 }
1902
1903 set_tracing(TRUE);
1904
1905 if(param & ISO14A_REQUEST_TRIGGER) {
1906 iso14a_set_trigger(TRUE);
1907 }
1908
1909 if(param & ISO14A_CONNECT) {
1910 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1911 if(!(param & ISO14A_NO_SELECT)) {
1912 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1913 arg0 = iso14443a_select_card(NULL,card,NULL);
1914 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1915 }
1916 }
1917
1918 if(param & ISO14A_SET_TIMEOUT) {
1919 iso14a_set_timeout(timeout);
1920 }
1921
1922 if(param & ISO14A_APDU) {
1923 arg0 = iso14_apdu(cmd, len, buf);
1924 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1925 }
1926
1927 if(param & ISO14A_RAW) {
1928 if(param & ISO14A_APPEND_CRC) {
1929 AppendCrc14443a(cmd,len);
1930 len += 2;
1931 if (lenbits) lenbits += 16;
1932 }
1933 if(lenbits>0) {
1934 GetParity(cmd, lenbits/8, par);
1935 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
1936 } else {
1937 ReaderTransmit(cmd,len, NULL);
1938 }
1939 arg0 = ReaderReceive(buf, par);
1940 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1941 }
1942
1943 if(param & ISO14A_REQUEST_TRIGGER) {
1944 iso14a_set_trigger(FALSE);
1945 }
1946
1947 if(param & ISO14A_NO_DISCONNECT) {
1948 return;
1949 }
1950
1951 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1952 LEDsoff();
1953 }
1954
1955
1956 // Determine the distance between two nonces.
1957 // Assume that the difference is small, but we don't know which is first.
1958 // Therefore try in alternating directions.
1959 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1960
1961 uint16_t i;
1962 uint32_t nttmp1, nttmp2;
1963
1964 if (nt1 == nt2) return 0;
1965
1966 nttmp1 = nt1;
1967 nttmp2 = nt2;
1968
1969 for (i = 1; i < 32768; i++) {
1970 nttmp1 = prng_successor(nttmp1, 1);
1971 if (nttmp1 == nt2) return i;
1972 nttmp2 = prng_successor(nttmp2, 1);
1973 if (nttmp2 == nt1) return -i;
1974 }
1975
1976 return(-99999); // either nt1 or nt2 are invalid nonces
1977 }
1978
1979
1980 //-----------------------------------------------------------------------------
1981 // Recover several bits of the cypher stream. This implements (first stages of)
1982 // the algorithm described in "The Dark Side of Security by Obscurity and
1983 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
1984 // (article by Nicolas T. Courtois, 2009)
1985 //-----------------------------------------------------------------------------
1986 void ReaderMifare(bool first_try)
1987 {
1988 // Mifare AUTH
1989 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
1990 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
1991 static uint8_t mf_nr_ar3;
1992
1993 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
1994 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
1995
1996 if (first_try) {
1997 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
1998 }
1999
2000 // free eventually allocated BigBuf memory. We want all for tracing.
2001 BigBuf_free();
2002
2003 clear_trace();
2004 set_tracing(TRUE);
2005
2006 byte_t nt_diff = 0;
2007 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2008 static byte_t par_low = 0;
2009 bool led_on = TRUE;
2010 uint8_t uid[10] ={0};
2011 uint32_t cuid;
2012
2013 uint32_t nt = 0;
2014 uint32_t previous_nt = 0;
2015 static uint32_t nt_attacked = 0;
2016 byte_t par_list[8] = {0x00};
2017 byte_t ks_list[8] = {0x00};
2018
2019 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2020 static uint32_t sync_time;
2021 static int32_t sync_cycles;
2022 int catch_up_cycles = 0;
2023 int last_catch_up = 0;
2024 uint16_t elapsed_prng_sequences;
2025 uint16_t consecutive_resyncs = 0;
2026 int isOK = 0;
2027
2028 if (first_try) {
2029 mf_nr_ar3 = 0;
2030 sync_time = GetCountSspClk() & 0xfffffff8;
2031 sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2032 nt_attacked = 0;
2033 par[0] = 0;
2034 }
2035 else {
2036 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2037 mf_nr_ar3++;
2038 mf_nr_ar[3] = mf_nr_ar3;
2039 par[0] = par_low;
2040 }
2041
2042 LED_A_ON();
2043 LED_B_OFF();
2044 LED_C_OFF();
2045
2046
2047 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2048 #define MAX_SYNC_TRIES 32
2049 #define NUM_DEBUG_INFOS 8 // per strategy
2050 #define MAX_STRATEGY 3
2051 uint16_t unexpected_random = 0;
2052 uint16_t sync_tries = 0;
2053 int16_t debug_info_nr = -1;
2054 uint16_t strategy = 0;
2055 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
2056 uint32_t select_time;
2057 uint32_t halt_time;
2058
2059 for(uint16_t i = 0; TRUE; i++) {
2060
2061 LED_C_ON();
2062 WDT_HIT();
2063
2064 // Test if the action was cancelled
2065 if(BUTTON_PRESS()) {
2066 isOK = -1;
2067 break;
2068 }
2069
2070 if (strategy == 2) {
2071 // test with additional hlt command
2072 halt_time = 0;
2073 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2074 if (len && MF_DBGLEVEL >= 3) {
2075 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2076 }
2077 }
2078
2079 if (strategy == 3) {
2080 // test with FPGA power off/on
2081 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2082 SpinDelay(200);
2083 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2084 SpinDelay(100);
2085 }
2086
2087 if(!iso14443a_select_card(uid, NULL, &cuid)) {
2088 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2089 continue;
2090 }
2091 select_time = GetCountSspClk();
2092
2093 elapsed_prng_sequences = 1;
2094 if (debug_info_nr == -1) {
2095 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2096 catch_up_cycles = 0;
2097
2098 // if we missed the sync time already, advance to the next nonce repeat
2099 while(GetCountSspClk() > sync_time) {
2100 elapsed_prng_sequences++;
2101 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2102 }
2103
2104 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2105 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2106 } else {
2107 // collect some information on tag nonces for debugging:
2108 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2109 if (strategy == 0) {
2110 // nonce distances at fixed time after card select:
2111 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2112 } else if (strategy == 1) {
2113 // nonce distances at fixed time between authentications:
2114 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2115 } else if (strategy == 2) {
2116 // nonce distances at fixed time after halt:
2117 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2118 } else {
2119 // nonce_distances at fixed time after power on
2120 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2121 }
2122 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2123 }
2124
2125 // Receive the (4 Byte) "random" nonce
2126 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2127 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2128 continue;
2129 }
2130
2131 previous_nt = nt;
2132 nt = bytes_to_num(receivedAnswer, 4);
2133
2134 // Transmit reader nonce with fake par
2135 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2136
2137 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2138 int nt_distance = dist_nt(previous_nt, nt);
2139 if (nt_distance == 0) {
2140 nt_attacked = nt;
2141 } else {
2142 if (nt_distance == -99999) { // invalid nonce received
2143 unexpected_random++;
2144 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
2145 isOK = -3; // Card has an unpredictable PRNG. Give up
2146 break;
2147 } else {
2148 continue; // continue trying...
2149 }
2150 }
2151 if (++sync_tries > MAX_SYNC_TRIES) {
2152 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
2153 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2154 break;
2155 } else { // continue for a while, just to collect some debug info
2156 debug_info[strategy][debug_info_nr] = nt_distance;
2157 debug_info_nr++;
2158 if (debug_info_nr == NUM_DEBUG_INFOS) {
2159 strategy++;
2160 debug_info_nr = 0;
2161 }
2162 continue;
2163 }
2164 }
2165 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
2166 if (sync_cycles <= 0) {
2167 sync_cycles += PRNG_SEQUENCE_LENGTH;
2168 }
2169 if (MF_DBGLEVEL >= 3) {
2170 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
2171 }
2172 continue;
2173 }
2174 }
2175
2176 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2177 catch_up_cycles = -dist_nt(nt_attacked, nt);
2178 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2179 catch_up_cycles = 0;
2180 continue;
2181 }
2182 catch_up_cycles /= elapsed_prng_sequences;
2183 if (catch_up_cycles == last_catch_up) {
2184 consecutive_resyncs++;
2185 }
2186 else {
2187 last_catch_up = catch_up_cycles;
2188 consecutive_resyncs = 0;
2189 }
2190 if (consecutive_resyncs < 3) {
2191 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2192 }
2193 else {
2194 sync_cycles = sync_cycles + catch_up_cycles;
2195 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2196 last_catch_up = 0;
2197 catch_up_cycles = 0;
2198 consecutive_resyncs = 0;
2199 }
2200 continue;
2201 }
2202
2203 consecutive_resyncs = 0;
2204
2205 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2206 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2207 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2208
2209 if (nt_diff == 0) {
2210 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2211 }
2212
2213 led_on = !led_on;
2214 if(led_on) LED_B_ON(); else LED_B_OFF();
2215
2216 par_list[nt_diff] = SwapBits(par[0], 8);
2217 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2218
2219 // Test if the information is complete
2220 if (nt_diff == 0x07) {
2221 isOK = 1;
2222 break;
2223 }
2224
2225 nt_diff = (nt_diff + 1) & 0x07;
2226 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2227 par[0] = par_low;
2228 } else {
2229 if (nt_diff == 0 && first_try)
2230 {
2231 par[0]++;
2232 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2233 isOK = -2;
2234 break;
2235 }
2236 } else {
2237 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2238 }
2239 }
2240 }
2241
2242
2243 mf_nr_ar[3] &= 0x1F;
2244
2245 if (isOK == -4) {
2246 if (MF_DBGLEVEL >= 3) {
2247 for (uint16_t i = 0; i <= MAX_STRATEGY; i++) {
2248 for(uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) {
2249 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2250 }
2251 }
2252 }
2253 }
2254
2255 byte_t buf[28];
2256 memcpy(buf + 0, uid, 4);
2257 num_to_bytes(nt, 4, buf + 4);
2258 memcpy(buf + 8, par_list, 8);
2259 memcpy(buf + 16, ks_list, 8);
2260 memcpy(buf + 24, mf_nr_ar, 4);
2261
2262 cmd_send(CMD_ACK, isOK, 0, 0, buf, 28);
2263
2264 // Thats it...
2265 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2266 LEDsoff();
2267
2268 set_tracing(FALSE);
2269 }
2270
2271 /**
2272 *MIFARE 1K simulate.
2273 *
2274 *@param flags :
2275 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2276 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2277 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2278 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2279 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2280 */
2281 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2282 {
2283 int cardSTATE = MFEMUL_NOFIELD;
2284 int _7BUID = 0;
2285 int vHf = 0; // in mV
2286 int res;
2287 uint32_t selTimer = 0;
2288 uint32_t authTimer = 0;
2289 uint16_t len = 0;
2290 uint8_t cardWRBL = 0;
2291 uint8_t cardAUTHSC = 0;
2292 uint8_t cardAUTHKEY = 0xff; // no authentication
2293 uint32_t cardRr = 0;
2294 uint32_t cuid = 0;
2295 //uint32_t rn_enc = 0;
2296 uint32_t ans = 0;
2297 uint32_t cardINTREG = 0;
2298 uint8_t cardINTBLOCK = 0;
2299 struct Crypto1State mpcs = {0, 0};
2300 struct Crypto1State *pcs;
2301 pcs = &mpcs;
2302 uint32_t numReads = 0;//Counts numer of times reader read a block
2303 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2304 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2305 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2306 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
2307
2308 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2309 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2310 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2311 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2312 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2313
2314 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2315 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2316
2317 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2318 // This can be used in a reader-only attack.
2319 // (it can also be retrieved via 'hf 14a list', but hey...
2320 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2321 uint8_t ar_nr_collected = 0;
2322
2323 // Authenticate response - nonce
2324 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2325
2326 //-- Determine the UID
2327 // Can be set from emulator memory, incoming data
2328 // and can be 7 or 4 bytes long
2329 if (flags & FLAG_4B_UID_IN_DATA)
2330 {
2331 // 4B uid comes from data-portion of packet
2332 memcpy(rUIDBCC1,datain,4);
2333 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2334
2335 } else if (flags & FLAG_7B_UID_IN_DATA) {
2336 // 7B uid comes from data-portion of packet
2337 memcpy(&rUIDBCC1[1],datain,3);
2338 memcpy(rUIDBCC2, datain+3, 4);
2339 _7BUID = true;
2340 } else {
2341 // get UID from emul memory
2342 emlGetMemBt(receivedCmd, 7, 1);
2343 _7BUID = !(receivedCmd[0] == 0x00);
2344 if (!_7BUID) { // ---------- 4BUID
2345 emlGetMemBt(rUIDBCC1, 0, 4);
2346 } else { // ---------- 7BUID
2347 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2348 emlGetMemBt(rUIDBCC2, 3, 4);
2349 }
2350 }
2351
2352 /*
2353 * Regardless of what method was used to set the UID, set fifth byte and modify
2354 * the ATQA for 4 or 7-byte UID
2355 */
2356 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2357 if (_7BUID) {
2358 rATQA[0] = 0x44;
2359 rUIDBCC1[0] = 0x88;
2360 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2361 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2362 }
2363
2364 if (MF_DBGLEVEL >= 1) {
2365 if (!_7BUID) {
2366 Dbprintf("4B UID: %02x%02x%02x%02x",
2367 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2368 } else {
2369 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2370 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2371 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2372 }
2373 }
2374
2375 // We need to listen to the high-frequency, peak-detected path.
2376 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2377
2378 // free eventually allocated BigBuf memory but keep Emulator Memory
2379 BigBuf_free_keep_EM();
2380
2381 // clear trace
2382 clear_trace();
2383 set_tracing(TRUE);
2384
2385
2386 bool finished = FALSE;
2387 while (!BUTTON_PRESS() && !finished) {
2388 WDT_HIT();
2389
2390 // find reader field
2391 if (cardSTATE == MFEMUL_NOFIELD) {
2392 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2393 if (vHf > MF_MINFIELDV) {
2394 cardSTATE_TO_IDLE();
2395 LED_A_ON();
2396 }
2397 }
2398 if(cardSTATE == MFEMUL_NOFIELD) continue;
2399
2400 //Now, get data
2401
2402 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2403 if (res == 2) { //Field is off!
2404 cardSTATE = MFEMUL_NOFIELD;
2405 LEDsoff();
2406 continue;
2407 } else if (res == 1) {
2408 break; //return value 1 means button press
2409 }
2410
2411 // REQ or WUP request in ANY state and WUP in HALTED state
2412 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2413 selTimer = GetTickCount();
2414 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2415 cardSTATE = MFEMUL_SELECT1;
2416
2417 // init crypto block
2418 LED_B_OFF();
2419 LED_C_OFF();
2420 crypto1_destroy(pcs);
2421 cardAUTHKEY = 0xff;
2422 continue;
2423 }
2424
2425 switch (cardSTATE) {
2426 case MFEMUL_NOFIELD:
2427 case MFEMUL_HALTED:
2428 case MFEMUL_IDLE:{
2429 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2430 break;
2431 }
2432 case MFEMUL_SELECT1:{
2433 // select all
2434 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2435 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2436 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2437 break;
2438 }
2439
2440 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2441 {
2442 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2443 }
2444 // select card
2445 if (len == 9 &&
2446 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2447 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2448 cuid = bytes_to_num(rUIDBCC1, 4);
2449 if (!_7BUID) {
2450 cardSTATE = MFEMUL_WORK;
2451 LED_B_ON();
2452 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2453 break;
2454 } else {
2455 cardSTATE = MFEMUL_SELECT2;
2456 }
2457 }
2458 break;
2459 }
2460 case MFEMUL_AUTH1:{
2461 if( len != 8)
2462 {
2463 cardSTATE_TO_IDLE();
2464 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2465 break;
2466 }
2467
2468 uint32_t ar = bytes_to_num(receivedCmd, 4);
2469 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2470
2471 //Collect AR/NR
2472 if(ar_nr_collected < 2){
2473 if(ar_nr_responses[2] != ar)
2474 {// Avoid duplicates... probably not necessary, ar should vary.
2475 ar_nr_responses[ar_nr_collected*4] = cuid;
2476 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2477 ar_nr_responses[ar_nr_collected*4+2] = ar;
2478 ar_nr_responses[ar_nr_collected*4+3] = nr;
2479 ar_nr_collected++;
2480 }
2481 }
2482
2483 // --- crypto
2484 crypto1_word(pcs, ar , 1);
2485 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2486
2487 // test if auth OK
2488 if (cardRr != prng_successor(nonce, 64)){
2489 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2490 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2491 cardRr, prng_successor(nonce, 64));
2492 // Shouldn't we respond anything here?
2493 // Right now, we don't nack or anything, which causes the
2494 // reader to do a WUPA after a while. /Martin
2495 // -- which is the correct response. /piwi
2496 cardSTATE_TO_IDLE();
2497 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2498 break;
2499 }
2500
2501 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2502
2503 num_to_bytes(ans, 4, rAUTH_AT);
2504 // --- crypto
2505 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2506 LED_C_ON();
2507 cardSTATE = MFEMUL_WORK;
2508 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2509 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2510 GetTickCount() - authTimer);
2511 break;
2512 }
2513 case MFEMUL_SELECT2:{
2514 if (!len) {
2515 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2516 break;
2517 }
2518 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2519 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2520 break;
2521 }
2522
2523 // select 2 card
2524 if (len == 9 &&
2525 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2526 EmSendCmd(rSAK, sizeof(rSAK));
2527 cuid = bytes_to_num(rUIDBCC2, 4);
2528 cardSTATE = MFEMUL_WORK;
2529 LED_B_ON();
2530 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2531 break;
2532 }
2533
2534 // i guess there is a command). go into the work state.
2535 if (len != 4) {
2536 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2537 break;
2538 }
2539 cardSTATE = MFEMUL_WORK;
2540 //goto lbWORK;
2541 //intentional fall-through to the next case-stmt
2542 }
2543
2544 case MFEMUL_WORK:{
2545 if (len == 0) {
2546 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2547 break;
2548 }
2549
2550 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2551
2552 if(encrypted_data) {
2553 // decrypt seqence
2554 mf_crypto1_decrypt(pcs, receivedCmd, len);
2555 }
2556
2557 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2558 authTimer = GetTickCount();
2559 cardAUTHSC = receivedCmd[1] / 4; // received block num
2560 cardAUTHKEY = receivedCmd[0] - 0x60;
2561 crypto1_destroy(pcs);//Added by martin
2562 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2563
2564 if (!encrypted_data) { // first authentication
2565 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2566
2567 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2568 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2569 } else { // nested authentication
2570 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2571 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2572 num_to_bytes(ans, 4, rAUTH_AT);
2573 }
2574
2575 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2576 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2577 cardSTATE = MFEMUL_AUTH1;
2578 break;
2579 }
2580
2581 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2582 // BUT... ACK --> NACK
2583 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2584 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2585 break;
2586 }
2587
2588 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2589 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2590 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2591 break;
2592 }
2593
2594 if(len != 4) {
2595 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2596 break;
2597 }
2598
2599 if(receivedCmd[0] == 0x30 // read block
2600 || receivedCmd[0] == 0xA0 // write block
2601 || receivedCmd[0] == 0xC0 // inc
2602 || receivedCmd[0] == 0xC1 // dec
2603 || receivedCmd[0] == 0xC2 // restore
2604 || receivedCmd[0] == 0xB0) { // transfer
2605 if (receivedCmd[1] >= 16 * 4) {
2606 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2607 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2608 break;
2609 }
2610
2611 if (receivedCmd[1] / 4 != cardAUTHSC) {
2612 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2613 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2614 break;
2615 }
2616 }
2617 // read block
2618 if (receivedCmd[0] == 0x30) {
2619 if (MF_DBGLEVEL >= 4) {
2620 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2621 }
2622 emlGetMem(response, receivedCmd[1], 1);
2623 AppendCrc14443a(response, 16);
2624 mf_crypto1_encrypt(pcs, response, 18, response_par);
2625 EmSendCmdPar(response, 18, response_par);
2626 numReads++;
2627 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2628 Dbprintf("%d reads done, exiting", numReads);
2629 finished = true;
2630 }
2631 break;
2632 }
2633 // write block
2634 if (receivedCmd[0] == 0xA0) {
2635 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2636 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2637 cardSTATE = MFEMUL_WRITEBL2;
2638 cardWRBL = receivedCmd[1];
2639 break;
2640 }
2641 // increment, decrement, restore
2642 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2643 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2644 if (emlCheckValBl(receivedCmd[1])) {
2645 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2646 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2647 break;
2648 }
2649 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2650 if (receivedCmd[0] == 0xC1)
2651 cardSTATE = MFEMUL_INTREG_INC;
2652 if (receivedCmd[0] == 0xC0)
2653 cardSTATE = MFEMUL_INTREG_DEC;
2654 if (receivedCmd[0] == 0xC2)
2655 cardSTATE = MFEMUL_INTREG_REST;
2656 cardWRBL = receivedCmd[1];
2657 break;
2658 }
2659 // transfer
2660 if (receivedCmd[0] == 0xB0) {
2661 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2662 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2663 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2664 else
2665 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2666 break;
2667 }
2668 // halt
2669 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2670 LED_B_OFF();
2671 LED_C_OFF();
2672 cardSTATE = MFEMUL_HALTED;
2673 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2674 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2675 break;
2676 }
2677 // RATS
2678 if (receivedCmd[0] == 0xe0) {//RATS
2679 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2680 break;
2681 }
2682 // command not allowed
2683 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2684 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2685 break;
2686 }
2687 case MFEMUL_WRITEBL2:{
2688 if (len == 18){
2689 mf_crypto1_decrypt(pcs, receivedCmd, len);
2690 emlSetMem(receivedCmd, cardWRBL, 1);
2691 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2692 cardSTATE = MFEMUL_WORK;
2693 } else {
2694 cardSTATE_TO_IDLE();
2695 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2696 }
2697 break;
2698 }
2699
2700 case MFEMUL_INTREG_INC:{
2701 mf_crypto1_decrypt(pcs, receivedCmd, len);
2702 memcpy(&ans, receivedCmd, 4);
2703 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2704 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2705 cardSTATE_TO_IDLE();
2706 break;
2707 }
2708 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2709 cardINTREG = cardINTREG + ans;
2710 cardSTATE = MFEMUL_WORK;
2711 break;
2712 }
2713 case MFEMUL_INTREG_DEC:{
2714 mf_crypto1_decrypt(pcs, receivedCmd, len);
2715 memcpy(&ans, receivedCmd, 4);
2716 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2717 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2718 cardSTATE_TO_IDLE();
2719 break;
2720 }
2721 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2722 cardINTREG = cardINTREG - ans;
2723 cardSTATE = MFEMUL_WORK;
2724 break;
2725 }
2726 case MFEMUL_INTREG_REST:{
2727 mf_crypto1_decrypt(pcs, receivedCmd, len);
2728 memcpy(&ans, receivedCmd, 4);
2729 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2730 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2731 cardSTATE_TO_IDLE();
2732 break;
2733 }
2734 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2735 cardSTATE = MFEMUL_WORK;
2736 break;
2737 }
2738 }
2739 }
2740
2741 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2742 LEDsoff();
2743
2744 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2745 {
2746 //May just aswell send the collected ar_nr in the response aswell
2747 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2748 }
2749
2750 if(flags & FLAG_NR_AR_ATTACK)
2751 {
2752 if(ar_nr_collected > 1) {
2753 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2754 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2755 ar_nr_responses[0], // UID
2756 ar_nr_responses[1], //NT
2757 ar_nr_responses[2], //AR1
2758 ar_nr_responses[3], //NR1
2759 ar_nr_responses[6], //AR2
2760 ar_nr_responses[7] //NR2
2761 );
2762 } else {
2763 Dbprintf("Failed to obtain two AR/NR pairs!");
2764 if(ar_nr_collected >0) {
2765 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2766 ar_nr_responses[0], // UID
2767 ar_nr_responses[1], //NT
2768 ar_nr_responses[2], //AR1
2769 ar_nr_responses[3] //NR1
2770 );
2771 }
2772 }
2773 }
2774 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
2775
2776 }
2777
2778
2779
2780 //-----------------------------------------------------------------------------
2781 // MIFARE sniffer.
2782 //
2783 //-----------------------------------------------------------------------------
2784 void RAMFUNC SniffMifare(uint8_t param) {
2785 // param:
2786 // bit 0 - trigger from first card answer
2787 // bit 1 - trigger from first reader 7-bit request
2788
2789 // C(red) A(yellow) B(green)
2790 LEDsoff();
2791 // init trace buffer
2792 clear_trace();
2793 set_tracing(TRUE);
2794
2795 // The command (reader -> tag) that we're receiving.
2796 // The length of a received command will in most cases be no more than 18 bytes.
2797 // So 32 should be enough!
2798 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2799 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
2800 // The response (tag -> reader) that we're receiving.
2801 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2802 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
2803
2804 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2805
2806 // free eventually allocated BigBuf memory
2807 BigBuf_free();
2808 // allocate the DMA buffer, used to stream samples from the FPGA
2809 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2810 uint8_t *data = dmaBuf;
2811 uint8_t previous_data = 0;
2812 int maxDataLen = 0;
2813 int dataLen = 0;
2814 bool ReaderIsActive = FALSE;
2815 bool TagIsActive = FALSE;
2816
2817 // Set up the demodulator for tag -> reader responses.
2818 DemodInit(receivedResponse, receivedResponsePar);
2819
2820 // Set up the demodulator for the reader -> tag commands
2821 UartInit(receivedCmd, receivedCmdPar);
2822
2823 // Setup for the DMA.
2824 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2825
2826 LED_D_OFF();
2827
2828 // init sniffer
2829 MfSniffInit();
2830
2831 // And now we loop, receiving samples.
2832 for(uint32_t sniffCounter = 0; TRUE; ) {
2833
2834 if(BUTTON_PRESS()) {
2835 DbpString("cancelled by button");
2836 break;
2837 }
2838
2839 LED_A_ON();
2840 WDT_HIT();
2841
2842 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2843 // check if a transaction is completed (timeout after 2000ms).
2844 // if yes, stop the DMA transfer and send what we have so far to the client
2845 if (MfSniffSend(2000)) {
2846 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2847 sniffCounter = 0;
2848 data = dmaBuf;
2849 maxDataLen = 0;
2850 ReaderIsActive = FALSE;
2851 TagIsActive = FALSE;
2852 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2853 }
2854 }
2855
2856 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2857 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2858 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2859 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2860 } else {
2861 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2862 }
2863 // test for length of buffer
2864 if(dataLen > maxDataLen) { // we are more behind than ever...
2865 maxDataLen = dataLen;
2866 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
2867 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2868 break;
2869 }
2870 }
2871 if(dataLen < 1) continue;
2872
2873 // primary buffer was stopped ( <-- we lost data!
2874 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2875 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2876 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2877 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2878 }
2879 // secondary buffer sets as primary, secondary buffer was stopped
2880 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2881 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2882 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2883 }
2884
2885 LED_A_OFF();
2886
2887 if (sniffCounter & 0x01) {
2888
2889 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2890 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2891 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2892 LED_C_INV();
2893 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
2894
2895 /* And ready to receive another command. */
2896 UartReset();
2897
2898 /* And also reset the demod code */
2899 DemodReset();
2900 }
2901 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2902 }
2903
2904 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2905 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2906 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2907 LED_C_INV();
2908
2909 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
2910
2911 // And ready to receive another response.
2912 DemodReset();
2913 }
2914 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2915 }
2916 }
2917
2918 previous_data = *data;
2919 sniffCounter++;
2920 data++;
2921 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2922 data = dmaBuf;
2923 }
2924
2925 } // main cycle
2926
2927 DbpString("COMMAND FINISHED");
2928
2929 FpgaDisableSscDma();
2930 MfSniffEnd();
2931
2932 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2933 LEDsoff();
2934 }
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