1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
5 //-----------------------------------------------------------------------------
6 // HitagS emulation (preliminary test version)
8 // (c) 2016 Oguzhan Cicek, Hendrik Schwartke, Ralf Spenneberg
10 //-----------------------------------------------------------------------------
11 // Some code was copied from Hitag2.c
12 //-----------------------------------------------------------------------------
16 #include "proxmark3.h"
24 #define CRC_PRESET 0xFF
25 #define CRC_POLYNOM 0x1D
30 #define rev8(x) ((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7))
31 #define rev16(x) (rev8 (x)+(rev8 (x>> 8)<< 8))
32 #define rev32(x) (rev16(x)+(rev16(x>>16)<<16))
33 #define rev64(x) (rev32(x)+(rev32(x>>32)<<32))
34 #define bit(x,n) (((x)>>(n))&1)
35 #define bit32(x,n) ((((x)[(n)>>5])>>((n)))&1)
36 #define inv32(x,i,n) ((x)[(i)>>5]^=((u32)(n))<<((i)&31))
37 #define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))
40 static bool bSuccessful
;
41 static struct hitagS_tag tag
;
42 static byte_t page_to_be_written
= 0;
43 static int block_data_left
= 0;
44 typedef enum modulation
{
45 AC2K
= 0, AC4K
, MC4K
, MC8K
47 static MOD m
= AC2K
; //used modulation
48 static uint32_t temp_uid
;
50 static int sof_bits
; //number of start-of-frame bits
51 static byte_t pwdh0
, pwdl0
, pwdl1
; //password bytes
52 static uint32_t rnd
= 0x74124485; //randomnumber
57 // Single bit Hitag2 functions:
58 #define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))
59 static const u32 ht2_f4a
= 0x2C79; // 0010 1100 0111 1001
60 static const u32 ht2_f4b
= 0x6671; // 0110 0110 0111 0001
61 static const u32 ht2_f5c
= 0x7907287B; // 0111 1001 0000 0111 0010 1000 0111 1011
62 #define ht2bs_4a(a,b,c,d) (~(((a|b)&c)^(a|d)^b))
63 #define ht2bs_4b(a,b,c,d) (~(((d|c)&(a^b))^(d|a|b)))
64 #define ht2bs_5c(a,b,c,d,e) (~((((((c^e)|d)&a)^b)&(c^b))^(((d^e)|a)&((d^b)|c))))
67 static u32
f20(const u64 x
) {
70 i5
= ((ht2_f4a
>> i4(x
, 1, 2, 4, 5)) & 1) * 1
71 + ((ht2_f4b
>> i4(x
, 7, 11, 13, 14)) & 1) * 2
72 + ((ht2_f4b
>> i4(x
, 16, 20, 22, 25)) & 1) * 4
73 + ((ht2_f4b
>> i4(x
, 27, 28, 30, 32)) & 1) * 8
74 + ((ht2_f4a
>> i4(x
, 33, 42, 43, 45)) & 1) * 16;
76 return (ht2_f5c
>> i5
) & 1;
78 static u64
hitag2_round(u64
*state
) {
82 + ((((x
>> 0) ^ (x
>> 2) ^ (x
>> 3) ^ (x
>> 6) ^ (x
>> 7) ^ (x
>> 8)
83 ^ (x
>> 16) ^ (x
>> 22) ^ (x
>> 23) ^ (x
>> 26) ^ (x
>> 30)
84 ^ (x
>> 41) ^ (x
>> 42) ^ (x
>> 43) ^ (x
>> 46) ^ (x
>> 47))
90 static u64
hitag2_init(const u64 key
, const u32 serial
, const u32 IV
) {
92 u64 x
= ((key
& 0xFFFF) << 32) + serial
;
93 for (i
= 0; i
< 32; i
++) {
95 x
+= (u64
) (f20(x
) ^ (((IV
>> i
) ^ (key
>> (i
+ 16))) & 1)) << 47;
99 static u32
hitag2_byte(u64
*x
) {
102 for (i
= 0, c
= 0; i
< 8; i
++)
103 c
+= (u32
) hitag2_round(x
) << (i
^ 7);
107 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
108 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
109 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
110 // T0 = TIMER_CLOCK1 / 125000 = 192
113 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
114 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
116 #define HITAG_FRAME_LEN 20
117 #define HITAG_T_STOP 36 /* T_EOF should be > 36 */
118 #define HITAG_T_LOW 8 /* T_LOW should be 4..10 */
119 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
120 #define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */
121 //#define HITAG_T_EOF 40 /* T_EOF should be > 36 */
122 #define HITAG_T_EOF 80 /* T_EOF should be > 36 */
123 #define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */
124 #define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */
125 #define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */
127 #define HITAG_T_TAG_ONE_HALF_PERIOD 10
128 #define HITAG_T_TAG_TWO_HALF_PERIOD 25
129 #define HITAG_T_TAG_THREE_HALF_PERIOD 41
130 #define HITAG_T_TAG_FOUR_HALF_PERIOD 57
132 #define HITAG_T_TAG_HALF_PERIOD 16
133 #define HITAG_T_TAG_FULL_PERIOD 32
135 #define HITAG_T_TAG_CAPTURE_ONE_HALF 13
136 #define HITAG_T_TAG_CAPTURE_TWO_HALF 25
137 #define HITAG_T_TAG_CAPTURE_THREE_HALF 41
138 #define HITAG_T_TAG_CAPTURE_FOUR_HALF 57
143 * Implementation of the crc8 calculation from Hitag S
144 * from http://www.proxmark.org/files/Documents/125%20kHz%20-%20Hitag/HitagS.V11.pdf
146 void calc_crc(unsigned char * crc
, unsigned char data
, unsigned char Bitcount
) {
147 *crc
^= data
; // crc = crc (exor) data
149 if (*crc
& 0x80) // if (MSB-CRC == 1)
151 *crc
<<= 1; // CRC = CRC Bit-shift left
152 *crc
^= CRC_POLYNOM
; // CRC = CRC (exor) CRC_POLYNOM
154 *crc
<<= 1; // CRC = CRC Bit-shift left
156 } while (--Bitcount
);
160 static void hitag_send_bit(int bit
) {
162 // Reset clock for the next bit
163 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
170 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
173 while (AT91C_BASE_TC0
->TC_CV
< T0
* 64)
178 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
181 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
184 while (AT91C_BASE_TC0
->TC_CV
< T0
* 48)
187 while (AT91C_BASE_TC0
->TC_CV
< T0
* 64)
196 while (AT91C_BASE_TC0
->TC_CV
< T0
* HITAG_T_TAG_HALF_PERIOD
)
199 while (AT91C_BASE_TC0
->TC_CV
< T0
* HITAG_T_TAG_FULL_PERIOD
)
204 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
207 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
210 while (AT91C_BASE_TC0
->TC_CV
< T0
* 24)
213 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
220 // Manchester: Unloaded, then loaded |__--|
222 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
225 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
228 // Manchester: Loaded, then unloaded |--__|
230 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
233 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
240 // Manchester: Unloaded, then loaded |__--|
242 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
245 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
248 // Manchester: Loaded, then unloaded |--__|
250 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
253 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
263 static void hitag_tag_send_frame(const byte_t
* frame
, size_t frame_len
) {
264 // Send start of frame
265 for (size_t i
= 0; i
< sof_bits
; i
++) {
269 // Send the content of the frame
270 for (size_t i
= 0; i
< frame_len
; i
++) {
271 hitag_send_bit((frame
[i
/ 8] >> (7 - (i
% 8))) & 1);
273 // Drop the modulation
277 static void hitag_reader_send_bit(int bit
) {
278 //Dbprintf("BIT: %d",bit);
280 // Reset clock for the next bit
281 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
283 // Binary puls length modulation (BPLM) is used to encode the data stream
284 // This means that a transmission of a one takes longer than that of a zero
286 // Enable modulation, which means, drop the the field
289 // Wait for 4-10 times the carrier period
290 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
294 // Disable modulation, just activates the field again
299 while (AT91C_BASE_TC0
->TC_CV
< T0
* 11)
301 // SpinDelayUs(16*8);
304 while (AT91C_BASE_TC0
->TC_CV
< T0
* 14)
306 // SpinDelayUs(22*8);
309 // Wait for 4-10 times the carrier period
310 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
314 // Disable modulation, just activates the field again
319 while (AT91C_BASE_TC0
->TC_CV
< T0
* 22)
321 // SpinDelayUs(16*8);
324 while (AT91C_BASE_TC0
->TC_CV
< T0
* 28)
326 // SpinDelayUs(22*8);
333 static void hitag_reader_send_frame(const byte_t
* frame
, size_t frame_len
) {
334 // Send the content of the frame
335 for (size_t i
= 0; i
< frame_len
; i
++) {
336 if (frame
[0] == 0xf8) {
337 //Dbprintf("BIT: %d",(frame[i / 8] >> (7 - (i % 8))) & 1);
339 hitag_reader_send_bit(((frame
[i
/ 8] >> (7 - (i
% 8))) & 1));
342 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
343 // Enable modulation, which means, drop the the field
345 // Wait for 4-10 times the carrier period
346 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
348 // Disable modulation, just activates the field again
352 static void hitag_decode_frame_MC(int bitRate
, int sofBits
, byte_t
* rx
, size_t* rxlenOrg
, int* response
, int rawMod
[], int rawLen
) {
362 for (int i
=0; i
< rawLen
; i
++) {
364 if (ra
>= HITAG_T_EOF
) {
366 //DbpString("wierd1?");
370 // Capture the T0 periods that have passed since last communication or field drop (reset)
371 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
372 *response
= ra
- HITAG_T_TAG_HALF_PERIOD
;
373 } else if (ra
>= HITAG_T_TAG_CAPTURE_FOUR_HALF
/ timing
) {
375 // Manchester coding example |-_|_-|-_| (101)
376 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
378 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
380 } else if (ra
>= HITAG_T_TAG_CAPTURE_THREE_HALF
/ timing
) {
382 // Manchester coding example |_-|...|_-|-_| (0...01)
383 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
385 // We have to skip this half period at start and add the 'one' the second time
387 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
392 } else if (ra
>= HITAG_T_TAG_CAPTURE_TWO_HALF
/ timing
) {
393 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
395 // Ignore bits that are transmitted during SOF
398 // bit is same as last bit
399 rx
[rxlen
/ 8] |= lastbit
<< (7 - (rxlen
% 8));
403 // Ignore wierd value, is to small to mean anything
410 static void hitag_decode_frame_AC2K_rising(byte_t* rx, size_t* rxlenOrg, int* response, int rawMod[], int rawLen) {
411 int tag_sof = 1; //skip start of frame
414 for (int i=0; i < rawLen; i++) {
416 if (ra >= HITAG_T_EOF) {
418 //DbpString("wierd1?");
420 // Capture the T0 periods that have passed since last communication or field drop (reset)
421 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
423 *response = ra - HITAG_T_TAG_HALF_PERIOD;
424 } else if (ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
425 // AC coding example |--__|--__| means 0
426 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
428 if (rawMod[i+1] == 0) { //TODO: this is weird - may we miss one capture with current configuration
429 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
431 i++; //drop next capture
433 } else if (ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
435 // Ignore bits that are transmitted during SOF
438 // AC coding example |-_-_|-_-_| which means 1
439 //check if another high is coming (only -_-_ = 1) except end of the frame (support 0)
440 if (rawMod[i+1] == 0 || rawMod[i+1] >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
441 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
443 i++; //drop next capture
445 Dbprintf("got weird high - %d,%d", ra, rawMod[i+1]);
449 // Ignore wierd value, is to small to mean anything
456 static void hitag_decode_frame_AC(int bitRate
, int sofBits
, byte_t
* rx
, size_t* rxlenOrg
, int* response
, int rawMod
[], int rawLen
) {
465 for (int i
=0; i
< rawLen
; i
++) {
467 if (ra
>= HITAG_T_EOF
) {
469 //DbpString("wierd1?");
472 // Capture the T0 periods that have passed since last communication or field drop (reset)
473 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
475 *response
= ra
- HITAG_T_TAG_HALF_PERIOD
;
476 } else if (ra
>= HITAG_T_TAG_CAPTURE_FOUR_HALF
/ timing
) {
479 // AC coding example |--__|--__| means 0
480 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
482 } else if (ra
>= HITAG_T_TAG_CAPTURE_THREE_HALF
/ timing
) {
485 if (rawMod
[i
-1] >= HITAG_T_TAG_CAPTURE_THREE_HALF
/ timing
) {
486 //treat like HITAG_T_TAG_CAPTURE_TWO_HALF
487 if (rawMod
[i
+1] >= HITAG_T_TAG_CAPTURE_TWO_HALF
/ timing
) {
488 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
490 i
++; //drop next capture
492 Dbprintf("got weird value - %d,%d", ra
, rawMod
[i
+1]);
495 //treat like HITAG_T_TAG_CAPTURE_FOUR_HALF
496 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
499 } else if (ra
>= HITAG_T_TAG_CAPTURE_TWO_HALF
/ timing
) {
501 // Ignore bits that are transmitted during SOF
504 // AC coding example |-_-_|-_-_| which means 1
505 //check if another high is coming (only -_-_ = 1) except end of the frame (support 0)
506 if (rawMod
[i
+1] == 0 || rawMod
[i
+1] >= HITAG_T_TAG_CAPTURE_TWO_HALF
/ timing
) {
507 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
509 i
++; //drop next capture
511 Dbprintf("got weird value - %d,%d", ra
, rawMod
[i
+1]);
515 // Ignore wierd value, is to small to mean anything
521 static void hitag_receive_frame(byte_t
* rx
, size_t* rxlen
, int* response
) {
522 int rawMod
[200] = {0};
528 if (tag
.pstate
== READY
) {
536 sofBits
= 5; //3 sof bits but 5 captures
540 sofBits
= 5; //3 sof bits but 5 captures
549 sofBits
= 0; //in theory 1
553 sofBits
= 5; //in theory 6
557 sofBits
= 5; //in theory 6
564 //rising AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
565 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_FALLING
;
568 //first capture timing values
569 while (AT91C_BASE_TC1
->TC_CV
< T0
* HITAG_T_WAIT_MAX
) {
570 // Check if rising edge in modulation is detected
571 if (AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
572 // Retrieve the new timing values
573 int ra
= (AT91C_BASE_TC1
->TC_RA
/ T0
);
576 // Reset timer every frame, we have to capture the last edge for timing
577 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
578 //AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
580 if (rawLen
>= 200) { //avoid exception
586 // We can break this loop if we received the last bit from a frame
587 if (AT91C_BASE_TC1
->TC_CV
> T0
* HITAG_T_EOF
) {
589 if (DEBUG
>= 2) { Dbprintf("AT91C_BASE_TC1->TC_CV > T0 * HITAG_T_EOF breaking (%d)", rawLen
); }
597 for (i
=0; i
< rawLen
; i
+=20) {
598 Dbprintf("raw modulation: - %d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d",
599 rawMod
[i
],rawMod
[i
+1],rawMod
[i
+2],rawMod
[i
+3], rawMod
[i
+4],rawMod
[i
+5],rawMod
[i
+6],rawMod
[i
+7],
600 rawMod
[i
+8],rawMod
[i
+9],rawMod
[i
+10],rawMod
[i
+11], rawMod
[i
+12],rawMod
[i
+13],rawMod
[i
+14],rawMod
[i
+15],
601 rawMod
[i
+16],rawMod
[i
+17],rawMod
[i
+18],rawMod
[i
+19]
607 // DATA | 1 | 0 | 1 | 1 | 0 |
608 // Manchester |--__|__--|--__|--__|__--|
609 // Anti Collision |-_-_|--__|-_-_|-_-_|--__|
613 if (DEBUG
>= 2) { Dbprintf("decoding frame with modulation AC2K"); }
614 hitag_decode_frame_AC(2, sofBits
, rx
, rxlen
, response
, rawMod
, rawLen
);
617 if (DEBUG
>= 2) { Dbprintf("decoding frame with modulation AC4K"); }
618 hitag_decode_frame_AC(4, sofBits
, rx
, rxlen
, response
, rawMod
, rawLen
);
621 if (DEBUG
>= 2) { Dbprintf("decoding frame with modulation MC4K"); }
622 hitag_decode_frame_MC(4, sofBits
, rx
, rxlen
, response
, rawMod
, rawLen
);
625 if (DEBUG
>= 2) { Dbprintf("decoding frame with modulation MC8K"); }
626 hitag_decode_frame_MC(8, sofBits
, rx
, rxlen
, response
, rawMod
, rawLen
);
632 int rb
[200] = {0}; int z
= 0;
633 for (i
= 0; i
< 16; i
++) { for (int j
= 0; j
< 8; j
++) {
635 if ((rx
[i
] & ((1 << 7) >> j
)) != 0) { rb
[z
] = 1; }
638 for (i
=0; i
< z
; i
+=8) {
639 Dbprintf("raw bit: - %d%d%d%d%d%d%d%d", rb
[i
],rb
[i
+1],rb
[i
+2],rb
[i
+3],rb
[i
+4],rb
[i
+5],rb
[i
+6],rb
[i
+7] );
644 static void hitag_start_auth(byte_t
* tx
, size_t* txlen
) {
648 //00110 - 0x30 - STANDARD MODE
649 memcpy(tx
, "\x30", nbytes(*txlen
));
652 //11000 - 0xc0 - Advance Mode
653 memcpy(tx
, "\xc0", nbytes(*txlen
));
658 default: //STANDARD MODE
659 memcpy(tx
, "\x30", nbytes(*txlen
));
666 static int hitag_read_page(hitag_function htf
, uint64_t key
, byte_t
* rx
, size_t* rxlen
, byte_t
* tx
, size_t* txlen
, int pageNum
) {
668 int response_bit
[200];
669 unsigned char mask
= 1;
671 unsigned char pageData
[32];
673 if (pageNum
>= tag
.max_page
) {
676 if (tag
.pstate
== SELECTED
&& tag
.tstate
== NO_OP
&& *rxlen
> 0) {
678 tag
.tstate
= READING_PAGE
;
681 tx
[0] = 0xc0 + (pageNum
/ 16);
682 calc_crc(&crc
, tx
[0], 8);
683 calc_crc(&crc
, 0x00 + ((pageNum
% 16) * 16), 4);
684 tx
[1] = 0x00 + ((pageNum
% 16) * 16) + (crc
/ 16);
685 tx
[2] = 0x00 + (crc
% 16) * 16;
686 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== READING_PAGE
&& *rxlen
> 0) {
689 for (i
= 0; i
< 4; i
++) {
690 for (j
= 0; j
< 8; j
++) {
692 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0) {
696 pageData
[z
] = response_bit
[z
];
702 for (i
= 0; i
< 4; i
++) {
703 tag
.pages
[pageNum
][i
] = 0x0;
705 for (i
= 0; i
< 4; i
++) {
706 tag
.pages
[pageNum
][i
] += ((pageData
[i
* 8] << 7) | (pageData
[1 + (i
* 8)] << 6) |
707 (pageData
[2 + (i
* 8)] << 5) | (pageData
[3 + (i
* 8)] << 4) |
708 (pageData
[4 + (i
* 8)] << 3) | (pageData
[5 + (i
* 8)] << 2) |
709 (pageData
[6 + (i
* 8)]
710 << 1) | pageData
[7 + (i
* 8)]);
712 if (tag
.auth
&& tag
.LKP
&& pageNum
== 1) {
713 Dbprintf("Page[%2d]: %02X %02X %02X %02X", pageNum
, pwdh0
,
714 tag
.pages
[pageNum
][2], tag
.pages
[pageNum
][1], tag
.pages
[pageNum
][0]);
716 Dbprintf("Page[%2d]: %02X %02X %02X %02X", pageNum
,
717 tag
.pages
[pageNum
][3], tag
.pages
[pageNum
][2],
718 tag
.pages
[pageNum
][1], tag
.pages
[pageNum
][0]);
722 //display key and password if possible
723 if (pageNum
== 1 && tag
.auth
== 1 && tag
.LKP
) {
724 if (htf
== 02) { //RHTS_KEY
725 Dbprintf("Page[ 2]: %02X %02X %02X %02X",
726 (byte_t
)(key
>> 8) & 0xff,
727 (byte_t
) key
& 0xff, pwdl1
, pwdl0
);
728 Dbprintf("Page[ 3]: %02X %02X %02X %02X",
729 (byte_t
)(key
>> 40) & 0xff,
730 (byte_t
)(key
>> 32) & 0xff,
731 (byte_t
)(key
>> 24) & 0xff,
732 (byte_t
)(key
>> 16) & 0xff);
734 //if the authentication is done with a challenge the key and password are unknown
735 Dbprintf("Page[ 2]: __ __ __ __");
736 Dbprintf("Page[ 3]: __ __ __ __");
742 tx
[0] = 0xc0 + ((pageNum
+1) / 16);
743 calc_crc(&crc
, tx
[0], 8);
744 calc_crc(&crc
, 0x00 + (((pageNum
+1) % 16) * 16), 4);
745 tx
[1] = 0x00 + (((pageNum
+1) % 16) * 16) + (crc
/ 16);
746 tx
[2] = 0x00 + (crc
% 16) * 16;
753 static int hitag_read_block(hitag_function htf
, uint64_t key
, byte_t
* rx
, size_t* rxlen
, byte_t
* tx
, size_t* txlen
, int blockNum
) {
755 int response_bit
[200];
756 unsigned char mask
= 1;
758 unsigned char blockData
[128];
760 if (blockNum
+4 >= tag
.max_page
) { //block always = 4 pages
764 if (tag
.pstate
== SELECTED
&& tag
.tstate
== NO_OP
&& *rxlen
> 0) {
766 tag
.tstate
= READING_BLOCK
;
769 tx
[0] = 0xd0 + (blockNum
/ 16);
770 calc_crc(&crc
, tx
[0], 8);
771 calc_crc(&crc
, 0x00 + ((blockNum
% 16) * 16), 4);
772 tx
[1] = 0x00 + ((blockNum
% 16) * 16) + (crc
/ 16);
773 tx
[2] = 0x00 + (crc
% 16) * 16;
774 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== READING_BLOCK
&& *rxlen
> 0) {
777 for (i
= 0; i
< 16; i
++) {
778 for (j
= 0; j
< 8; j
++) {
780 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0) {
784 blockData
[z
] = response_bit
[z
];
790 for (z
= 0; z
< 4; z
++) { //4 pages
791 for (i
= 0; i
< 4; i
++) {
792 tag
.pages
[blockNum
+z
][i
] = 0x0;
795 for (z
= 0; z
< 4; z
++) { //4 pages
796 for (i
= 0; i
< 4; i
++) {
797 j
= (i
* 8) + (z
*32); //bit in page + pageStart
798 tag
.pages
[blockNum
+z
][i
] = ((blockData
[j
] << 7) | (blockData
[1 + j
] << 6) |
799 (blockData
[2 + j
] << 5) | (blockData
[3 + j
] << 4) |
800 (blockData
[4 + j
] << 3) | (blockData
[5 + j
] << 2) |
801 (blockData
[6 + j
] << 1) | blockData
[7 + j
]);
805 for (z
= 0; z
< 4; z
++) {
806 Dbprintf("Page[%2d]: %02X %02X %02X %02X", blockNum
+z
,
807 tag
.pages
[blockNum
+z
][3], tag
.pages
[blockNum
+z
][2],
808 tag
.pages
[blockNum
+z
][1], tag
.pages
[blockNum
+z
][0]);
811 Dbprintf("Block[%2d]: %02X %02X %02X %02X - %02X %02X %02X %02X - %02X %02X %02X %02X - %02X %02X %02X %02X", blockNum
,
812 tag
.pages
[blockNum
][3], tag
.pages
[blockNum
][2], tag
.pages
[blockNum
][1], tag
.pages
[blockNum
][0],
813 tag
.pages
[blockNum
+1][3], tag
.pages
[blockNum
+1][2], tag
.pages
[blockNum
+1][1], tag
.pages
[blockNum
+1][0],
814 tag
.pages
[blockNum
+2][3], tag
.pages
[blockNum
+2][2], tag
.pages
[blockNum
+2][1], tag
.pages
[blockNum
+2][0],
815 tag
.pages
[blockNum
+3][3], tag
.pages
[blockNum
+3][2], tag
.pages
[blockNum
+3][1], tag
.pages
[blockNum
+3][0]);
819 tx
[0] = 0xd0 + ((blockNum
+4) / 16);
820 calc_crc(&crc
, tx
[0], 8);
821 calc_crc(&crc
, 0x00 + (((blockNum
+4) % 16) * 16), 4);
822 tx
[1] = 0x00 + (((blockNum
+4) % 16) * 16) + (crc
/ 16);
823 tx
[2] = 0x00 + (crc
% 16) * 16;
832 * to check if the right uid was selected
834 static int check_select(byte_t
* rx
, uint32_t uid
) {
835 unsigned char resp
[48];
838 for (i
= 0; i
< 48; i
++)
839 resp
[i
] = (rx
[i
/ 8] >> (7 - (i
% 8))) & 0x1;
840 for (i
= 0; i
< 32; i
++)
841 ans
+= resp
[5 + i
] << (31 - i
);
842 /*if (rx[0] == 0x01 && rx[1] == 0x15 && rx[2] == 0xc1 && rx[3] == 0x14
843 && rx[4] == 0x65 && rx[5] == 0x38)
844 Dbprintf("got uid %X", ans);*/
852 * handles all commands from a reader
854 static void hitagS_handle_reader_command(byte_t
* rx
, const size_t rxlen
,
855 byte_t
* tx
, size_t* txlen
) {
856 byte_t rx_air
[HITAG_FRAME_LEN
];
862 // Copy the (original) received frame how it is send over the air
863 memcpy(rx_air
, rx
, nbytes(rxlen
));
864 // Reset the transmission frame length
866 // Try to find out which command was send by selecting on length (in bits)
869 //UID request with a selected response protocol mode
872 if ((rx
[0] & 0xf0) == 0x30) {
873 Dbprintf("recieved uid request in Standard Mode");
878 if ((rx
[0] & 0xf0) == 0xc0) {
879 Dbprintf("recieved uid request in ADVANCE Mode");
884 if ((rx
[0] & 0xf0) == 0xd0) {
885 Dbprintf("recieved uid request in FAST_ADVANCE Mode");
886 tag
.mode
= FAST_ADVANCED
;
890 //send uid as a response
892 for (i
= 0; i
< 4; i
++) {
893 tx
[i
] = (tag
.uid
>> (24 - (i
* 8))) & 0xff;
898 //select command from reader received
899 if (check_select(rx
, tag
.uid
) == 1) {
900 //if the right tag was selected
904 Dbprintf("uid selected in Standard Mode");
909 Dbprintf("uid selected in ADVANCE Mode");
914 Dbprintf("uid selected in FAST_ADVANCE Mode");
923 tx
[0] = tag
.pages
[1][3];
924 tx
[1] = tag
.pages
[1][2];
925 tx
[2] = tag
.pages
[1][1];
927 if (tag
.mode
!= STANDARD
) {
930 for (i
= 0; i
< 4; i
++)
931 calc_crc(&crc
, tx
[i
], 8);
954 //challenge message received
955 Dbprintf("Challenge for UID: %X", temp_uid
);
957 state
= hitag2_init(rev64(tag
.key
), rev32(tag
.pages
[0][0]),
958 rev32(((rx
[3] << 24) + (rx
[2] << 16) + (rx
[1] << 8) + rx
[0])));
960 ",{0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X}",
961 rx
[0], rx
[1], rx
[2], rx
[3], rx
[4], rx
[5], rx
[6], rx
[7]);
963 for (i
= 0; i
< 4; i
++) {
968 //send con2,pwdh0,pwdl0,pwdl1 encrypted as a response
969 tx
[0] = hitag2_byte(&state
) ^ tag
.pages
[1][1];
970 tx
[1] = hitag2_byte(&state
) ^ tag
.pwdh0
;
971 tx
[2] = hitag2_byte(&state
) ^ tag
.pwdl0
;
972 tx
[3] = hitag2_byte(&state
) ^ tag
.pwdl1
;
973 if (tag
.mode
!= STANDARD
) {
977 calc_crc(&crc
, tag
.pages
[1][1], 8);
978 calc_crc(&crc
, tag
.pwdh0
, 8);
979 calc_crc(&crc
, tag
.pwdl0
, 8);
980 calc_crc(&crc
, tag
.pwdl1
, 8);
981 tx
[4] = (crc
^ hitag2_byte(&state
));
985 //data received to be written
986 if (tag
.tstate
== WRITING_PAGE_DATA
) {
988 tag
.pages
[page_to_be_written
][0] = rx
[3];
989 tag
.pages
[page_to_be_written
][1] = rx
[2];
990 tag
.pages
[page_to_be_written
][2] = rx
[1];
991 tag
.pages
[page_to_be_written
][3] = rx
[0];
996 page_to_be_written
= 0;
1013 } else if (tag
.tstate
== WRITING_BLOCK_DATA
) {
1014 tag
.pages
[page_to_be_written
][0] = rx
[0];
1015 tag
.pages
[page_to_be_written
][1] = rx
[1];
1016 tag
.pages
[page_to_be_written
][2] = rx
[2];
1017 tag
.pages
[page_to_be_written
][3] = rx
[3];
1038 page_to_be_written
++;
1040 if (block_data_left
== 0) {
1042 page_to_be_written
= 0;
1047 //write page, write block, read page or read block command received
1048 if ((rx
[0] & 0xf0) == 0xc0) { //read page
1050 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
1051 Dbprintf("reading page %d", page
);
1053 tx
[0] = tag
.pages
[page
][0];
1054 tx
[1] = tag
.pages
[page
][1];
1055 tx
[2] = tag
.pages
[page
][2];
1056 tx
[3] = tag
.pages
[page
][3];
1058 if (tag
.LKP
&& page
== 1)
1078 if (tag
.mode
!= STANDARD
) {
1082 for (i
= 0; i
< 4; i
++)
1083 calc_crc(&crc
, tx
[i
], 8);
1087 if (tag
.LKP
&& (page
== 2 || page
== 3)) {
1088 //if reader asks for key or password and the LKP-mark is set do not respond
1092 } else if ((rx
[0] & 0xf0) == 0xd0) { //read block
1093 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
1094 Dbprintf("reading block %d", page
);
1096 //send page,...,page+3 data
1097 for (i
= 0; i
< 4; i
++) {
1098 tx
[0 + (i
* 4)] = tag
.pages
[page
][0];
1099 tx
[1 + (i
* 4)] = tag
.pages
[page
][1];
1100 tx
[2 + (i
* 4)] = tag
.pages
[page
][2];
1101 tx
[3 + (i
* 4)] = tag
.pages
[page
][3];
1122 if (tag
.mode
!= STANDARD
) {
1124 *txlen
= 32 * 4 + 8;
1126 for (i
= 0; i
< 16; i
++)
1127 calc_crc(&crc
, tx
[i
], 8);
1131 if ((page
- 4) % 4 != 0 || (tag
.LKP
&& (page
- 4) == 0)) {
1135 } else if ((rx
[0] & 0xf0) == 0x80) { //write page
1136 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
1154 if ((tag
.LCON
&& page
== 1)
1155 || (tag
.LKP
&& (page
== 2 || page
== 3))) {
1162 page_to_be_written
= page
;
1163 tag
.tstate
= WRITING_PAGE_DATA
;
1166 } else if ((rx
[0] & 0xf0) == 0x90) { //write block
1167 page
= ((rx
[0] & 0x0f) * 6) + ((rx
[1] & 0xf0) / 16);
1184 if (page
% 4 != 0 || page
== 0) {
1191 page_to_be_written
= page
;
1192 block_data_left
= 4;
1193 tag
.tstate
= WRITING_BLOCK_DATA
;
1206 * to autenticate to a tag with the given key or challenge
1208 static int hitagS_handle_tag_auth(hitag_function htf
,uint64_t key
, uint64_t NrAr
, byte_t
* rx
,
1209 const size_t rxlen
, byte_t
* tx
, size_t* txlen
) {
1210 byte_t rx_air
[HITAG_FRAME_LEN
];
1211 int response_bit
[200] = {0};
1213 unsigned char mask
= 1;
1214 unsigned char uid
[32];
1215 byte_t uid1
= 0x00, uid2
= 0x00, uid3
= 0x00, uid4
= 0x00;
1219 byte_t conf_pages
[3];
1220 memcpy(rx_air
, rx
, nbytes(rxlen
));
1224 Dbprintf("START hitagS_handle_tag_auth - rxlen: %d, tagstate=%d", rxlen
, (int)tag
.pstate
);
1227 if (tag
.pstate
== READY
&& rxlen
>= 32) {
1230 Dbprintf("authentication failed!");
1234 for (i
= 0; i
< 10; i
++) {
1235 for (j
= 0; j
< 8; j
++) {
1236 response_bit
[z
] = 0;
1237 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
1238 response_bit
[z
] = 1;
1242 for (i
= 0; i
< 32; i
++) {
1243 uid
[i
] = response_bit
[i
];
1246 uid1
= (uid
[0] << 7) | (uid
[1] << 6) | (uid
[2] << 5) | (uid
[3] << 4)
1247 | (uid
[4] << 3) | (uid
[5] << 2) | (uid
[6] << 1) | uid
[7];
1248 uid2
= (uid
[8] << 7) | (uid
[9] << 6) | (uid
[10] << 5) | (uid
[11] << 4)
1249 | (uid
[12] << 3) | (uid
[13] << 2) | (uid
[14] << 1) | uid
[15];
1250 uid3
= (uid
[16] << 7) | (uid
[17] << 6) | (uid
[18] << 5) | (uid
[19] << 4)
1251 | (uid
[20] << 3) | (uid
[21] << 2) | (uid
[22] << 1) | uid
[23];
1252 uid4
= (uid
[24] << 7) | (uid
[25] << 6) | (uid
[26] << 5) | (uid
[27] << 4)
1253 | (uid
[28] << 3) | (uid
[29] << 2) | (uid
[30] << 1) | uid
[31];
1254 Dbprintf("UID: %02X %02X %02X %02X", uid1
, uid2
, uid3
, uid4
);
1255 tag
.uid
= (uid4
<< 24 | uid3
<< 16 | uid2
<< 8 | uid1
);
1259 calc_crc(&crc
, 0x00, 5);
1260 calc_crc(&crc
, uid1
, 8);
1261 calc_crc(&crc
, uid2
, 8);
1262 calc_crc(&crc
, uid3
, 8);
1263 calc_crc(&crc
, uid4
, 8);
1264 Dbprintf("crc: %02X", crc
);
1266 //resetting response bit
1267 for (i
= 0; i
< 100; i
++) {
1268 response_bit
[i
] = 0;
1272 for (i
= 5; i
< 37; i
++) {
1273 response_bit
[i
] = uid
[i
- 5];
1276 for (j
= 0; j
< 8; j
++) {
1277 response_bit
[i
] = 0;
1278 if ((crc
& ((mask
<< 7) >> j
)) != 0)
1279 response_bit
[i
] = 1;
1284 for (i
= 0; i
< 6; i
++) {
1285 tx
[i
] = (response_bit
[k
] << 7) | (response_bit
[k
+ 1] << 6)
1286 | (response_bit
[k
+ 2] << 5) | (response_bit
[k
+ 3] << 4)
1287 | (response_bit
[k
+ 4] << 3) | (response_bit
[k
+ 5] << 2)
1288 | (response_bit
[k
+ 6] << 1) | response_bit
[k
+ 7];
1293 } else if (tag
.pstate
== INIT
&& rxlen
> 24) {
1294 // received configuration after select command
1296 for (i
= 0; i
< 4; i
++) {
1297 for (j
= 0; j
< 8; j
++) {
1298 response_bit
[z
] = 0;
1299 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0) {
1300 response_bit
[z
] = 1;
1306 //check wich memorysize this tag has
1308 if (response_bit
[6] == 0 && response_bit
[7] == 0)
1309 tag
.max_page
= 32 / 32;
1310 if (response_bit
[6] == 0 && response_bit
[7] == 1)
1311 tag
.max_page
= 256 / 32;
1312 if (response_bit
[6] == 1 && response_bit
[7] == 0)
1313 tag
.max_page
= 2048 / 32;
1314 if (response_bit
[6] == 1 && response_bit
[7] == 1) //reserved but some tags got this setting
1315 tag
.max_page
= 2048 / 32;
1318 tag
.auth
= response_bit
[8];
1319 tag
.TTFC
= response_bit
[9];
1320 //tag.TTFDR in response_bit[10] and response_bit[11]
1321 //tag.TTFM in response_bit[12] and response_bit[13]
1322 tag
.LCON
= response_bit
[14];
1323 tag
.LKP
= response_bit
[15];
1326 tag
.LCK7
= response_bit
[16];
1327 tag
.LCK6
= response_bit
[17];
1328 tag
.LCK5
= response_bit
[18];
1329 tag
.LCK4
= response_bit
[19];
1330 tag
.LCK3
= response_bit
[20];
1331 tag
.LCK2
= response_bit
[21];
1332 tag
.LCK1
= response_bit
[22];
1333 tag
.LCK0
= response_bit
[23];
1336 conf_pages
[0] = ((response_bit
[0] << 7) | (response_bit
[1] << 6)
1337 | (response_bit
[2] << 5) | (response_bit
[3] << 4)
1338 | (response_bit
[4] << 3) | (response_bit
[5] << 2)
1339 | (response_bit
[6] << 1) | response_bit
[7]);
1340 conf_pages
[1] = ((response_bit
[8] << 7) | (response_bit
[9] << 6)
1341 | (response_bit
[10] << 5) | (response_bit
[11] << 4)
1342 | (response_bit
[12] << 3) | (response_bit
[13] << 2)
1343 | (response_bit
[14] << 1) | response_bit
[15]);
1344 conf_pages
[2] = ((response_bit
[16] << 7) | (response_bit
[17] << 6)
1345 | (response_bit
[18] << 5) | (response_bit
[19] << 4)
1346 | (response_bit
[20] << 3) | (response_bit
[21] << 2)
1347 | (response_bit
[22] << 1) | response_bit
[23]);
1348 Dbprintf("conf0: %02X conf1: %02X conf2: %02X", conf_pages
[0], conf_pages
[1], conf_pages
[2]);
1349 Dbprintf("tag.max_page: %d, tag.auth: %d", tag
.max_page
, tag
.auth
);
1352 if (tag
.auth
== 1) {
1353 //if the tag is in authentication mode try the key or challenge
1356 if(htf
==02||htf
==04){ //RHTS_KEY //WHTS_KEY
1357 state
= hitag2_init(rev64(key
), rev32(tag
.uid
), rev32(rnd
));
1359 Dbprintf("key: %02X %02X\n\n", key, rev64(key));
1360 Dbprintf("tag.uid: %02X %02X\n\n", tag.uid, rev32(tag.uid));
1361 Dbprintf("rnd: %02X %02X\n\n", rnd, rev32(rnd));
1363 for (i
= 0; i
< 4; i
++) {
1364 auth_ks
[i
] = hitag2_byte(&state
) ^ 0xff;
1368 tx
[1] = (rnd
>> 8) & 0xff;
1369 tx
[2] = (rnd
>> 16) & 0xff;
1370 tx
[3] = (rnd
>> 24) & 0xff;
1377 Dbprintf("%02X %02X %02X %02X %02X %02X %02X %02X", tx
[0],
1378 tx
[1], tx
[2], tx
[3], tx
[4], tx
[5], tx
[6], tx
[7]);
1379 } else if(htf
==01 || htf
==03) { //RHTS_CHALLENGE //WHTS_CHALLENGE
1380 for (i
= 0; i
< 8; i
++)
1381 tx
[i
]=((NrAr
>>(56-(i
*8)))&0xff);
1384 tag
.pstate
= AUTHENTICATE
;
1386 Dbprintf("authentication failed!");
1389 } else if (tag
.auth
== 0) {
1390 tag
.pstate
= SELECTED
;
1393 } else if (tag
.pstate
== AUTHENTICATE
&& rxlen
>= 32) {
1394 //encrypted con2,password received.
1396 Dbprintf("UID:::%X", tag
.uid
);
1397 Dbprintf("RND:::%X", rnd
);
1404 if(htf
==02 || htf
==04) { //RHTS_KEY //WHTS_KEY
1405 state
= hitag2_init(rev64(key
), rev32(tag
.uid
), rev32(rnd
));
1406 for (i
= 0; i
< 5; i
++) {
1407 hitag2_byte(&state
);
1409 pwdh0
= ((rx
[1] & 0x0f) * 16 + ((rx
[2] & 0xf0) / 16)) ^ hitag2_byte(&state
);
1410 pwdl0
= ((rx
[2] & 0x0f) * 16 + ((rx
[3] & 0xf0) / 16)) ^ hitag2_byte(&state
);
1411 pwdl1
= ((rx
[3] & 0x0f) * 16 + ((rx
[4] & 0xf0) / 16)) ^ hitag2_byte(&state
);
1413 Dbprintf("pwdh0 %02X pwdl0 %02X pwdl1 %02X", pwdh0
, pwdl0
, pwdl1
);
1416 tag
.pstate
= SELECTED
; //tag is now ready for read/write commands
1420 Dbprintf("END hitagS_handle_tag_auth - tagstate=%d", (int)tag
.pstate
);
1427 * Emulates a Hitag S Tag with the given data from the .hts file
1429 void SimulateHitagSTag(bool tag_mem_supplied
, byte_t
* data
) {
1434 byte_t rx
[HITAG_FRAME_LEN
];
1437 byte_t txbuf
[HITAG_FRAME_LEN
];
1440 uint8_t con0
, con1
, con2
;
1443 // Clean up trace and prepare it for storing frames
1447 DbpString("Starting HitagS simulation");
1452 //read tag data into memory
1453 if (tag_mem_supplied
) {
1454 DbpString("Loading hitagS memory...");
1455 for (i
= 0; i
< 64; i
++) {
1456 for (j
= 0; j
< 4; j
++) {
1457 tag
.pages
[i
][j
] = 0x0;
1461 for (i
= 0; i
< 64; i
++) {
1462 for (j
= 0; j
< 4; j
++) {
1463 tag
.pages
[i
][j
] = data
[(i
*4)+j
];
1467 tag
.uid
= (tag
.pages
[0][3] << 24 | tag
.pages
[0][2] << 16 | tag
.pages
[0][1] << 8 | tag
.pages
[0][0]);
1468 con0
= tag
.pages
[1][3];
1469 con1
= tag
.pages
[1][2];
1470 con2
= tag
.pages
[1][1];
1471 Dbprintf("UID: %X", tag
.uid
);
1472 Dbprintf("Hitag S simulation started");
1474 //0x01 plain mode - Reserved, CON2, CON1, CON0
1475 //0x01 auth mode - PWDH 0, CON2, CON1, CON0
1476 //0x02 auth mode - KEYH 1, KEYH 0, PWDL 1, PWDL 0
1477 //0x03 auth mode - KEYL 3, KEYL 2, KEYL 1, KEYL 0
1480 tag
.max_page
= 2048 / 32;
1481 if ((con0
& 0x2) == 0 && (con0
& 0x1) == 1)
1482 tag
.max_page
= 256 / 32;
1483 if ((con0
& 0x2) == 0 && (con0
& 0x1) == 0)
1484 tag
.max_page
= 32 / 32;
1487 tag
.auth
= ((con1
& 0x80) == 0x80) ? 1 : 0;
1488 tag
.TTFC
= ((con1
& 0x40) == 0x40) ? 1 : 0;
1489 //tag.TTFDR in response_bit[10] and response_bit[11]
1490 //tag.TTFM in response_bit[12] and response_bit[13]
1491 tag
.LCON
= ((con1
& 0x2) == 0x2) ? 1 : 0;
1492 tag
.LKP
= ((con1
& 0x1) == 0x1) ? 1 : 0;
1495 tag
.LCK7
= ((con2
& 0x80) == 0x80) ? 1 : 0;
1496 tag
.LCK6
= ((con2
& 0x40) == 0x40) ? 1 : 0;
1497 tag
.LCK5
= ((con2
& 0x20) == 0x20) ? 1 : 0;
1498 tag
.LCK4
= ((con2
& 0x10) == 0x10) ? 1 : 0;
1499 tag
.LCK3
= ((con2
& 0x8) == 0x8) ? 1 : 0;
1500 tag
.LCK2
= ((con2
& 0x4) == 0x4) ? 1 : 0;
1501 tag
.LCK1
= ((con2
& 0x2) == 0x2) ? 1 : 0;
1502 tag
.LCK0
= ((con2
& 0x1) == 0x1) ? 1 : 0;
1504 if (tag
.auth
== 1) {
1505 //TODO check if this working :D
1506 tag
.key
=(intptr_t)tag
.pages
[3];
1508 tag
.key
+=((tag
.pages
[2][0])<<8)+tag
.pages
[2][1];
1509 tag
.pwdl0
=tag
.pages
[2][3];
1510 tag
.pwdl1
=tag
.pages
[2][2];
1511 tag
.pwdh0
=tag
.pages
[1][0];
1514 // Set up simulator mode, frequency divisor which will drive the FPGA
1515 // and analog mux selection.
1516 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1517 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
);
1518 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1519 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1522 // Configure output pin that is connected to the FPGA (for modulating)
1523 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1524 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1526 // Disable modulation at default, which means release resistance
1529 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1530 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1532 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
1533 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1534 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1536 // Disable timer during configuration
1537 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1539 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1540 // external trigger rising edge, load RA on rising edge of TIOA.
1541 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_RISING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_RISING
;
1543 // Reset the received frame, frame count and timing info
1544 memset(rx
, 0x00, sizeof(rx
));
1549 // Enable and reset counter
1550 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1552 while (!BUTTON_PRESS()) {
1556 // Receive frame, watch for at most T0*EOF periods
1558 while (AT91C_BASE_TC1
->TC_CV
< T0
* HITAG_T_EOF
) {
1559 // Check if rising edge in modulation is detected
1560 if (AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
1561 // Retrieve the new timing values
1562 int ra
= (AT91C_BASE_TC1
->TC_RA
/ T0
) + overflow
;
1565 // Reset timer every frame, we have to capture the last edge for timing
1566 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1570 // Capture reader frame
1571 if (ra
>= HITAG_T_STOP
) {
1573 //DbpString("wierd0?");
1575 // Capture the T0 periods that have passed since last communication or field drop (reset)
1576 response
= (ra
- HITAG_T_LOW
);
1577 } else if (ra
>= HITAG_T_1_MIN
) {
1579 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
1581 } else if (ra
>= HITAG_T_0_MIN
) {
1583 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
1586 // Ignore wierd value, is to small to mean anything
1591 // Check if frame was captured
1595 if (!LogTraceHitag(rx
, rxlen
, response
, 0, true)) {
1596 DbpString("Trace full");
1601 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1602 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1604 // Process the incoming frame (rx) and prepare the outgoing frame (tx)
1605 hitagS_handle_reader_command(rx
, rxlen
, tx
, &txlen
);
1607 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
1608 // not that since the clock counts since the rising edge, but T_Wait1 is
1609 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
1610 // periods. The gap time T_Low varies (4..10). All timer values are in
1611 // terms of T0 units
1612 while (AT91C_BASE_TC0
->TC_CV
< T0
* (HITAG_T_WAIT_1
- HITAG_T_LOW
)) { }
1614 // Send and store the tag answer (if there is any)
1616 // Transmit the tag frame
1617 hitag_tag_send_frame(tx
, txlen
);
1619 // Store the frame in the trace
1621 if (!LogTraceHitag(tx
, txlen
, 0, 0, false)) {
1622 DbpString("Trace full");
1628 // Enable and reset external trigger in timer for capturing future frames
1629 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1631 // Reset the received frame and response timing info
1632 memset(rx
, 0x00, sizeof(rx
));
1637 // Reset the frame length
1639 // Save the timer overflow, will be 0 when frame was received
1640 overflow
+= (AT91C_BASE_TC1
->TC_CV
/ T0
);
1641 // Reset the timer to restart while-loop that receives frames
1642 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_SWTRG
;
1644 Dbprintf("Hitag S simulation stopped");
1647 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1648 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
1649 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1653 * Authenticates to the Tag with the given key or challenge.
1654 * If the key was given the password will be decrypted.
1655 * Reads every page of a hitag S transpoder.
1657 void ReadHitagSintern(hitag_function htf
, hitag_data
* htd
, stype tagMode
, int startPage
, bool readBlock
) {
1660 int sendNum
= startPage
;
1664 //int response_bit[200];
1665 //unsigned char mask = 1;
1668 byte_t rx
[HITAG_FRAME_LEN
];
1670 byte_t txbuf
[HITAG_FRAME_LEN
];
1674 int t_wait
= HITAG_T_WAIT_MAX
;
1676 bool bQuitTraceFull
= false;
1678 page_to_be_written
= 0;
1680 //read given key/challenge
1687 case 03: { //RHTS_CHALLENGE
1688 DbpString("Authenticating using nr,ar pair:");
1689 memcpy(NrAr_
,htd
->auth
.NrAr
,8);
1690 Dbhexdump(8,NrAr_
,false);
1691 NrAr
=NrAr_
[7] | ((uint64_t)NrAr_
[6]) << 8 | ((uint64_t)NrAr_
[5]) << 16 | ((uint64_t)NrAr_
[4]) << 24 | ((uint64_t)NrAr_
[3]) << 32 |
1692 ((uint64_t)NrAr_
[2]) << 40| ((uint64_t)NrAr_
[1]) << 48 | ((uint64_t)NrAr_
[0]) << 56;
1695 case 04: { //RHTS_KEY
1696 DbpString("Authenticating using key:");
1697 memcpy(key_
,htd
->crypto
.key
,6);
1698 Dbhexdump(6,key_
,false);
1699 key
=key_
[5] | ((uint64_t)key_
[4]) << 8 | ((uint64_t)key_
[3]) << 16 | ((uint64_t)key_
[2]) << 24 | ((uint64_t)key_
[1]) << 32 | ((uint64_t)key_
[0]) << 40;
1702 Dbprintf("Error , unknown function: %d",htf
);
1709 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1710 // Reset the return status
1711 bSuccessful
= false;
1713 // Clean up trace and prepare it for storing frames
1721 // Configure output and enable pin that is connected to the FPGA (for modulating)
1722 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1723 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1725 // Set fpga in edge detect with reader field, we can modulate as reader now
1726 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
1728 // Set Frequency divisor which will drive the FPGA and analog mux selection
1729 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1730 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1733 // Disable modulation at default, which means enable the field
1736 // Give it a bit of time for the resonant antenna to settle.
1739 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1740 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1742 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1743 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1744 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1746 // Disable timer during configuration
1747 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1749 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1750 // external trigger rising edge, load RA on falling edge of TIOA.
1751 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_FALLING
;
1753 // Enable and reset counters
1754 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1755 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1757 // Reset the received frame, frame count and timing info
1764 while (!bStop
&& !BUTTON_PRESS()) {
1769 // Add transmitted frame to total count
1773 if (tag
.pstate
== READY
&& rxlen
< 1) {
1774 //skip logging starting auths if no response
1777 // Store the frame in the trace
1778 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
1779 if (bQuitTraceFull
) {
1780 DbpString("Trace full");
1790 // Check if frame was captured and store it
1794 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
1795 DbpString("Trace full");
1796 if (bQuitTraceFull
) {
1805 // By default reset the transmission buffer
1810 Dbprintf("FRO %d rxlen: %d, pstate=%d, tstate=%d", frame_count
, rxlen
, (int)tag
.pstate
, (int)tag
.tstate
);
1814 //start authentication
1815 hitag_start_auth(tx
, &txlen
);
1816 } else if (tag
.pstate
!= SELECTED
) {
1817 if (hitagS_handle_tag_auth(htf
, key
,NrAr
,rx
, rxlen
, tx
, &txlen
) == -1) {
1818 Dbprintf("hitagS_handle_tag_auth - bStop = !false");
1825 if (readBlock
&& tag
.pstate
== SELECTED
&& (tag
.tstate
== READING_BLOCK
|| tag
.tstate
== NO_OP
) && rxlen
> 0) {
1826 i
= hitag_read_block(htf
, key
, rx
, &rxlen
, tx
, &txlen
, sendNum
);
1827 if (i
> 0) { sendNum
+=4; }
1828 if (sendNum
+4 >= tag
.max_page
) {
1831 } else if (!readBlock
&& tag
.pstate
== SELECTED
&& (tag
.tstate
== READING_PAGE
|| tag
.tstate
== NO_OP
) && rxlen
> 0) {
1832 i
= hitag_read_page(htf
, key
, rx
, &rxlen
, tx
, &txlen
, sendNum
);
1833 if (i
> 0) { sendNum
++; }
1834 if (sendNum
>= tag
.max_page
) {
1839 // Send and store the reader command
1840 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1841 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1843 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1844 // Since the clock counts since the last falling edge, a 'one' means that the
1845 // falling edge occured halfway the period. with respect to this falling edge,
1846 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1847 // All timer values are in terms of T0 units
1849 while (AT91C_BASE_TC0
->TC_CV
< T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
))) { }
1851 // Transmit the reader frame
1852 hitag_reader_send_frame(tx
, txlen
);
1855 // Enable and reset external trigger in timer for capturing future frames
1856 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1859 // Reset values for receiving frames
1860 memset(rx
, 0x00, sizeof(rx
));
1865 // get tag id in anti-collision mode (proprietary data format, so switch off manchester and read at double the data rate, for 4 x the data bits)
1866 hitag_receive_frame(rx
, &rxlen
, &response
);
1871 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1872 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
1873 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1874 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);
1877 void ReadHitagSCmd(hitag_function htf
, hitag_data
* htd
, uint64_t startPage
, uint64_t tagMode
, bool readBlock
) {
1879 Dbprintf("ReadHitagS in mode=ADVANCED, blockRead=%d, startPage=%d", readBlock
, startPage
);
1880 ReadHitagSintern(htf
, htd
, ADVANCED
, (int)startPage
, readBlock
);
1881 } else if (tagMode
== 2) {
1882 Dbprintf("ReadHitagS in mode=FAST_ADVANCED, blockRead=%d, startPage=%d", readBlock
, startPage
);
1883 ReadHitagSintern(htf
, htd
, FAST_ADVANCED
, (int)startPage
, readBlock
);
1885 Dbprintf("ReadHitagS in mode=STANDARD, blockRead=%d, startPage=%d", readBlock
, startPage
);
1886 ReadHitagSintern(htf
, htd
, STANDARD
, (int)startPage
, readBlock
);
1893 * Authenticates to the Tag with the given Key or Challenge.
1894 * Writes the given 32Bit data into page_
1896 void WritePageHitagS(hitag_function htf
, hitag_data
* htd
,int page_
) {
1899 byte_t rx
[HITAG_FRAME_LEN
];
1901 byte_t txbuf
[HITAG_FRAME_LEN
];
1905 int t_wait
= HITAG_T_WAIT_MAX
;
1907 bool bQuitTraceFull
= false;
1910 byte_t data
[4]= {0,0,0,0};
1912 //read given key/challenge, the page and the data
1918 case 03: { //WHTS_CHALLENGE
1919 memcpy(data
,htd
->auth
.data
,4);
1920 DbpString("Authenticating using nr,ar pair:");
1921 memcpy(NrAr_
,htd
->auth
.NrAr
,8);
1922 Dbhexdump(8,NrAr_
,false);
1923 NrAr
=NrAr_
[7] | ((uint64_t)NrAr_
[6]) << 8 | ((uint64_t)NrAr_
[5]) << 16 | ((uint64_t)NrAr_
[4]) << 24 | ((uint64_t)NrAr_
[3]) << 32 |
1924 ((uint64_t)NrAr_
[2]) << 40| ((uint64_t)NrAr_
[1]) << 48 | ((uint64_t)NrAr_
[0]) << 56;
1926 case 04: { //WHTS_KEY
1927 memcpy(data
,htd
->crypto
.data
,4);
1928 DbpString("Authenticating using key:");
1929 memcpy(key_
,htd
->crypto
.key
,6);
1930 Dbhexdump(6,key_
,false);
1931 key
=key_
[5] | ((uint64_t)key_
[4]) << 8 | ((uint64_t)key_
[3]) << 16 | ((uint64_t)key_
[2]) << 24 | ((uint64_t)key_
[1]) << 32 | ((uint64_t)key_
[0]) << 40;
1934 Dbprintf("Error , unknown function: %d",htf
);
1939 Dbprintf("Page: %d",page_
);
1940 Dbprintf("DATA: %02X %02X %02X %02X", data
[0], data
[1], data
[2], data
[3]);
1941 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1942 // Reset the return status
1943 bSuccessful
= false;
1948 // Clean up trace and prepare it for storing frames
1956 // Configure output and enable pin that is connected to the FPGA (for modulating)
1957 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1958 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1960 // Set fpga in edge detect with reader field, we can modulate as reader now
1961 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
1963 // Set Frequency divisor which will drive the FPGA and analog mux selection
1964 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1965 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1968 // Disable modulation at default, which means enable the field
1971 // Give it a bit of time for the resonant antenna to settle.
1974 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1975 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1977 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1978 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1979 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1981 // Disable timer during configuration
1982 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1984 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1985 // external trigger rising edge, load RA on falling edge of TIOA.
1986 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1987 | AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
1988 | AT91C_TC_LDRA_FALLING
;
1990 // Enable and reset counters
1991 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1992 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1994 // Reset the received frame, frame count and timing info
2001 while (!bStop
&& !BUTTON_PRESS()) {
2005 // Check if frame was captured and store it
2009 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
2010 DbpString("Trace full");
2011 if (bQuitTraceFull
) {
2020 //check for valid input
2023 Dbprintf("usage: lf hitag writer [03 | 04] [CHALLENGE | KEY] [page] [byte0] [byte1] [byte2] [byte3]");
2028 // By default reset the transmission buffer
2032 if (rxlen
== 0 && tag
.tstate
== WRITING_PAGE_ACK
) {
2033 //no write access on this page
2034 Dbprintf("no write access on page %d", page_
);
2036 } else if (rxlen
== 0 && tag
.tstate
!= WRITING_PAGE_DATA
) {
2037 //start the authetication
2038 //tag.mode = ADVANCED;
2039 tag
.mode
= STANDARD
;
2040 hitag_start_auth(tx
, &txlen
);
2042 } else if (tag
.pstate
!= SELECTED
) {
2043 //try to authenticate with the given key or challenge
2044 if (hitagS_handle_tag_auth(htf
,key
,NrAr
,rx
, rxlen
, tx
, &txlen
) == -1) {
2050 if (tag
.pstate
== SELECTED
&& tag
.tstate
== NO_OP
&& rxlen
> 0) {
2051 //check if the given page exists
2052 if (page
> tag
.max_page
) {
2053 Dbprintf("page number too big");
2056 //ask Tag for write permission
2057 tag
.tstate
= WRITING_PAGE_ACK
;
2060 tx
[0] = 0x90 + (page
/ 16);
2061 calc_crc(&crc
, tx
[0], 8);
2062 calc_crc(&crc
, 0x00 + ((page
% 16) * 16), 4);
2063 tx
[1] = 0x00 + ((page
% 16) * 16) + (crc
/ 16);
2064 tx
[2] = 0x00 + (crc
% 16) * 16;
2065 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== WRITING_PAGE_ACK
2066 && rxlen
== 2 && rx
[0] == 0x40) {
2067 //ACK recieved to write the page. send data
2068 tag
.tstate
= WRITING_PAGE_DATA
;
2071 calc_crc(&crc
, data
[3], 8);
2072 calc_crc(&crc
, data
[2], 8);
2073 calc_crc(&crc
, data
[1], 8);
2074 calc_crc(&crc
, data
[0], 8);
2080 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== WRITING_PAGE_DATA
2081 && rxlen
== 2 && rx
[0] == 0x40) {
2083 Dbprintf("Successful!");
2087 // Send and store the reader command
2088 // Disable timer 1 with external trigger to avoid triggers during our own modulation
2089 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2091 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
2092 // Since the clock counts since the last falling edge, a 'one' means that the
2093 // falling edge occured halfway the period. with respect to this falling edge,
2094 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
2095 // All timer values are in terms of T0 units
2097 while (AT91C_BASE_TC0
->TC_CV
2098 < T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
)))
2101 // Transmit the reader frame
2102 hitag_reader_send_frame(tx
, txlen
);
2104 // Enable and reset external trigger in timer for capturing future frames
2105 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2107 // Add transmitted frame to total count
2111 // Store the frame in the trace
2112 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
2113 if (bQuitTraceFull
) {
2114 DbpString("Trace full");
2123 // Reset values for receiving frames
2124 memset(rx
, 0x00, sizeof(rx
));
2129 hitag_receive_frame(rx
, &rxlen
, &response
);
2134 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2135 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
2136 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2137 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);
2142 * Tries to authenticate to a Hitag S Transponder with the given challenges from a .cc file.
2143 * Displays all Challenges that failed.
2144 * When collecting Challenges to break the key it is possible that some data
2145 * is not received correctly due to Antenna problems. This function
2146 * detects these challenges.
2148 void check_challenges_cmd(bool file_given
, byte_t
* data
, uint64_t tagMode
) {
2153 byte_t rx
[HITAG_FRAME_LEN
];
2154 byte_t unlocker
[60][8];
2157 byte_t txbuf
[HITAG_FRAME_LEN
];
2161 int t_wait
= HITAG_T_WAIT_MAX
;
2164 bool bQuitTraceFull
= false;
2165 int response_bit
[200];
2166 unsigned char mask
= 1;
2167 unsigned char uid
[32];
2171 Dbprintf("check_challenges in mode=ADVANCED");
2172 tag
.mode
= ADVANCED
;
2173 } else if (tagMode
== 2) {
2174 Dbprintf("check_challenges in mode=FAST_ADVANCED");
2175 tag
.mode
= FAST_ADVANCED
;
2177 Dbprintf("check_challenges in mode=STANDARD");
2178 tag
.mode
= STANDARD
;
2182 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
2183 // Reset the return status
2184 bSuccessful
= false;
2186 // Clean up trace and prepare it for storing frames
2194 // Configure output and enable pin that is connected to the FPGA (for modulating)
2195 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
2196 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
2198 // Set fpga in edge detect with reader field, we can modulate as reader now
2200 FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
2202 // Set Frequency divisor which will drive the FPGA and analog mux selection
2203 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
2204 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
2207 // Disable modulation at default, which means enable the field
2210 // Give it a bit of time for the resonant antenna to settle.
2213 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
2214 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
2216 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
2217 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
2218 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
2220 // Disable timer during configuration
2221 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2223 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
2224 // external trigger rising edge, load RA on falling edge of TIOA.
2225 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_FALLING
;
2227 // Enable and reset counters
2228 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2229 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2231 // Reset the received frame, frame count and timing info
2240 DbpString("Loading challenges...");
2241 memcpy((byte_t
*)unlocker
,data
,60*8);
2244 while (file_given
&& !bStop
&& !BUTTON_PRESS()) {
2248 // Check if frame was captured and store it
2252 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
2253 DbpString("Trace full");
2254 if (bQuitTraceFull
) {
2268 Dbprintf("Challenge failed: %02X %02X %02X %02X %02X %02X %02X %02X",
2269 unlocker
[u1
- 1][0], unlocker
[u1
- 1][1],
2270 unlocker
[u1
- 1][2], unlocker
[u1
- 1][3],
2271 unlocker
[u1
- 1][4], unlocker
[u1
- 1][5],
2272 unlocker
[u1
- 1][6], unlocker
[u1
- 1][7]);
2275 hitag_start_auth(tx
, &txlen
);
2276 } else if (rxlen
>= 32 && STATE
== 0) {
2279 for (i
= 0; i
< 10; i
++) {
2280 for (j
= 0; j
< 8; j
++) {
2281 response_bit
[z
] = 0;
2282 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
2283 response_bit
[z
] = 1;
2287 for (i
= 0; i
< 32; i
++) {
2288 uid
[i
] = response_bit
[i
];
2291 uid_byte
[0] = (uid
[0] << 7) | (uid
[1] << 6) | (uid
[2] << 5)
2292 | (uid
[3] << 4) | (uid
[4] << 3) | (uid
[5] << 2)
2293 | (uid
[6] << 1) | uid
[7];
2294 uid_byte
[1] = (uid
[8] << 7) | (uid
[9] << 6) | (uid
[10] << 5)
2295 | (uid
[11] << 4) | (uid
[12] << 3) | (uid
[13] << 2)
2296 | (uid
[14] << 1) | uid
[15];
2297 uid_byte
[2] = (uid
[16] << 7) | (uid
[17] << 6) | (uid
[18] << 5)
2298 | (uid
[19] << 4) | (uid
[20] << 3) | (uid
[21] << 2)
2299 | (uid
[22] << 1) | uid
[23];
2300 uid_byte
[3] = (uid
[24] << 7) | (uid
[25] << 6) | (uid
[26] << 5)
2301 | (uid
[27] << 4) | (uid
[28] << 3) | (uid
[29] << 2)
2302 | (uid
[30] << 1) | uid
[31];
2303 //Dbhexdump(10, rx, rxlen);
2307 calc_crc(&crc
, 0x00, 5);
2308 calc_crc(&crc
, uid_byte
[0], 8);
2309 calc_crc(&crc
, uid_byte
[1], 8);
2310 calc_crc(&crc
, uid_byte
[2], 8);
2311 calc_crc(&crc
, uid_byte
[3], 8);
2312 for (i
= 0; i
< 100; i
++) {
2313 response_bit
[i
] = 0;
2315 for (i
= 0; i
< 5; i
++) {
2316 response_bit
[i
] = 0;
2318 for (i
= 5; i
< 37; i
++) {
2319 response_bit
[i
] = uid
[i
- 5];
2321 for (j
= 0; j
< 8; j
++) {
2322 response_bit
[i
] = 0;
2323 if ((crc
& ((mask
<< 7) >> j
)) != 0)
2324 response_bit
[i
] = 1;
2328 for (i
= 0; i
< 6; i
++) {
2329 tx
[i
] = (response_bit
[k
] << 7) | (response_bit
[k
+ 1] << 6)
2330 | (response_bit
[k
+ 2] << 5)
2331 | (response_bit
[k
+ 3] << 4)
2332 | (response_bit
[k
+ 4] << 3)
2333 | (response_bit
[k
+ 5] << 2)
2334 | (response_bit
[k
+ 6] << 1) | response_bit
[k
+ 7];
2340 } else if (STATE
== 1 && rxlen
> 24) {
2341 //received configuration
2344 for (i
= 0; i
< 6; i
++) {
2345 for (j
= 0; j
< 8; j
++) {
2346 response_bit
[z
] = 0;
2347 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
2348 response_bit
[z
] = 1;
2354 if (u1
>= (sizeof(unlocker
) / sizeof(unlocker
[0])))
2356 for (i
= 0; i
< 8; i
++)
2357 tx
[i
] = unlocker
[u1
][i
];
2360 tag
.pstate
= SELECTED
;
2361 } else if (STATE
== 2 && rxlen
>= 32) {
2365 // Send and store the reader command
2366 // Disable timer 1 with external trigger to avoid triggers during our own modulation
2367 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2369 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
2370 // Since the clock counts since the last falling edge, a 'one' means that the
2371 // falling edge occured halfway the period. with respect to this falling edge,
2372 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
2373 // All timer values are in terms of T0 units
2374 while (AT91C_BASE_TC0
->TC_CV
< T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
))) { }
2376 // Transmit the reader frame
2377 hitag_reader_send_frame(tx
, txlen
);
2379 // Enable and reset external trigger in timer for capturing future frames
2380 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2382 // Add transmitted frame to total count
2386 // Store the frame in the trace
2387 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
2388 if (bQuitTraceFull
) {
2389 DbpString("Trace full");
2398 // Reset values for receiving frames
2399 memset(rx
, 0x00, sizeof(rx
));
2404 hitag_receive_frame(rx
, &rxlen
, &response
);
2408 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2409 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
2410 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2411 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);
2415 Backward compatibility
2417 void check_challenges(bool file_given
, byte_t
* data
) {
2418 check_challenges_cmd(file_given
, data
, 1);
2421 void ReadHitagS(hitag_function htf
, hitag_data
* htd
) {
2422 ReadHitagSintern(htf
, htd
, ADVANCED
, 0, false);