1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
13 #include "iso14443a.h"
17 #include "proxmark3.h"
21 #include "iso14443crc.h"
22 #include "crapto1/crapto1.h"
23 #include "mifareutil.h"
24 #include "mifaresniff.h"
26 #include "protocols.h"
28 #include "fpgaloader.h"
34 // DEMOD_MOD_FIRST_HALF,
35 // DEMOD_NOMOD_FIRST_HALF,
41 uint16_t collisionPos
;
48 uint32_t startTime
, endTime
;
63 STATE_START_OF_COMMUNICATION
,
79 uint32_t startTime
, endTime
;
84 static uint32_t iso14a_timeout
;
85 #define MAX_ISO14A_TIMEOUT 524288
89 // the block number for the ISO14443-4 PCB
90 static uint8_t iso14_pcb_blocknum
= 0;
95 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
96 #define REQUEST_GUARD_TIME (7000/16 + 1)
97 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
98 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
99 // bool LastCommandWasRequest = false;
102 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
104 // When the PM acts as reader and is receiving tag data, it takes
105 // 3 ticks delay in the AD converter
106 // 16 ticks until the modulation detector completes and sets curbit
107 // 8 ticks until bit_to_arm is assigned from curbit
108 // 8*16 ticks for the transfer from FPGA to ARM
109 // 4*16 ticks until we measure the time
110 // - 8*16 ticks because we measure the time of the previous transfer
111 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
113 // When the PM acts as a reader and is sending, it takes
114 // 4*16 ticks until we can write data to the sending hold register
115 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
116 // 8 ticks until the first transfer starts
117 // 8 ticks later the FPGA samples the data
118 // 1 tick to assign mod_sig_coil
119 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
121 // When the PM acts as tag and is receiving it takes
122 // 2 ticks delay in the RF part (for the first falling edge),
123 // 3 ticks for the A/D conversion,
124 // 8 ticks on average until the start of the SSC transfer,
125 // 8 ticks until the SSC samples the first data
126 // 7*16 ticks to complete the transfer from FPGA to ARM
127 // 8 ticks until the next ssp_clk rising edge
128 // 4*16 ticks until we measure the time
129 // - 8*16 ticks because we measure the time of the previous transfer
130 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
132 // The FPGA will report its internal sending delay in
133 uint16_t FpgaSendQueueDelay
;
134 // the 5 first bits are the number of bits buffered in mod_sig_buf
135 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
136 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
138 // When the PM acts as tag and is sending, it takes
139 // 4*16 + 8 ticks until we can write data to the sending hold register
140 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
141 // 8 ticks later the FPGA samples the first data
142 // + 16 ticks until assigned to mod_sig
143 // + 1 tick to assign mod_sig_coil
144 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
145 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8 + 8*16 + 8 + 16 + 1 + DELAY_FPGA_QUEUE)
147 // When the PM acts as sniffer and is receiving tag data, it takes
148 // 3 ticks A/D conversion
149 // 14 ticks to complete the modulation detection
150 // 8 ticks (on average) until the result is stored in to_arm
151 // + the delays in transferring data - which is the same for
152 // sniffing reader and tag data and therefore not relevant
153 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
155 // When the PM acts as sniffer and is receiving reader data, it takes
156 // 2 ticks delay in analogue RF receiver (for the falling edge of the
157 // start bit, which marks the start of the communication)
158 // 3 ticks A/D conversion
159 // 8 ticks on average until the data is stored in to_arm.
160 // + the delays in transferring data - which is the same for
161 // sniffing reader and tag data and therefore not relevant
162 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
164 //variables used for timing purposes:
165 //these are in ssp_clk cycles:
166 static uint32_t NextTransferTime
;
167 static uint32_t LastTimeProxToAirStart
;
168 static uint32_t LastProxToAirDuration
;
172 // CARD TO READER - manchester
173 // Sequence D: 11110000 modulation with subcarrier during first half
174 // Sequence E: 00001111 modulation with subcarrier during second half
175 // Sequence F: 00000000 no modulation with subcarrier
176 // READER TO CARD - miller
177 // Sequence X: 00001100 drop after half a period
178 // Sequence Y: 00000000 no drop
179 // Sequence Z: 11000000 drop at start
187 void iso14a_set_trigger(bool enable
) {
192 void iso14a_set_timeout(uint32_t timeout
) {
193 // adjust timeout by FPGA delays and 2 additional ssp_frames to detect SOF
194 iso14a_timeout
= timeout
+ (DELAY_AIR2ARM_AS_READER
+ DELAY_ARM2AIR_AS_READER
)/(16*8) + 2;
195 if(MF_DBGLEVEL
>= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", timeout
, timeout
/ 106);
199 uint32_t iso14a_get_timeout(void) {
200 return iso14a_timeout
- (DELAY_AIR2ARM_AS_READER
+ DELAY_ARM2AIR_AS_READER
)/(16*8) - 2;
203 //-----------------------------------------------------------------------------
204 // Generate the parity value for a byte sequence
206 //-----------------------------------------------------------------------------
207 void GetParity(const uint8_t *pbtCmd
, uint16_t iLen
, uint8_t *par
)
209 uint16_t paritybit_cnt
= 0;
210 uint16_t paritybyte_cnt
= 0;
211 uint8_t parityBits
= 0;
213 for (uint16_t i
= 0; i
< iLen
; i
++) {
214 // Generate the parity bits
215 parityBits
|= ((oddparity8(pbtCmd
[i
])) << (7-paritybit_cnt
));
216 if (paritybit_cnt
== 7) {
217 par
[paritybyte_cnt
] = parityBits
; // save 8 Bits parity
218 parityBits
= 0; // and advance to next Parity Byte
226 // save remaining parity bits
227 par
[paritybyte_cnt
] = parityBits
;
231 void AppendCrc14443a(uint8_t* data
, int len
)
233 ComputeCrc14443(CRC_14443_A
,data
,len
,data
+len
,data
+len
+1);
236 static void AppendCrc14443b(uint8_t* data
, int len
)
238 ComputeCrc14443(CRC_14443_B
,data
,len
,data
+len
,data
+len
+1);
242 //=============================================================================
243 // ISO 14443 Type A - Miller decoder
244 //=============================================================================
246 // This decoder is used when the PM3 acts as a tag.
247 // The reader will generate "pauses" by temporarily switching of the field.
248 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
249 // The FPGA does a comparison with a threshold and would deliver e.g.:
250 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
251 // The Miller decoder needs to identify the following sequences:
252 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
253 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
254 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
255 // Note 1: the bitstream may start at any time. We therefore need to sync.
256 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
257 //-----------------------------------------------------------------------------
260 // Lookup-Table to decide if 4 raw bits are a modulation.
261 // We accept the following:
262 // 0001 - a 3 tick wide pause
263 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
264 // 0111 - a 2 tick wide pause shifted left
265 // 1001 - a 2 tick wide pause shifted right
266 const bool Mod_Miller_LUT
[] = {
267 false, true, false, true, false, false, false, true,
268 false, true, false, false, false, false, false, false
270 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
271 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
273 static void UartReset()
275 Uart
.state
= STATE_UNSYNCD
;
277 Uart
.len
= 0; // number of decoded data bytes
278 Uart
.parityLen
= 0; // number of decoded parity bytes
279 Uart
.shiftReg
= 0; // shiftreg to hold decoded data bits
280 Uart
.parityBits
= 0; // holds 8 parity bits
283 static void UartInit(uint8_t *data
, uint8_t *parity
)
286 Uart
.parity
= parity
;
287 Uart
.fourBits
= 0x00000000; // clear the buffer for 4 Bits
293 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
294 static RAMFUNC
bool MillerDecoding(uint8_t bit
, uint32_t non_real_time
)
297 Uart
.fourBits
= (Uart
.fourBits
<< 8) | bit
;
299 if (Uart
.state
== STATE_UNSYNCD
) { // not yet synced
301 Uart
.syncBit
= 9999; // not set
302 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
303 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
304 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
305 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
306 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
307 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
308 if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 0)) == ISO14443A_STARTBIT_PATTERN
>> 0) Uart
.syncBit
= 7;
309 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 1)) == ISO14443A_STARTBIT_PATTERN
>> 1) Uart
.syncBit
= 6;
310 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 2)) == ISO14443A_STARTBIT_PATTERN
>> 2) Uart
.syncBit
= 5;
311 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 3)) == ISO14443A_STARTBIT_PATTERN
>> 3) Uart
.syncBit
= 4;
312 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 4)) == ISO14443A_STARTBIT_PATTERN
>> 4) Uart
.syncBit
= 3;
313 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 5)) == ISO14443A_STARTBIT_PATTERN
>> 5) Uart
.syncBit
= 2;
314 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 6)) == ISO14443A_STARTBIT_PATTERN
>> 6) Uart
.syncBit
= 1;
315 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 7)) == ISO14443A_STARTBIT_PATTERN
>> 7) Uart
.syncBit
= 0;
317 if (Uart
.syncBit
!= 9999) { // found a sync bit
318 Uart
.startTime
= non_real_time
?non_real_time
:(GetCountSspClk() & 0xfffffff8);
319 Uart
.startTime
-= Uart
.syncBit
;
320 Uart
.endTime
= Uart
.startTime
;
321 Uart
.state
= STATE_START_OF_COMMUNICATION
;
327 if (IsMillerModulationNibble1(Uart
.fourBits
>> Uart
.syncBit
)) {
328 if (IsMillerModulationNibble2(Uart
.fourBits
>> Uart
.syncBit
)) { // Modulation in both halves - error
331 } else { // Modulation in first half = Sequence Z = logic "0"
332 if (Uart
.state
== STATE_MILLER_X
) { // error - must not follow after X
337 Uart
.shiftReg
= (Uart
.shiftReg
>> 1); // add a 0 to the shiftreg
338 Uart
.state
= STATE_MILLER_Z
;
339 Uart
.endTime
= Uart
.startTime
+ 8*(9*Uart
.len
+ Uart
.bitCount
+ 1) - 6;
340 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
341 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
342 Uart
.parityBits
<<= 1; // make room for the parity bit
343 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
346 if((Uart
.len
&0x0007) == 0) { // every 8 data bytes
347 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
354 if (IsMillerModulationNibble2(Uart
.fourBits
>> Uart
.syncBit
)) { // Modulation second half = Sequence X = logic "1"
356 Uart
.shiftReg
= (Uart
.shiftReg
>> 1) | 0x100; // add a 1 to the shiftreg
357 Uart
.state
= STATE_MILLER_X
;
358 Uart
.endTime
= Uart
.startTime
+ 8*(9*Uart
.len
+ Uart
.bitCount
+ 1) - 2;
359 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
360 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
361 Uart
.parityBits
<<= 1; // make room for the new parity bit
362 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
365 if ((Uart
.len
&0x0007) == 0) { // every 8 data bytes
366 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
370 } else { // no modulation in both halves - Sequence Y
371 if (Uart
.state
== STATE_MILLER_Z
|| Uart
.state
== STATE_MILLER_Y
) { // Y after logic "0" - End of Communication
373 Uart
.state
= STATE_UNSYNCD
;
374 Uart
.bitCount
--; // last "0" was part of EOC sequence
375 Uart
.shiftReg
<<= 1; // drop it
376 if(Uart
.bitCount
> 0) { // if we decoded some bits
377 Uart
.shiftReg
>>= (9 - Uart
.bitCount
); // right align them
378 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff); // add last byte to the output
379 Uart
.parityBits
<<= 1; // add a (void) parity bit
380 Uart
.parityBits
<<= (8 - (Uart
.len
&0x0007)); // left align parity bits
381 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // and store it
383 } else if (Uart
.len
& 0x0007) { // there are some parity bits to store
384 Uart
.parityBits
<<= (8 - (Uart
.len
&0x0007)); // left align remaining parity bits
385 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // and store them
388 return true; // we are finished with decoding the raw data sequence
390 UartReset(); // Nothing received - start over
393 if (Uart
.state
== STATE_START_OF_COMMUNICATION
) { // error - must not follow directly after SOC
396 } else { // a logic "0"
398 Uart
.shiftReg
= (Uart
.shiftReg
>> 1); // add a 0 to the shiftreg
399 Uart
.state
= STATE_MILLER_Y
;
400 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
401 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
402 Uart
.parityBits
<<= 1; // make room for the parity bit
403 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
406 if ((Uart
.len
&0x0007) == 0) { // every 8 data bytes
407 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
417 return false; // not finished yet, need more data
422 //=============================================================================
423 // ISO 14443 Type A - Manchester decoder
424 //=============================================================================
426 // This decoder is used when the PM3 acts as a reader.
427 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
428 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
429 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
430 // The Manchester decoder needs to identify the following sequences:
431 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
432 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
433 // 8 ticks unmodulated: Sequence F = end of communication
434 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
435 // Note 1: the bitstream may start at any time. We therefore need to sync.
436 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
439 // Lookup-Table to decide if 4 raw bits are a modulation.
440 // We accept three or four "1" in any position
441 const bool Mod_Manchester_LUT
[] = {
442 false, false, false, false, false, false, false, true,
443 false, false, false, true, false, true, true, true
446 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
447 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
450 static void DemodReset()
452 Demod
.state
= DEMOD_UNSYNCD
;
453 Demod
.len
= 0; // number of decoded data bytes
455 Demod
.shiftReg
= 0; // shiftreg to hold decoded data bits
456 Demod
.parityBits
= 0; //
457 Demod
.collisionPos
= 0; // Position of collision bit
458 Demod
.twoBits
= 0xffff; // buffer for 2 Bits
464 static void DemodInit(uint8_t *data
, uint8_t *parity
)
467 Demod
.parity
= parity
;
471 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
472 static RAMFUNC
int ManchesterDecoding(uint8_t bit
, uint16_t offset
, uint32_t non_real_time
)
475 Demod
.twoBits
= (Demod
.twoBits
<< 8) | bit
;
477 if (Demod
.state
== DEMOD_UNSYNCD
) {
479 if (Demod
.highCnt
< 2) { // wait for a stable unmodulated signal
480 if (Demod
.twoBits
== 0x0000) {
486 Demod
.syncBit
= 0xFFFF; // not set
487 if ((Demod
.twoBits
& 0x7700) == 0x7000) Demod
.syncBit
= 7;
488 else if ((Demod
.twoBits
& 0x3B80) == 0x3800) Demod
.syncBit
= 6;
489 else if ((Demod
.twoBits
& 0x1DC0) == 0x1C00) Demod
.syncBit
= 5;
490 else if ((Demod
.twoBits
& 0x0EE0) == 0x0E00) Demod
.syncBit
= 4;
491 else if ((Demod
.twoBits
& 0x0770) == 0x0700) Demod
.syncBit
= 3;
492 else if ((Demod
.twoBits
& 0x03B8) == 0x0380) Demod
.syncBit
= 2;
493 else if ((Demod
.twoBits
& 0x01DC) == 0x01C0) Demod
.syncBit
= 1;
494 else if ((Demod
.twoBits
& 0x00EE) == 0x00E0) Demod
.syncBit
= 0;
495 if (Demod
.syncBit
!= 0xFFFF) {
496 Demod
.startTime
= non_real_time
?non_real_time
:(GetCountSspClk() & 0xfffffff8);
497 Demod
.startTime
-= Demod
.syncBit
;
498 Demod
.bitCount
= offset
; // number of decoded data bits
499 Demod
.state
= DEMOD_MANCHESTER_DATA
;
506 if (IsManchesterModulationNibble1(Demod
.twoBits
>> Demod
.syncBit
)) { // modulation in first half
507 if (IsManchesterModulationNibble2(Demod
.twoBits
>> Demod
.syncBit
)) { // ... and in second half = collision
508 if (!Demod
.collisionPos
) {
509 Demod
.collisionPos
= (Demod
.len
<< 3) + Demod
.bitCount
;
511 } // modulation in first half only - Sequence D = 1
513 Demod
.shiftReg
= (Demod
.shiftReg
>> 1) | 0x100; // in both cases, add a 1 to the shiftreg
514 if(Demod
.bitCount
== 9) { // if we decoded a full byte (including parity)
515 Demod
.output
[Demod
.len
++] = (Demod
.shiftReg
& 0xff);
516 Demod
.parityBits
<<= 1; // make room for the parity bit
517 Demod
.parityBits
|= ((Demod
.shiftReg
>> 8) & 0x01); // store parity bit
520 if((Demod
.len
&0x0007) == 0) { // every 8 data bytes
521 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // store 8 parity bits
522 Demod
.parityBits
= 0;
525 Demod
.endTime
= Demod
.startTime
+ 8*(9*Demod
.len
+ Demod
.bitCount
+ 1) - 4;
526 } else { // no modulation in first half
527 if (IsManchesterModulationNibble2(Demod
.twoBits
>> Demod
.syncBit
)) { // and modulation in second half = Sequence E = 0
529 Demod
.shiftReg
= (Demod
.shiftReg
>> 1); // add a 0 to the shiftreg
530 if(Demod
.bitCount
>= 9) { // if we decoded a full byte (including parity)
531 Demod
.output
[Demod
.len
++] = (Demod
.shiftReg
& 0xff);
532 Demod
.parityBits
<<= 1; // make room for the new parity bit
533 Demod
.parityBits
|= ((Demod
.shiftReg
>> 8) & 0x01); // store parity bit
536 if ((Demod
.len
&0x0007) == 0) { // every 8 data bytes
537 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // store 8 parity bits1
538 Demod
.parityBits
= 0;
541 Demod
.endTime
= Demod
.startTime
+ 8*(9*Demod
.len
+ Demod
.bitCount
+ 1);
542 } else { // no modulation in both halves - End of communication
544 if(Demod
.bitCount
> 0) { // there are some remaining data bits
545 Demod
.shiftReg
>>= (9 - Demod
.bitCount
); // right align the decoded bits
546 Demod
.output
[Demod
.len
++] = Demod
.shiftReg
& 0xff; // and add them to the output
547 Demod
.parityBits
<<= 1; // add a (void) parity bit
548 Demod
.parityBits
<<= (8 - (Demod
.len
&0x0007)); // left align remaining parity bits
549 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // and store them
551 } else if (Demod
.len
& 0x0007) { // there are some parity bits to store
552 Demod
.parityBits
<<= (8 - (Demod
.len
&0x0007)); // left align remaining parity bits
553 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // and store them
556 return true; // we are finished with decoding the raw data sequence
557 } else { // nothing received. Start over
565 return false; // not finished yet, need more data
568 //=============================================================================
569 // Finally, a `sniffer' for ISO 14443 Type A
570 // Both sides of communication!
571 //=============================================================================
573 //-----------------------------------------------------------------------------
574 // Record the sequence of commands sent by the reader to the tag, with
575 // triggering so that we start recording at the point that the tag is moved
577 //-----------------------------------------------------------------------------
578 void RAMFUNC
SnoopIso14443a(uint8_t param
) {
580 // bit 0 - trigger from first card answer
581 // bit 1 - trigger from first reader 7-bit request
586 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER
);
588 // Allocate memory from BigBuf for some buffers
589 // free all previous allocations first
592 // The command (reader -> tag) that we're receiving.
593 uint8_t *receivedCmd
= BigBuf_malloc(MAX_FRAME_SIZE
);
594 uint8_t *receivedCmdPar
= BigBuf_malloc(MAX_PARITY_SIZE
);
596 // The response (tag -> reader) that we're receiving.
597 uint8_t *receivedResponse
= BigBuf_malloc(MAX_FRAME_SIZE
);
598 uint8_t *receivedResponsePar
= BigBuf_malloc(MAX_PARITY_SIZE
);
600 // The DMA buffer, used to stream samples from the FPGA
601 uint8_t *dmaBuf
= BigBuf_malloc(DMA_BUFFER_SIZE
);
607 uint8_t *data
= dmaBuf
;
608 uint8_t previous_data
= 0;
611 bool TagIsActive
= false;
612 bool ReaderIsActive
= false;
614 // Set up the demodulator for tag -> reader responses.
615 DemodInit(receivedResponse
, receivedResponsePar
);
617 // Set up the demodulator for the reader -> tag commands
618 UartInit(receivedCmd
, receivedCmdPar
);
620 // Setup and start DMA.
621 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
);
623 // We won't start recording the frames that we acquire until we trigger;
624 // a good trigger condition to get started is probably when we see a
625 // response from the tag.
626 // triggered == false -- to wait first for card
627 bool triggered
= !(param
& 0x03);
629 // And now we loop, receiving samples.
630 for (uint32_t rsamples
= 0; true; ) {
632 if (BUTTON_PRESS()) {
633 DbpString("cancelled by button");
639 int register readBufDataP
= data
- dmaBuf
;
640 int register dmaBufDataP
= DMA_BUFFER_SIZE
- AT91C_BASE_PDC_SSC
->PDC_RCR
;
641 if (readBufDataP
<= dmaBufDataP
){
642 dataLen
= dmaBufDataP
- readBufDataP
;
644 dataLen
= DMA_BUFFER_SIZE
- readBufDataP
+ dmaBufDataP
;
646 // test for length of buffer
647 if(dataLen
> maxDataLen
) {
648 maxDataLen
= dataLen
;
649 if(dataLen
> (9 * DMA_BUFFER_SIZE
/ 10)) {
650 Dbprintf("blew circular buffer! dataLen=%d", dataLen
);
654 if(dataLen
< 1) continue;
656 // primary buffer was stopped( <-- we lost data!
657 if (!AT91C_BASE_PDC_SSC
->PDC_RCR
) {
658 AT91C_BASE_PDC_SSC
->PDC_RPR
= (uint32_t) dmaBuf
;
659 AT91C_BASE_PDC_SSC
->PDC_RCR
= DMA_BUFFER_SIZE
;
660 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen
); // temporary
662 // secondary buffer sets as primary, secondary buffer was stopped
663 if (!AT91C_BASE_PDC_SSC
->PDC_RNCR
) {
664 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
;
665 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
668 if (rsamples
& 0x01) { // Need two samples to feed Miller and Manchester-Decoder
670 if(!TagIsActive
) { // no need to try decoding reader data if the tag is sending
671 uint8_t readerdata
= (previous_data
& 0xF0) | (*data
>> 4);
672 if (MillerDecoding(readerdata
, (rsamples
-1)*4)) {
673 // check - if there is a short 7bit request from reader
674 if ((!triggered
) && (param
& 0x02) && (Uart
.len
== 1) && (Uart
.bitCount
== 7)) {
678 if (!LogTrace(receivedCmd
,
680 Uart
.startTime
*16 - DELAY_READER_AIR2ARM_AS_SNIFFER
,
681 Uart
.endTime
*16 - DELAY_READER_AIR2ARM_AS_SNIFFER
,
685 /* And ready to receive another command. */
687 /* And also reset the demod code, which might have been */
688 /* false-triggered by the commands from the reader. */
691 ReaderIsActive
= (Uart
.state
!= STATE_UNSYNCD
);
694 if (!ReaderIsActive
) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
695 uint8_t tagdata
= (previous_data
<< 4) | (*data
& 0x0F);
696 if (ManchesterDecoding(tagdata
, 0, (rsamples
-1)*4)) {
697 if (!LogTrace(receivedResponse
,
699 Demod
.startTime
*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER
,
700 Demod
.endTime
*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER
,
703 if ((!triggered
) && (param
& 0x01)) triggered
= true;
704 // And ready to receive another response.
706 // And reset the Miller decoder including itS (now outdated) input buffer
707 UartInit(receivedCmd
, receivedCmdPar
);
709 TagIsActive
= (Demod
.state
!= DEMOD_UNSYNCD
);
713 previous_data
= *data
;
716 if(data
== dmaBuf
+ DMA_BUFFER_SIZE
) {
724 DbpString("COMMAND FINISHED");
725 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen
, Uart
.state
, Uart
.len
);
726 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart
.output
[0]);
729 //-----------------------------------------------------------------------------
730 // Prepare tag messages
731 //-----------------------------------------------------------------------------
732 static void CodeIso14443aAsTagPar(const uint8_t *cmd
, uint16_t len
, uint8_t *parity
)
736 // Correction bit, might be removed when not needed
741 ToSendStuffBit(1); // 1
747 ToSend
[++ToSendMax
] = SEC_D
;
748 LastProxToAirDuration
= 8 * ToSendMax
- 4;
750 for (uint16_t i
= 0; i
< len
; i
++) {
754 for (uint16_t j
= 0; j
< 8; j
++) {
756 ToSend
[++ToSendMax
] = SEC_D
;
758 ToSend
[++ToSendMax
] = SEC_E
;
763 // Get the parity bit
764 if (parity
[i
>>3] & (0x80>>(i
&0x0007))) {
765 ToSend
[++ToSendMax
] = SEC_D
;
766 LastProxToAirDuration
= 8 * ToSendMax
- 4;
768 ToSend
[++ToSendMax
] = SEC_E
;
769 LastProxToAirDuration
= 8 * ToSendMax
;
774 ToSend
[++ToSendMax
] = SEC_F
;
776 // Convert from last byte pos to length
781 static void Code4bitAnswerAsTag(uint8_t cmd
)
787 // Correction bit, might be removed when not needed
792 ToSendStuffBit(1); // 1
798 ToSend
[++ToSendMax
] = SEC_D
;
801 for (i
= 0; i
< 4; i
++) {
803 ToSend
[++ToSendMax
] = SEC_D
;
804 LastProxToAirDuration
= 8 * ToSendMax
- 4;
806 ToSend
[++ToSendMax
] = SEC_E
;
807 LastProxToAirDuration
= 8 * ToSendMax
;
813 ToSend
[++ToSendMax
] = SEC_F
;
815 // Convert from last byte pos to length
820 static uint8_t *LastReaderTraceTime
= NULL
;
822 static void EmLogTraceReader(void) {
823 // remember last reader trace start to fix timing info later
824 LastReaderTraceTime
= BigBuf_get_addr() + BigBuf_get_traceLen();
825 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, true);
829 static void FixLastReaderTraceTime(uint32_t tag_StartTime
) {
830 uint32_t reader_EndTime
= Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
;
831 uint32_t reader_StartTime
= Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
;
832 uint16_t reader_modlen
= reader_EndTime
- reader_StartTime
;
833 uint16_t approx_fdt
= tag_StartTime
- reader_EndTime
;
834 uint16_t exact_fdt
= (approx_fdt
- 20 + 32)/64 * 64 + 20;
835 reader_StartTime
= tag_StartTime
- exact_fdt
- reader_modlen
;
836 LastReaderTraceTime
[0] = (reader_StartTime
>> 0) & 0xff;
837 LastReaderTraceTime
[1] = (reader_StartTime
>> 8) & 0xff;
838 LastReaderTraceTime
[2] = (reader_StartTime
>> 16) & 0xff;
839 LastReaderTraceTime
[3] = (reader_StartTime
>> 24) & 0xff;
843 static void EmLogTraceTag(uint8_t *tag_data
, uint16_t tag_len
, uint8_t *tag_Parity
, uint32_t ProxToAirDuration
) {
844 uint32_t tag_StartTime
= LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_TAG
;
845 uint32_t tag_EndTime
= (LastTimeProxToAirStart
+ ProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_TAG
;
846 LogTrace(tag_data
, tag_len
, tag_StartTime
, tag_EndTime
, tag_Parity
, false);
847 FixLastReaderTraceTime(tag_StartTime
);
851 //-----------------------------------------------------------------------------
852 // Wait for commands from reader
853 // Stop when button is pressed
854 // Or return true when command is captured
855 //-----------------------------------------------------------------------------
856 static int GetIso14443aCommandFromReader(uint8_t *received
, uint8_t *parity
, int *len
)
858 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
859 // only, since we are receiving, not transmitting).
860 // Signal field is off with the appropriate LED
862 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
864 // Now run a `software UART' on the stream of incoming samples.
865 UartInit(received
, parity
);
868 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
873 if(BUTTON_PRESS()) return false;
875 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
876 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
877 if(MillerDecoding(b
, 0)) {
887 int EmSend4bit(uint8_t resp
);
888 static int EmSendCmdExPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
);
889 int EmSendCmd(uint8_t *resp
, uint16_t respLen
);
890 int EmSendPrecompiledCmd(tag_response_info_t
*response_info
);
893 static bool prepare_tag_modulation(tag_response_info_t
* response_info
, size_t max_buffer_size
) {
894 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
895 // This will need the following byte array for a modulation sequence
896 // 144 data bits (18 * 8)
899 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
900 // 1 just for the case
902 // 166 bytes, since every bit that needs to be send costs us a byte
906 // Prepare the tag modulation bits from the message
907 GetParity(response_info
->response
, response_info
->response_n
, &(response_info
->par
));
908 CodeIso14443aAsTagPar(response_info
->response
,response_info
->response_n
, &(response_info
->par
));
910 // Make sure we do not exceed the free buffer space
911 if (ToSendMax
> max_buffer_size
) {
912 Dbprintf("Out of memory, when modulating bits for tag answer:");
913 Dbhexdump(response_info
->response_n
, response_info
->response
, false);
917 // Copy the byte array, used for this modulation to the buffer position
918 memcpy(response_info
->modulation
, ToSend
, ToSendMax
);
920 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
921 response_info
->modulation_n
= ToSendMax
;
922 response_info
->ProxToAirDuration
= LastProxToAirDuration
;
928 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
929 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
930 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits for the modulation
931 // -> need 273 bytes buffer
932 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
934 bool prepare_allocated_tag_modulation(tag_response_info_t
* response_info
, uint8_t **buffer
, size_t *max_buffer_size
) {
936 // Retrieve and store the current buffer index
937 response_info
->modulation
= *buffer
;
939 // Forward the prepare tag modulation function to the inner function
940 if (prepare_tag_modulation(response_info
, *max_buffer_size
)) {
941 // Update the free buffer offset and the remaining buffer size
942 *buffer
+= ToSendMax
;
943 *max_buffer_size
-= ToSendMax
;
950 //-----------------------------------------------------------------------------
951 // Main loop of simulated tag: receive commands from reader, decide what
952 // response to send, and send it.
953 //-----------------------------------------------------------------------------
954 void SimulateIso14443aTag(int tagType
, int uid_1st
, int uid_2nd
, byte_t
* data
)
958 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
959 uint8_t response1
[2];
962 case 1: { // MIFARE Classic
963 // Says: I am Mifare 1k - original line
968 case 2: { // MIFARE Ultralight
969 // Says: I am a stupid memory tag, no crypto
974 case 3: { // MIFARE DESFire
975 // Says: I am a DESFire tag, ph33r me
980 case 4: { // ISO/IEC 14443-4
981 // Says: I am a javacard (JCOP)
986 case 5: { // MIFARE TNP3XXX
993 Dbprintf("Error: unkown tagtype (%d)",tagType
);
998 // The second response contains the (mandatory) first 24 bits of the UID
999 uint8_t response2
[5] = {0x00};
1001 // Check if the uid uses the (optional) part
1002 uint8_t response2a
[5] = {0x00};
1005 response2
[0] = 0x88;
1006 num_to_bytes(uid_1st
,3,response2
+1);
1007 num_to_bytes(uid_2nd
,4,response2a
);
1008 response2a
[4] = response2a
[0] ^ response2a
[1] ^ response2a
[2] ^ response2a
[3];
1010 // Configure the ATQA and SAK accordingly
1011 response1
[0] |= 0x40;
1014 num_to_bytes(uid_1st
,4,response2
);
1015 // Configure the ATQA and SAK accordingly
1016 response1
[0] &= 0xBF;
1020 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1021 response2
[4] = response2
[0] ^ response2
[1] ^ response2
[2] ^ response2
[3];
1023 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1024 uint8_t response3
[3] = {0x00};
1026 ComputeCrc14443(CRC_14443_A
, response3
, 1, &response3
[1], &response3
[2]);
1028 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1029 uint8_t response3a
[3] = {0x00};
1030 response3a
[0] = sak
& 0xFB;
1031 ComputeCrc14443(CRC_14443_A
, response3a
, 1, &response3a
[1], &response3a
[2]);
1033 uint8_t response5
[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1034 uint8_t response6
[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1035 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1036 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1037 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1038 // TC(1) = 0x02: CID supported, NAD not supported
1039 ComputeCrc14443(CRC_14443_A
, response6
, 4, &response6
[4], &response6
[5]);
1041 #define TAG_RESPONSE_COUNT 7
1042 tag_response_info_t responses
[TAG_RESPONSE_COUNT
] = {
1043 { .response
= response1
, .response_n
= sizeof(response1
) }, // Answer to request - respond with card type
1044 { .response
= response2
, .response_n
= sizeof(response2
) }, // Anticollision cascade1 - respond with uid
1045 { .response
= response2a
, .response_n
= sizeof(response2a
) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1046 { .response
= response3
, .response_n
= sizeof(response3
) }, // Acknowledge select - cascade 1
1047 { .response
= response3a
, .response_n
= sizeof(response3a
) }, // Acknowledge select - cascade 2
1048 { .response
= response5
, .response_n
= sizeof(response5
) }, // Authentication answer (random nonce)
1049 { .response
= response6
, .response_n
= sizeof(response6
) }, // dummy ATS (pseudo-ATR), answer to RATS
1052 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1053 // Such a response is less time critical, so we can prepare them on the fly
1054 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1055 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1056 uint8_t dynamic_response_buffer
[DYNAMIC_RESPONSE_BUFFER_SIZE
];
1057 uint8_t dynamic_modulation_buffer
[DYNAMIC_MODULATION_BUFFER_SIZE
];
1058 tag_response_info_t dynamic_response_info
= {
1059 .response
= dynamic_response_buffer
,
1061 .modulation
= dynamic_modulation_buffer
,
1065 // We need to listen to the high-frequency, peak-detected path.
1066 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
1068 BigBuf_free_keep_EM();
1070 // allocate buffers:
1071 uint8_t *receivedCmd
= BigBuf_malloc(MAX_FRAME_SIZE
);
1072 uint8_t *receivedCmdPar
= BigBuf_malloc(MAX_PARITY_SIZE
);
1073 uint8_t *free_buffer_pointer
= BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE
);
1074 size_t free_buffer_size
= ALLOCATED_TAG_MODULATION_BUFFER_SIZE
;
1079 // Prepare the responses of the anticollision phase
1080 // there will be not enough time to do this at the moment the reader sends it REQA
1081 for (size_t i
=0; i
<TAG_RESPONSE_COUNT
; i
++) {
1082 prepare_allocated_tag_modulation(&responses
[i
], &free_buffer_pointer
, &free_buffer_size
);
1087 // To control where we are in the protocol
1091 // Just to allow some checks
1097 tag_response_info_t
* p_response
;
1101 // Clean receive command buffer
1102 if(!GetIso14443aCommandFromReader(receivedCmd
, receivedCmdPar
, &len
)) {
1103 DbpString("Button press");
1109 // Okay, look at the command now.
1111 if(receivedCmd
[0] == 0x26) { // Received a REQUEST
1112 p_response
= &responses
[0]; order
= 1;
1113 } else if(receivedCmd
[0] == 0x52) { // Received a WAKEUP
1114 p_response
= &responses
[0]; order
= 6;
1115 } else if(receivedCmd
[1] == 0x20 && receivedCmd
[0] == 0x93) { // Received request for UID (cascade 1)
1116 p_response
= &responses
[1]; order
= 2;
1117 } else if(receivedCmd
[1] == 0x20 && receivedCmd
[0] == 0x95) { // Received request for UID (cascade 2)
1118 p_response
= &responses
[2]; order
= 20;
1119 } else if(receivedCmd
[1] == 0x70 && receivedCmd
[0] == 0x93) { // Received a SELECT (cascade 1)
1120 p_response
= &responses
[3]; order
= 3;
1121 } else if(receivedCmd
[1] == 0x70 && receivedCmd
[0] == 0x95) { // Received a SELECT (cascade 2)
1122 p_response
= &responses
[4]; order
= 30;
1123 } else if(receivedCmd
[0] == 0x30) { // Received a (plain) READ
1124 EmSendCmd(data
+(4*receivedCmd
[1]),16);
1125 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1126 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1128 } else if(receivedCmd
[0] == 0x50) { // Received a HALT
1130 } else if(receivedCmd
[0] == 0x60 || receivedCmd
[0] == 0x61) { // Received an authentication request
1131 p_response
= &responses
[5]; order
= 7;
1132 } else if(receivedCmd
[0] == 0xE0) { // Received a RATS request
1133 if (tagType
== 1 || tagType
== 2) { // RATS not supported
1134 EmSend4bit(CARD_NACK_NA
);
1137 p_response
= &responses
[6]; order
= 70;
1139 } else if (order
== 7 && len
== 8) { // Received {nr] and {ar} (part of authentication)
1140 uint32_t nr
= bytes_to_num(receivedCmd
,4);
1141 uint32_t ar
= bytes_to_num(receivedCmd
+4,4);
1142 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr
,ar
);
1144 // Check for ISO 14443A-4 compliant commands, look at left nibble
1145 switch (receivedCmd
[0]) {
1148 case 0x0A: { // IBlock (command)
1149 dynamic_response_info
.response
[0] = receivedCmd
[0];
1150 dynamic_response_info
.response
[1] = 0x00;
1151 dynamic_response_info
.response
[2] = 0x90;
1152 dynamic_response_info
.response
[3] = 0x00;
1153 dynamic_response_info
.response_n
= 4;
1157 case 0x1B: { // Chaining command
1158 dynamic_response_info
.response
[0] = 0xaa | ((receivedCmd
[0]) & 1);
1159 dynamic_response_info
.response_n
= 2;
1164 dynamic_response_info
.response
[0] = receivedCmd
[0] ^ 0x11;
1165 dynamic_response_info
.response_n
= 2;
1169 memcpy(dynamic_response_info
.response
,"\xAB\x00",2);
1170 dynamic_response_info
.response_n
= 2;
1174 case 0xC2: { // Readers sends deselect command
1175 memcpy(dynamic_response_info
.response
,"\xCA\x00",2);
1176 dynamic_response_info
.response_n
= 2;
1180 // Never seen this command before
1181 Dbprintf("Received unknown command (len=%d):",len
);
1182 Dbhexdump(len
,receivedCmd
,false);
1184 dynamic_response_info
.response_n
= 0;
1188 if (dynamic_response_info
.response_n
> 0) {
1189 // Copy the CID from the reader query
1190 dynamic_response_info
.response
[1] = receivedCmd
[1];
1192 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1193 AppendCrc14443a(dynamic_response_info
.response
,dynamic_response_info
.response_n
);
1194 dynamic_response_info
.response_n
+= 2;
1196 if (prepare_tag_modulation(&dynamic_response_info
,DYNAMIC_MODULATION_BUFFER_SIZE
) == false) {
1197 Dbprintf("Error preparing tag response");
1200 p_response
= &dynamic_response_info
;
1204 // Count number of wakeups received after a halt
1205 if(order
== 6 && lastorder
== 5) { happened
++; }
1207 // Count number of other messages after a halt
1208 if(order
!= 6 && lastorder
== 5) { happened2
++; }
1210 if(cmdsRecvd
> 999) {
1211 DbpString("1000 commands later...");
1216 if (p_response
!= NULL
) {
1217 EmSendPrecompiledCmd(p_response
);
1220 if (!get_tracing()) {
1221 Dbprintf("Trace Full. Simulation stopped.");
1226 Dbprintf("%x %x %x", happened
, happened2
, cmdsRecvd
);
1228 BigBuf_free_keep_EM();
1232 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1233 // of bits specified in the delay parameter.
1234 static void PrepareDelayedTransfer(uint16_t delay
)
1236 uint8_t bitmask
= 0;
1237 uint8_t bits_to_shift
= 0;
1238 uint8_t bits_shifted
= 0;
1242 for (uint16_t i
= 0; i
< delay
; i
++) {
1243 bitmask
|= (0x01 << i
);
1245 ToSend
[ToSendMax
++] = 0x00;
1246 for (uint16_t i
= 0; i
< ToSendMax
; i
++) {
1247 bits_to_shift
= ToSend
[i
] & bitmask
;
1248 ToSend
[i
] = ToSend
[i
] >> delay
;
1249 ToSend
[i
] = ToSend
[i
] | (bits_shifted
<< (8 - delay
));
1250 bits_shifted
= bits_to_shift
;
1256 //-------------------------------------------------------------------------------------
1257 // Transmit the command (to the tag) that was placed in ToSend[].
1258 // Parameter timing:
1259 // if NULL: transfer at next possible time, taking into account
1260 // request guard time, startup frame guard time and frame delay time
1261 // if == 0: transfer immediately and return time of transfer
1262 // if != 0: delay transfer until time specified
1263 //-------------------------------------------------------------------------------------
1264 static void TransmitFor14443a(const uint8_t *cmd
, uint16_t len
, uint32_t *timing
)
1268 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_READER_MOD
);
1270 uint32_t ThisTransferTime
= 0;
1273 if(*timing
== 0) { // Measure time
1274 *timing
= (GetCountSspClk() + 8) & 0xfffffff8;
1276 PrepareDelayedTransfer(*timing
& 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1278 if(MF_DBGLEVEL
>= 4 && GetCountSspClk() >= (*timing
& 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1279 while (GetCountSspClk() < (*timing
& 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1280 LastTimeProxToAirStart
= *timing
;
1282 ThisTransferTime
= ((MAX(NextTransferTime
, GetCountSspClk()) & 0xfffffff8) + 8);
1283 while (GetCountSspClk() < ThisTransferTime
);
1284 LastTimeProxToAirStart
= ThisTransferTime
;
1288 AT91C_BASE_SSC
->SSC_THR
= SEC_Y
;
1292 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1293 AT91C_BASE_SSC
->SSC_THR
= cmd
[c
];
1301 NextTransferTime
= MAX(NextTransferTime
, LastTimeProxToAirStart
+ REQUEST_GUARD_TIME
);
1306 //-----------------------------------------------------------------------------
1307 // Prepare reader command (in bits, support short frames) to send to FPGA
1308 //-----------------------------------------------------------------------------
1309 static void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd
, uint16_t bits
, const uint8_t *parity
)
1317 // Start of Communication (Seq. Z)
1318 ToSend
[++ToSendMax
] = SEC_Z
;
1319 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1322 size_t bytecount
= nbytes(bits
);
1323 // Generate send structure for the data bits
1324 for (i
= 0; i
< bytecount
; i
++) {
1325 // Get the current byte to send
1327 size_t bitsleft
= MIN((bits
-(i
*8)),8);
1329 for (j
= 0; j
< bitsleft
; j
++) {
1332 ToSend
[++ToSendMax
] = SEC_X
;
1333 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 2;
1338 ToSend
[++ToSendMax
] = SEC_Z
;
1339 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1342 ToSend
[++ToSendMax
] = SEC_Y
;
1349 // Only transmit parity bit if we transmitted a complete byte
1350 if (j
== 8 && parity
!= NULL
) {
1351 // Get the parity bit
1352 if (parity
[i
>>3] & (0x80 >> (i
&0x0007))) {
1354 ToSend
[++ToSendMax
] = SEC_X
;
1355 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 2;
1360 ToSend
[++ToSendMax
] = SEC_Z
;
1361 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1364 ToSend
[++ToSendMax
] = SEC_Y
;
1371 // End of Communication: Logic 0 followed by Sequence Y
1374 ToSend
[++ToSendMax
] = SEC_Z
;
1375 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1378 ToSend
[++ToSendMax
] = SEC_Y
;
1381 ToSend
[++ToSendMax
] = SEC_Y
;
1383 // Convert to length of command:
1388 //-----------------------------------------------------------------------------
1389 // Wait for commands from reader
1390 // Stop when button is pressed (return 1) or field was gone (return 2)
1391 // Or return 0 when command is captured
1392 //-----------------------------------------------------------------------------
1393 int EmGetCmd(uint8_t *received
, uint16_t *len
, uint8_t *parity
)
1395 uint32_t field_off_time
= -1;
1396 uint32_t samples
= 0;
1399 uint8_t dmaBuf
[DMA_BUFFER_SIZE
];
1400 uint8_t *upTo
= dmaBuf
;
1404 // Run a 'software UART' on the stream of incoming samples.
1405 UartInit(received
, parity
);
1408 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_START
;
1410 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN
1411 while (GetCountSspClk() < LastTimeProxToAirStart
+ LastProxToAirDuration
+ (FpgaSendQueueDelay
>>3) - 8 - 3) /* wait */ ;
1413 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1414 // only, since we are receiving, not transmitting).
1415 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
1417 // clear receive register, measure time of next transfer
1418 uint32_t temp
= AT91C_BASE_SSC
->SSC_RHR
; (void) temp
;
1419 while (!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
)) ;
1420 uint32_t start_time
= GetCountSspClk() & 0xfffffff8;
1422 // Setup and start DMA.
1423 FpgaSetupSscDma(dmaBuf
, DMA_BUFFER_SIZE
);
1426 uint16_t behindBy
= ((uint8_t*)AT91C_BASE_PDC_SSC
->PDC_RPR
- upTo
) & (DMA_BUFFER_SIZE
-1);
1428 if (behindBy
== 0) continue;
1432 if(upTo
>= dmaBuf
+ DMA_BUFFER_SIZE
) { // we have read all of the DMA buffer content.
1433 upTo
= dmaBuf
; // start reading the circular buffer from the beginning
1434 if(behindBy
> (9*DMA_BUFFER_SIZE
/10)) {
1435 Dbprintf("About to blow circular buffer - aborted! behindBy=%d", behindBy
);
1440 if (AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_ENDRX
)) { // DMA Counter Register had reached 0, already rotated.
1441 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
; // refresh the DMA Next Buffer and
1442 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
; // DMA Next Counter registers
1445 if (BUTTON_PRESS()) {
1450 // check reader's HF field
1451 if (AT91C_BASE_ADC
->ADC_SR
& ADC_END_OF_CONVERSION(ADC_CHAN_HF_LOW
)) {
1452 if ((MAX_ADC_HF_VOLTAGE_LOW
* AT91C_BASE_ADC
->ADC_CDR
[ADC_CHAN_HF_LOW
]) >> 10 < MF_MINFIELDV
) {
1453 if (GetTickCount() - field_off_time
> 50) {
1454 ret
= 2; // reader has switched off HF field for more than 50ms. Timeout
1458 field_off_time
= GetTickCount(); // HF field is still there. Reset timer
1460 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_START
; // restart ADC
1463 if (MillerDecoding(b
, start_time
+ samples
*8)) {
1473 FpgaDisableSscDma();
1478 static int EmSendCmd14443aRaw(uint8_t *resp
, uint16_t respLen
)
1484 bool correctionNeeded
;
1486 // Modulate Manchester
1487 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_MOD
);
1489 // include correction bit if necessary
1490 if (Uart
.bitCount
== 7)
1492 // Short tags (7 bits) don't have parity, determine the correct value from MSB
1493 correctionNeeded
= Uart
.output
[0] & 0x40;
1497 // Look at the last parity bit
1498 correctionNeeded
= Uart
.parity
[(Uart
.len
-1)/8] & (0x80 >> ((Uart
.len
-1) & 7));
1501 if (correctionNeeded
) {
1502 // 1236, so correction bit needed
1508 // clear receiving shift register and holding register
1509 b
= AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1510 while (!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1511 b
= AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1513 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1514 for (uint16_t j
= 0; j
< 5; j
++) { // allow timeout - better late than never
1515 while (!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1516 if (AT91C_BASE_SSC
->SSC_RHR
) break;
1519 LastTimeProxToAirStart
= (GetCountSspClk() & 0xfffffff8) + (correctionNeeded
?8:0);
1522 for (; i
< respLen
; ) {
1523 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1524 AT91C_BASE_SSC
->SSC_THR
= resp
[i
++];
1525 FpgaSendQueueDelay
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1528 if(BUTTON_PRESS()) {
1538 int EmSend4bit(uint8_t resp
){
1539 Code4bitAnswerAsTag(resp
);
1540 int res
= EmSendCmd14443aRaw(ToSend
, ToSendMax
);
1541 // Log this tag answer and fix timing of previous reader command:
1542 EmLogTraceTag(&resp
, 1, NULL
, LastProxToAirDuration
);
1547 static int EmSendCmdExPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
){
1548 CodeIso14443aAsTagPar(resp
, respLen
, par
);
1549 int res
= EmSendCmd14443aRaw(ToSend
, ToSendMax
);
1550 // Log this tag answer and fix timing of previous reader command:
1551 EmLogTraceTag(resp
, respLen
, par
, LastProxToAirDuration
);
1556 int EmSendCmd(uint8_t *resp
, uint16_t respLen
){
1557 uint8_t par
[MAX_PARITY_SIZE
];
1558 GetParity(resp
, respLen
, par
);
1559 return EmSendCmdExPar(resp
, respLen
, par
);
1563 int EmSendCmdPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
){
1564 return EmSendCmdExPar(resp
, respLen
, par
);
1568 int EmSendPrecompiledCmd(tag_response_info_t
*response_info
) {
1569 int ret
= EmSendCmd14443aRaw(response_info
->modulation
, response_info
->modulation_n
);
1570 // Log this tag answer and fix timing of previous reader command:
1571 EmLogTraceTag(response_info
->response
, response_info
->response_n
, &(response_info
->par
), response_info
->ProxToAirDuration
);
1576 //-----------------------------------------------------------------------------
1577 // Wait a certain time for tag response
1578 // If a response is captured return true
1579 // If it takes too long return false
1580 //-----------------------------------------------------------------------------
1581 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse
, uint8_t *receivedResponsePar
, uint16_t offset
)
1585 // Set FPGA mode to "reader listen mode", no modulation (listen
1586 // only, since we are receiving, not transmitting).
1587 // Signal field is on with the appropriate LED
1589 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_READER_LISTEN
);
1591 // Now get the answer from the card
1592 DemodInit(receivedResponse
, receivedResponsePar
);
1595 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1601 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1602 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1603 if(ManchesterDecoding(b
, offset
, 0)) {
1604 NextTransferTime
= MAX(NextTransferTime
, Demod
.endTime
- (DELAY_AIR2ARM_AS_READER
+ DELAY_ARM2AIR_AS_READER
)/16 + FRAME_DELAY_TIME_PICC_TO_PCD
);
1606 } else if (c
++ > iso14a_timeout
&& Demod
.state
== DEMOD_UNSYNCD
) {
1614 void ReaderTransmitBitsPar(uint8_t* frame
, uint16_t bits
, uint8_t *par
, uint32_t *timing
)
1616 CodeIso14443aBitsAsReaderPar(frame
, bits
, par
);
1618 // Send command to tag
1619 TransmitFor14443a(ToSend
, ToSendMax
, timing
);
1623 // Log reader command in trace buffer
1624 LogTrace(frame
, nbytes(bits
), LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_READER
, (LastTimeProxToAirStart
+ LastProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_READER
, par
, true);
1628 void ReaderTransmitPar(uint8_t* frame
, uint16_t len
, uint8_t *par
, uint32_t *timing
)
1630 ReaderTransmitBitsPar(frame
, len
*8, par
, timing
);
1634 static void ReaderTransmitBits(uint8_t* frame
, uint16_t len
, uint32_t *timing
)
1636 // Generate parity and redirect
1637 uint8_t par
[MAX_PARITY_SIZE
];
1638 GetParity(frame
, len
/8, par
);
1639 ReaderTransmitBitsPar(frame
, len
, par
, timing
);
1643 void ReaderTransmit(uint8_t* frame
, uint16_t len
, uint32_t *timing
)
1645 // Generate parity and redirect
1646 uint8_t par
[MAX_PARITY_SIZE
];
1647 GetParity(frame
, len
, par
);
1648 ReaderTransmitBitsPar(frame
, len
*8, par
, timing
);
1652 static int ReaderReceiveOffset(uint8_t* receivedAnswer
, uint16_t offset
, uint8_t *parity
)
1654 if (!GetIso14443aAnswerFromTag(receivedAnswer
, parity
, offset
)) return false;
1655 LogTrace(receivedAnswer
, Demod
.len
, Demod
.startTime
*16 - DELAY_AIR2ARM_AS_READER
, Demod
.endTime
*16 - DELAY_AIR2ARM_AS_READER
, parity
, false);
1660 int ReaderReceive(uint8_t *receivedAnswer
, uint8_t *parity
)
1662 if (!GetIso14443aAnswerFromTag(receivedAnswer
, parity
, 0)) return false;
1663 LogTrace(receivedAnswer
, Demod
.len
, Demod
.startTime
*16 - DELAY_AIR2ARM_AS_READER
, Demod
.endTime
*16 - DELAY_AIR2ARM_AS_READER
, parity
, false);
1668 static void iso14a_set_ATS_times(uint8_t *ats
) {
1674 if (ats
[0] > 1) { // there is a format byte T0
1675 if ((ats
[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
1676 if ((ats
[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
1681 fwi
= (tb1
& 0xf0) >> 4; // frame waiting time integer (FWI)
1683 fwt
= 256 * 16 * (1 << fwi
); // frame waiting time (FWT) in 1/fc
1684 iso14a_set_timeout(fwt
/(8*16));
1686 sfgi
= tb1
& 0x0f; // startup frame guard time integer (SFGI)
1687 if (sfgi
!= 0 && sfgi
!= 15) {
1688 sfgt
= 256 * 16 * (1 << sfgi
); // startup frame guard time (SFGT) in 1/fc
1689 NextTransferTime
= MAX(NextTransferTime
, Demod
.endTime
+ (sfgt
- DELAY_AIR2ARM_AS_READER
- DELAY_ARM2AIR_AS_READER
)/16);
1696 static int GetATQA(uint8_t *resp
, uint8_t *resp_par
) {
1698 #define WUPA_RETRY_TIMEOUT 10 // 10ms
1699 uint8_t wupa
[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1701 uint32_t save_iso14a_timeout
= iso14a_get_timeout();
1702 iso14a_set_timeout(1236/(16*8)+1); // response to WUPA is expected at exactly 1236/fc. No need to wait longer.
1704 uint32_t start_time
= GetTickCount();
1707 // we may need several tries if we did send an unknown command or a wrong authentication before...
1709 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1710 ReaderTransmitBitsPar(wupa
, 7, NULL
, NULL
);
1712 len
= ReaderReceive(resp
, resp_par
);
1713 } while (len
== 0 && GetTickCount() <= start_time
+ WUPA_RETRY_TIMEOUT
);
1715 iso14a_set_timeout(save_iso14a_timeout
);
1720 // performs iso14443a anticollision (optional) and card select procedure
1721 // fills the uid and cuid pointer unless NULL
1722 // fills the card info record unless NULL
1723 // if anticollision is false, then the UID must be provided in uid_ptr[]
1724 // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1725 // requests ATS unless no_rats is true
1726 int iso14443a_select_card(byte_t
*uid_ptr
, iso14a_card_select_t
*p_hi14a_card
, uint32_t *cuid_ptr
, bool anticollision
, uint8_t num_cascades
, bool no_rats
) {
1727 uint8_t sel_all
[] = { 0x93,0x20 };
1728 uint8_t sel_uid
[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1729 uint8_t rats
[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1730 uint8_t resp
[MAX_FRAME_SIZE
]; // theoretically. A usual RATS will be much smaller
1731 uint8_t resp_par
[MAX_PARITY_SIZE
];
1733 size_t uid_resp_len
;
1735 uint8_t sak
= 0x04; // cascade uid
1736 int cascade_level
= 0;
1741 p_hi14a_card
->uidlen
= 0;
1742 memset(p_hi14a_card
->uid
, 0, 10);
1743 p_hi14a_card
->ats_len
= 0;
1746 if (!GetATQA(resp
, resp_par
)) {
1751 memcpy(p_hi14a_card
->atqa
, resp
, 2);
1754 if (anticollision
) {
1757 memset(uid_ptr
,0,10);
1761 // check for proprietary anticollision:
1762 if ((resp
[0] & 0x1F) == 0) {
1766 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1767 // which case we need to make a cascade 2 request and select - this is a long UID
1768 // While the UID is not complete, the 3rd bit (from the right) is set in the SAK.
1769 for (; sak
& 0x04; cascade_level
++) {
1770 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1771 sel_uid
[0] = sel_all
[0] = 0x93 + cascade_level
* 2;
1773 if (anticollision
) {
1775 ReaderTransmit(sel_all
, sizeof(sel_all
), NULL
);
1776 if (!ReaderReceive(resp
, resp_par
)) {
1780 if (Demod
.collisionPos
) { // we had a collision and need to construct the UID bit by bit
1781 memset(uid_resp
, 0, 4);
1782 uint16_t uid_resp_bits
= 0;
1783 uint16_t collision_answer_offset
= 0;
1784 // anti-collision-loop:
1785 while (Demod
.collisionPos
) {
1786 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod
.collisionPos
);
1787 for (uint16_t i
= collision_answer_offset
; i
< Demod
.collisionPos
; i
++, uid_resp_bits
++) { // add valid UID bits before collision point
1788 uint16_t UIDbit
= (resp
[i
/8] >> (i
% 8)) & 0x01;
1789 uid_resp
[uid_resp_bits
/ 8] |= UIDbit
<< (uid_resp_bits
% 8);
1791 uid_resp
[uid_resp_bits
/8] |= 1 << (uid_resp_bits
% 8); // next time select the card(s) with a 1 in the collision position
1793 // construct anticollosion command:
1794 sel_uid
[1] = ((2 + uid_resp_bits
/8) << 4) | (uid_resp_bits
& 0x07); // length of data in bytes and bits
1795 for (uint16_t i
= 0; i
<= uid_resp_bits
/8; i
++) {
1796 sel_uid
[2+i
] = uid_resp
[i
];
1798 collision_answer_offset
= uid_resp_bits
%8;
1799 ReaderTransmitBits(sel_uid
, 16 + uid_resp_bits
, NULL
);
1800 if (!ReaderReceiveOffset(resp
, collision_answer_offset
, resp_par
)) {
1804 // finally, add the last bits and BCC of the UID
1805 for (uint16_t i
= collision_answer_offset
; i
< (Demod
.len
-1)*8; i
++, uid_resp_bits
++) {
1806 uint16_t UIDbit
= (resp
[i
/8] >> (i
%8)) & 0x01;
1807 uid_resp
[uid_resp_bits
/8] |= UIDbit
<< (uid_resp_bits
% 8);
1810 } else { // no collision, use the response to SELECT_ALL as current uid
1811 memcpy(uid_resp
, resp
, 4);
1814 if (cascade_level
< num_cascades
- 1) {
1816 memcpy(uid_resp
+1, uid_ptr
+cascade_level
*3, 3);
1818 memcpy(uid_resp
, uid_ptr
+cascade_level
*3, 4);
1823 // calculate crypto UID. Always use last 4 Bytes.
1825 *cuid_ptr
= bytes_to_num(uid_resp
, 4);
1828 // Construct SELECT UID command
1829 sel_uid
[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1830 memcpy(sel_uid
+2, uid_resp
, 4); // the UID received during anticollision, or the provided UID
1831 sel_uid
[6] = sel_uid
[2] ^ sel_uid
[3] ^ sel_uid
[4] ^ sel_uid
[5]; // calculate and add BCC
1832 AppendCrc14443a(sel_uid
, 7); // calculate and add CRC
1833 ReaderTransmit(sel_uid
, sizeof(sel_uid
), NULL
);
1836 if (!ReaderReceive(resp
, resp_par
)) {
1841 // Test if more parts of the uid are coming
1842 if ((sak
& 0x04) /* && uid_resp[0] == 0x88 */) {
1843 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1844 // http://www.nxp.com/documents/application_note/AN10927.pdf
1845 uid_resp
[0] = uid_resp
[1];
1846 uid_resp
[1] = uid_resp
[2];
1847 uid_resp
[2] = uid_resp
[3];
1851 if(uid_ptr
&& anticollision
) {
1852 memcpy(uid_ptr
+ (cascade_level
*3), uid_resp
, uid_resp_len
);
1856 memcpy(p_hi14a_card
->uid
+ (cascade_level
*3), uid_resp
, uid_resp_len
);
1857 p_hi14a_card
->uidlen
+= uid_resp_len
;
1862 p_hi14a_card
->sak
= sak
;
1865 // PICC compilant with iso14443a-4 ---> (SAK & 0x20 != 0)
1866 if( (sak
& 0x20) == 0) return 2;
1869 // Request for answer to select
1870 AppendCrc14443a(rats
, 2);
1871 ReaderTransmit(rats
, sizeof(rats
), NULL
);
1873 if (!(len
= ReaderReceive(resp
, resp_par
))) {
1878 memcpy(p_hi14a_card
->ats
, resp
, len
);
1879 p_hi14a_card
->ats_len
= len
;
1882 // reset the PCB block number
1883 iso14_pcb_blocknum
= 0;
1885 // set default timeout and delay next transfer based on ATS
1886 iso14a_set_ATS_times(resp
);
1893 void iso14443a_setup(uint8_t fpga_minor_mode
) {
1894 FpgaDownloadAndGo(FPGA_BITSTREAM_HF
);
1895 // Set up the synchronous serial port
1896 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A
);
1897 // connect Demodulated Signal to ADC:
1898 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
1900 // Signal field is on with the appropriate LED
1901 if (fpga_minor_mode
== FPGA_HF_ISO14443A_READER_MOD
1902 || fpga_minor_mode
== FPGA_HF_ISO14443A_READER_LISTEN
) {
1907 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| fpga_minor_mode
);
1909 // Set ADC to read field strength
1910 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_SWRST
;
1911 AT91C_BASE_ADC
->ADC_MR
=
1912 ADC_MODE_PRESCALE(63) |
1913 ADC_MODE_STARTUP_TIME(1) |
1914 ADC_MODE_SAMPLE_HOLD_TIME(15);
1915 AT91C_BASE_ADC
->ADC_CHER
= ADC_CHANNEL(ADC_CHAN_HF_LOW
);
1922 LastTimeProxToAirStart
= 0;
1923 FpgaSendQueueDelay
= 0;
1924 LastProxToAirDuration
= 20; // arbitrary small value. Avoid lock in EmGetCmd()
1925 NextTransferTime
= 2*DELAY_ARM2AIR_AS_READER
;
1926 iso14a_set_timeout(1060); // 10ms default
1929 /* Peter Fillmore 2015
1930 Added card id field to the function
1931 info from ISO14443A standard
1934 b3 = depends on block
1935 b4 = Card ID following if set to 1
1936 b5 = depends on block type
1937 b6 = depends on block type
1940 b8 b7 b6 b5 b4 b3 b2 b1
1944 b8 b7 b6 b5 b4 b3 b2 b1
1948 b8 b7 b6 b5 b4 b3 b2 b1
1950 b5,b6 = 00 - DESELECT
1953 int iso14_apdu(uint8_t *cmd
, uint16_t cmd_len
, bool send_chaining
, void *data
, uint8_t *res
) {
1954 uint8_t parity
[MAX_PARITY_SIZE
];
1955 uint8_t real_cmd
[cmd_len
+ 4];
1958 // ISO 14443 APDU frame: PCB [CID] [NAD] APDU CRC PCB=0x02
1959 real_cmd
[0] = 0x02; // bnr,nad,cid,chn=0; i-block(0x00)
1960 if (send_chaining
) {
1961 real_cmd
[0] |= 0x10;
1963 // put block number into the PCB
1964 real_cmd
[0] |= iso14_pcb_blocknum
;
1965 memcpy(real_cmd
+ 1, cmd
, cmd_len
);
1968 real_cmd
[0] = 0xA2; // r-block + ACK
1969 real_cmd
[0] |= iso14_pcb_blocknum
;
1971 AppendCrc14443a(real_cmd
, cmd_len
+ 1);
1973 ReaderTransmit(real_cmd
, cmd_len
+ 3, NULL
);
1975 size_t len
= ReaderReceive(data
, parity
);
1976 uint8_t *data_bytes
= (uint8_t *) data
;
1979 return 0; //DATA LINK ERROR
1982 while (len
&& ((data_bytes
[0] & 0xF2) == 0xF2)) {
1983 uint32_t save_iso14a_timeout
= iso14a_get_timeout();
1984 // temporarily increase timeout
1985 iso14a_set_timeout(MAX((data_bytes
[1] & 0x3f) * save_iso14a_timeout
, MAX_ISO14A_TIMEOUT
));
1986 // Transmit WTX back
1987 // byte1 - WTXM [1..59]. command FWT=FWT*WTXM
1988 data_bytes
[1] = data_bytes
[1] & 0x3f; // 2 high bits mandatory set to 0b
1989 // now need to fix CRC.
1990 AppendCrc14443a(data_bytes
, len
- 2);
1992 ReaderTransmit(data_bytes
, len
, NULL
);
1993 // retrieve the result again (with increased timeout)
1994 len
= ReaderReceive(data
, parity
);
1997 iso14a_set_timeout(save_iso14a_timeout
);
2000 // if we received an I- or R(ACK)-Block with a block number equal to the
2001 // current block number, toggle the current block number
2002 if (len
>= 3 // PCB+CRC = 3 bytes
2003 && ((data_bytes
[0] & 0xC0) == 0 // I-Block
2004 || (data_bytes
[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2005 && (data_bytes
[0] & 0x01) == iso14_pcb_blocknum
) // equal block numbers
2007 iso14_pcb_blocknum
^= 1;
2010 // if we received I-block with chaining we need to send ACK and receive another block of data
2012 *res
= data_bytes
[0];
2015 if (len
>= 3 && !CheckCrc14443(CRC_14443_A
, data_bytes
, len
)) {
2024 // memmove(data_bytes, data_bytes + 1, len);
2025 for (int i
= 0; i
< len
; i
++)
2026 data_bytes
[i
] = data_bytes
[i
+ 1];
2033 //-----------------------------------------------------------------------------
2034 // Read an ISO 14443a tag. Send out commands and store answers.
2036 //-----------------------------------------------------------------------------
2037 void ReaderIso14443a(UsbCommand
*c
)
2039 iso14a_command_t param
= c
->arg
[0];
2040 uint8_t *cmd
= c
->d
.asBytes
;
2041 size_t len
= c
->arg
[1] & 0xffff;
2042 size_t lenbits
= c
->arg
[1] >> 16;
2043 uint32_t timeout
= c
->arg
[2];
2045 byte_t buf
[USB_CMD_DATA_SIZE
] = {0};
2046 uint8_t par
[MAX_PARITY_SIZE
];
2047 bool cantSELECT
= false;
2051 if(param
& ISO14A_CLEAR_TRACE
) {
2055 if(param
& ISO14A_REQUEST_TRIGGER
) {
2056 iso14a_set_trigger(true);
2059 if(param
& ISO14A_CONNECT
) {
2061 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN
);
2062 if(!(param
& ISO14A_NO_SELECT
)) {
2063 iso14a_card_select_t
*card
= (iso14a_card_select_t
*)buf
;
2064 arg0
= iso14443a_select_card(NULL
, card
, NULL
, true, 0, param
& ISO14A_NO_RATS
);
2066 // if we cant select then we cant send data
2067 if (arg0
!= 1 && arg0
!= 2) {
2068 // 1 - all is OK with ATS, 2 - without ATS
2071 FpgaDisableTracing();
2073 cmd_send(CMD_ACK
,arg0
,card
->uidlen
,0,buf
,sizeof(iso14a_card_select_t
));
2078 if(param
& ISO14A_SET_TIMEOUT
) {
2079 iso14a_set_timeout(timeout
);
2082 if(param
& ISO14A_APDU
&& !cantSELECT
) {
2084 arg0
= iso14_apdu(cmd
, len
, (param
& ISO14A_SEND_CHAINING
), buf
, &res
);
2085 FpgaDisableTracing();
2087 cmd_send(CMD_ACK
, arg0
, res
, 0, buf
, sizeof(buf
));
2091 if(param
& ISO14A_RAW
&& !cantSELECT
) {
2092 if(param
& ISO14A_APPEND_CRC
) {
2093 if(param
& ISO14A_TOPAZMODE
) {
2094 AppendCrc14443b(cmd
,len
);
2096 AppendCrc14443a(cmd
,len
);
2099 if (lenbits
) lenbits
+= 16;
2101 if(lenbits
>0) { // want to send a specific number of bits (e.g. short commands)
2102 if(param
& ISO14A_TOPAZMODE
) {
2103 int bits_to_send
= lenbits
;
2105 ReaderTransmitBitsPar(&cmd
[i
++], MIN(bits_to_send
, 7), NULL
, NULL
); // first byte is always short (7bits) and no parity
2107 while (bits_to_send
> 0) {
2108 ReaderTransmitBitsPar(&cmd
[i
++], MIN(bits_to_send
, 8), NULL
, NULL
); // following bytes are 8 bit and no parity
2112 GetParity(cmd
, lenbits
/8, par
);
2113 ReaderTransmitBitsPar(cmd
, lenbits
, par
, NULL
); // bytes are 8 bit with odd parity
2115 } else { // want to send complete bytes only
2116 if(param
& ISO14A_TOPAZMODE
) {
2118 ReaderTransmitBitsPar(&cmd
[i
++], 7, NULL
, NULL
); // first byte: 7 bits, no paritiy
2120 ReaderTransmitBitsPar(&cmd
[i
++], 8, NULL
, NULL
); // following bytes: 8 bits, no paritiy
2123 ReaderTransmit(cmd
,len
, NULL
); // 8 bits, odd parity
2126 arg0
= ReaderReceive(buf
, par
);
2127 FpgaDisableTracing();
2130 cmd_send(CMD_ACK
,arg0
,0,0,buf
,sizeof(buf
));
2134 if(param
& ISO14A_REQUEST_TRIGGER
) {
2135 iso14a_set_trigger(false);
2138 if(param
& ISO14A_NO_DISCONNECT
) {
2142 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2147 // Determine the distance between two nonces.
2148 // Assume that the difference is small, but we don't know which is first.
2149 // Therefore try in alternating directions.
2150 static int32_t dist_nt(uint32_t nt1
, uint32_t nt2
) {
2153 uint32_t nttmp1
, nttmp2
;
2155 if (nt1
== nt2
) return 0;
2160 for (i
= 1; i
< 32768; i
++) {
2161 nttmp1
= prng_successor(nttmp1
, 1);
2162 if (nttmp1
== nt2
) return i
;
2163 nttmp2
= prng_successor(nttmp2
, 1);
2164 if (nttmp2
== nt1
) return -i
;
2167 return(-99999); // either nt1 or nt2 are invalid nonces
2171 //-----------------------------------------------------------------------------
2172 // Recover several bits of the cypher stream. This implements (first stages of)
2173 // the algorithm described in "The Dark Side of Security by Obscurity and
2174 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2175 // (article by Nicolas T. Courtois, 2009)
2176 //-----------------------------------------------------------------------------
2177 void ReaderMifare(bool first_try
)
2180 uint8_t mf_auth
[] = { 0x60,0x00,0xf5,0x7b };
2181 uint8_t mf_nr_ar
[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2182 static uint8_t mf_nr_ar3
;
2184 uint8_t receivedAnswer
[MAX_MIFARE_FRAME_SIZE
];
2185 uint8_t receivedAnswerPar
[MAX_MIFARE_PARITY_SIZE
];
2187 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD
);
2189 // free eventually allocated BigBuf memory. We want all for tracing.
2195 uint8_t nt_diff
= 0;
2196 uint8_t par
[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2197 static uint8_t par_low
= 0;
2199 uint8_t uid
[10] ={0};
2203 uint32_t previous_nt
= 0;
2204 static uint32_t nt_attacked
= 0;
2205 uint8_t par_list
[8] = {0x00};
2206 uint8_t ks_list
[8] = {0x00};
2208 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2209 uint32_t sync_time
= GetCountSspClk() & 0xfffffff8;
2210 static int32_t sync_cycles
;
2211 int catch_up_cycles
= 0;
2212 int last_catch_up
= 0;
2213 uint16_t elapsed_prng_sequences
;
2214 uint16_t consecutive_resyncs
= 0;
2219 par
[0] = par_low
= 0;
2220 sync_cycles
= PRNG_SEQUENCE_LENGTH
; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2224 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2226 mf_nr_ar
[3] = mf_nr_ar3
;
2235 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2236 #define MAX_SYNC_TRIES 32
2237 #define SYNC_TIME_BUFFER 16 // if there is only SYNC_TIME_BUFFER left before next planned sync, wait for next PRNG cycle
2238 #define NUM_DEBUG_INFOS 8 // per strategy
2239 #define MAX_STRATEGY 3
2240 uint16_t unexpected_random
= 0;
2241 uint16_t sync_tries
= 0;
2242 int16_t debug_info_nr
= -1;
2243 uint16_t strategy
= 0;
2244 int32_t debug_info
[MAX_STRATEGY
][NUM_DEBUG_INFOS
];
2245 uint32_t select_time
;
2248 for (uint16_t i
= 0; true; i
++) {
2253 // Test if the action was cancelled
2254 if(BUTTON_PRESS()) {
2259 if (strategy
== 2) {
2260 // test with additional hlt command
2262 int len
= mifare_sendcmd_short(NULL
, false, 0x50, 0x00, receivedAnswer
, receivedAnswerPar
, &halt_time
);
2263 if (len
&& MF_DBGLEVEL
>= 3) {
2264 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len
);
2268 if (strategy
== 3) {
2269 // test with FPGA power off/on
2270 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2272 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD
);
2276 if(!iso14443a_select_card(uid
, NULL
, &cuid
, true, 0, true)) {
2277 if (MF_DBGLEVEL
>= 1) Dbprintf("Mifare: Can't select card");
2280 select_time
= GetCountSspClk();
2282 elapsed_prng_sequences
= 1;
2283 if (debug_info_nr
== -1) {
2284 sync_time
= (sync_time
& 0xfffffff8) + sync_cycles
+ catch_up_cycles
;
2285 catch_up_cycles
= 0;
2287 // if we missed the sync time already or are about to miss it, advance to the next nonce repeat
2288 while(sync_time
< GetCountSspClk() + SYNC_TIME_BUFFER
) {
2289 elapsed_prng_sequences
++;
2290 sync_time
= (sync_time
& 0xfffffff8) + sync_cycles
;
2293 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2294 ReaderTransmit(mf_auth
, sizeof(mf_auth
), &sync_time
);
2296 // collect some information on tag nonces for debugging:
2297 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2298 if (strategy
== 0) {
2299 // nonce distances at fixed time after card select:
2300 sync_time
= select_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2301 } else if (strategy
== 1) {
2302 // nonce distances at fixed time between authentications:
2303 sync_time
= sync_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2304 } else if (strategy
== 2) {
2305 // nonce distances at fixed time after halt:
2306 sync_time
= halt_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2308 // nonce_distances at fixed time after power on
2309 sync_time
= DEBUG_FIXED_SYNC_CYCLES
;
2311 ReaderTransmit(mf_auth
, sizeof(mf_auth
), &sync_time
);
2314 // Receive the (4 Byte) "random" nonce
2315 if (!ReaderReceive(receivedAnswer
, receivedAnswerPar
)) {
2316 if (MF_DBGLEVEL
>= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2321 nt
= bytes_to_num(receivedAnswer
, 4);
2323 // Transmit reader nonce with fake par
2324 ReaderTransmitPar(mf_nr_ar
, sizeof(mf_nr_ar
), par
, NULL
);
2326 if (first_try
&& previous_nt
&& !nt_attacked
) { // we didn't calibrate our clock yet
2327 int nt_distance
= dist_nt(previous_nt
, nt
);
2328 if (nt_distance
== 0) {
2331 if (nt_distance
== -99999) { // invalid nonce received
2332 unexpected_random
++;
2333 if (unexpected_random
> MAX_UNEXPECTED_RANDOM
) {
2334 isOK
= -3; // Card has an unpredictable PRNG. Give up
2337 continue; // continue trying...
2340 if (++sync_tries
> MAX_SYNC_TRIES
) {
2341 if (strategy
> MAX_STRATEGY
|| MF_DBGLEVEL
< 3) {
2342 isOK
= -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2344 } else { // continue for a while, just to collect some debug info
2345 debug_info
[strategy
][debug_info_nr
] = nt_distance
;
2347 if (debug_info_nr
== NUM_DEBUG_INFOS
) {
2354 sync_cycles
= (sync_cycles
- nt_distance
/elapsed_prng_sequences
);
2355 if (sync_cycles
<= 0) {
2356 sync_cycles
+= PRNG_SEQUENCE_LENGTH
;
2358 if (MF_DBGLEVEL
>= 3) {
2359 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i
, nt_distance
, elapsed_prng_sequences
, sync_cycles
);
2365 if ((nt
!= nt_attacked
) && nt_attacked
) { // we somehow lost sync. Try to catch up again...
2366 catch_up_cycles
= -dist_nt(nt_attacked
, nt
);
2367 if (catch_up_cycles
== 99999) { // invalid nonce received. Don't resync on that one.
2368 catch_up_cycles
= 0;
2371 catch_up_cycles
/= elapsed_prng_sequences
;
2372 if (catch_up_cycles
== last_catch_up
) {
2373 consecutive_resyncs
++;
2376 last_catch_up
= catch_up_cycles
;
2377 consecutive_resyncs
= 0;
2379 if (consecutive_resyncs
< 3) {
2380 if (MF_DBGLEVEL
>= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i
, -catch_up_cycles
, consecutive_resyncs
);
2383 sync_cycles
= sync_cycles
+ catch_up_cycles
;
2384 if (MF_DBGLEVEL
>= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i
, -catch_up_cycles
, sync_cycles
);
2386 catch_up_cycles
= 0;
2387 consecutive_resyncs
= 0;
2392 consecutive_resyncs
= 0;
2394 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2395 if (ReaderReceive(receivedAnswer
, receivedAnswerPar
)) {
2396 catch_up_cycles
= 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2399 par_low
= par
[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2403 if(led_on
) LED_B_ON(); else LED_B_OFF();
2405 par_list
[nt_diff
] = SwapBits(par
[0], 8);
2406 ks_list
[nt_diff
] = receivedAnswer
[0] ^ 0x05;
2408 // Test if the information is complete
2409 if (nt_diff
== 0x07) {
2414 nt_diff
= (nt_diff
+ 1) & 0x07;
2415 mf_nr_ar
[3] = (mf_nr_ar
[3] & 0x1F) | (nt_diff
<< 5);
2418 if (nt_diff
== 0 && first_try
)
2421 if (par
[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2426 par
[0] = ((par
[0] & 0x1F) + 1) | par_low
;
2432 mf_nr_ar
[3] &= 0x1F;
2435 if (MF_DBGLEVEL
>= 3) {
2436 for (uint16_t i
= 0; i
<= MAX_STRATEGY
; i
++) {
2437 for (uint16_t j
= 0; j
< NUM_DEBUG_INFOS
; j
++) {
2438 Dbprintf("collected debug info[%d][%d] = %d", i
, j
, debug_info
[i
][j
]);
2444 FpgaDisableTracing();
2447 memcpy(buf
+ 0, uid
, 4);
2448 num_to_bytes(nt
, 4, buf
+ 4);
2449 memcpy(buf
+ 8, par_list
, 8);
2450 memcpy(buf
+ 16, ks_list
, 8);
2451 memcpy(buf
+ 24, mf_nr_ar
, 8);
2453 cmd_send(CMD_ACK
, isOK
, 0, 0, buf
, 32);
2456 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2463 //-----------------------------------------------------------------------------
2466 //-----------------------------------------------------------------------------
2467 void RAMFUNC
SniffMifare(uint8_t param
) {
2469 // bit 0 - trigger from first card answer
2470 // bit 1 - trigger from first reader 7-bit request
2472 // C(red) A(yellow) B(green)
2476 // init trace buffer
2480 // The command (reader -> tag) that we're receiving.
2481 // The length of a received command will in most cases be no more than 18 bytes.
2482 // So 32 should be enough!
2483 uint8_t receivedCmd
[MAX_MIFARE_FRAME_SIZE
];
2484 uint8_t receivedCmdPar
[MAX_MIFARE_PARITY_SIZE
];
2485 // The response (tag -> reader) that we're receiving.
2486 uint8_t receivedResponse
[MAX_MIFARE_FRAME_SIZE
];
2487 uint8_t receivedResponsePar
[MAX_MIFARE_PARITY_SIZE
];
2489 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER
);
2491 // free eventually allocated BigBuf memory
2493 // allocate the DMA buffer, used to stream samples from the FPGA
2494 uint8_t *dmaBuf
= BigBuf_malloc(DMA_BUFFER_SIZE
);
2495 uint8_t *data
= dmaBuf
;
2496 uint8_t previous_data
= 0;
2499 bool ReaderIsActive
= false;
2500 bool TagIsActive
= false;
2502 // Set up the demodulator for tag -> reader responses.
2503 DemodInit(receivedResponse
, receivedResponsePar
);
2505 // Set up the demodulator for the reader -> tag commands
2506 UartInit(receivedCmd
, receivedCmdPar
);
2508 // Setup for the DMA.
2509 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
); // set transfer address and number of bytes. Start transfer.
2514 // And now we loop, receiving samples.
2515 for (uint32_t sniffCounter
= 0; true; ) {
2517 if(BUTTON_PRESS()) {
2518 DbpString("Canceled by button.");
2524 if ((sniffCounter
& 0x0000FFFF) == 0) { // from time to time
2525 // check if a transaction is completed (timeout after 2000ms).
2526 // if yes, stop the DMA transfer and send what we have so far to the client
2527 if (MfSniffSend(2000)) {
2528 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2532 ReaderIsActive
= false;
2533 TagIsActive
= false;
2534 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
); // set transfer address and number of bytes. Start transfer.
2538 int register readBufDataP
= data
- dmaBuf
; // number of bytes we have processed so far
2539 int register dmaBufDataP
= DMA_BUFFER_SIZE
- AT91C_BASE_PDC_SSC
->PDC_RCR
; // number of bytes already transferred
2540 if (readBufDataP
<= dmaBufDataP
){ // we are processing the same block of data which is currently being transferred
2541 dataLen
= dmaBufDataP
- readBufDataP
; // number of bytes still to be processed
2543 dataLen
= DMA_BUFFER_SIZE
- readBufDataP
+ dmaBufDataP
; // number of bytes still to be processed
2545 // test for length of buffer
2546 if(dataLen
> maxDataLen
) { // we are more behind than ever...
2547 maxDataLen
= dataLen
;
2548 if(dataLen
> (9 * DMA_BUFFER_SIZE
/ 10)) {
2549 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen
);
2553 if(dataLen
< 1) continue;
2555 // primary buffer was stopped ( <-- we lost data!
2556 if (!AT91C_BASE_PDC_SSC
->PDC_RCR
) {
2557 AT91C_BASE_PDC_SSC
->PDC_RPR
= (uint32_t) dmaBuf
;
2558 AT91C_BASE_PDC_SSC
->PDC_RCR
= DMA_BUFFER_SIZE
;
2559 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen
); // temporary
2561 // secondary buffer sets as primary, secondary buffer was stopped
2562 if (!AT91C_BASE_PDC_SSC
->PDC_RNCR
) {
2563 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
;
2564 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
2567 if (sniffCounter
& 0x01) {
2569 if(!TagIsActive
) { // no need to try decoding tag data if the reader is sending
2570 uint8_t readerdata
= (previous_data
& 0xF0) | (*data
>> 4);
2571 if(MillerDecoding(readerdata
, (sniffCounter
-1)*4)) {
2573 if (MfSniffLogic(receivedCmd
, Uart
.len
, Uart
.parity
, Uart
.bitCount
, true)) break;
2575 /* And ready to receive another command. */
2576 UartInit(receivedCmd
, receivedCmdPar
);
2578 /* And also reset the demod code */
2581 ReaderIsActive
= (Uart
.state
!= STATE_UNSYNCD
);
2584 if(!ReaderIsActive
) { // no need to try decoding tag data if the reader is sending
2585 uint8_t tagdata
= (previous_data
<< 4) | (*data
& 0x0F);
2586 if(ManchesterDecoding(tagdata
, 0, (sniffCounter
-1)*4)) {
2588 if (MfSniffLogic(receivedResponse
, Demod
.len
, Demod
.parity
, Demod
.bitCount
, false)) break;
2590 // And ready to receive another response.
2592 // And reset the Miller decoder including its (now outdated) input buffer
2593 UartInit(receivedCmd
, receivedCmdPar
);
2595 TagIsActive
= (Demod
.state
!= DEMOD_UNSYNCD
);
2599 previous_data
= *data
;
2602 if(data
== dmaBuf
+ DMA_BUFFER_SIZE
) {
2608 FpgaDisableTracing();
2609 FpgaDisableSscDma();
2612 DbpString("COMMAND FINISHED.");
2616 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen
, Uart
.state
, Uart
.len
);