cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/fpga_hf.v

   1 //-----------------------------------------------------------------------------
   2 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
   3 // and the ARM. In the low-frequency modes it passes the data straight
   4 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
   5 // frequency modes, the FPGA might perform some demodulation first, to
   6 // reduce the amount of data that we must send to the ARM.
   7 //
   8 // I am not really an FPGA/ASIC designer, so I am sure that a lot of this
   9 // could be improved.
  10 //
  11 // Jonathan Westhues, March 2006
  12 // Added ISO14443-A support by Gerhard de Koning Gans, April 2008
  13 // iZsh <izsh at fail0verflow.com>, June 2014
  14 //-----------------------------------------------------------------------------
  15
  16 // Defining modes and options. This must be aligned to the definitions in fpgaloader.h
  17 // Note: the definitions here are without shifts
  18 // Major modes:
  19 `define FPGA_MAJOR_MODE_LF_ADC                      0
  20 `define FPGA_MAJOR_MODE_LF_EDGE_DETECT              1
  21 `define FPGA_MAJOR_MODE_LF_PASSTHRU                 2
  22 `define FPGA_MAJOR_MODE_HF_READER                   0
  23 `define FPGA_MAJOR_MODE_HF_SIMULATOR                1
  24 `define FPGA_MAJOR_MODE_HF_ISO14443A                2
  25 `define FPGA_MAJOR_MODE_HF_SNOOP                    3
  26 `define FPGA_MAJOR_MODE_HF_GET_TRACE                4
  27 `define FPGA_MAJOR_MODE_OFF                         7
  28
  29 // Options for the generic HF reader
  30 `define FPGA_HF_READER_MODE_RECEIVE_IQ              0
  31 `define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE       1
  32 `define FPGA_HF_READER_MODE_RECEIVE_PHASE           2
  33 `define FPGA_HF_READER_MODE_SEND_FULL_MOD           3
  34 `define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD        4
  35 `define FPGA_HF_READER_MODE_SNIFF_IQ                5
  36 `define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE         6
  37 `define FPGA_HF_READER_MODE_SNIFF_PHASE             7
  38 `define FPGA_HF_READER_SUBCARRIER_848_KHZ           0
  39 `define FPGA_HF_READER_SUBCARRIER_424_KHZ           1
  40 `define FPGA_HF_READER_SUBCARRIER_212_KHZ           2
  41
  42 // Options for the HF simulated tag, how to modulate
  43 `define FPGA_HF_SIMULATOR_NO_MODULATION             0
  44 `define FPGA_HF_SIMULATOR_MODULATE_BPSK             1
  45 `define FPGA_HF_SIMULATOR_MODULATE_212K             2
  46 `define FPGA_HF_SIMULATOR_MODULATE_424K             4
  47 `define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT        5
  48
  49 // Options for ISO14443A
  50 `define FPGA_HF_ISO14443A_SNIFFER                   0
  51 `define FPGA_HF_ISO14443A_TAGSIM_LISTEN             1
  52 `define FPGA_HF_ISO14443A_TAGSIM_MOD                2
  53 `define FPGA_HF_ISO14443A_READER_LISTEN             3
  54 `define FPGA_HF_ISO14443A_READER_MOD                4
  55
  56 `include "hi_reader.v"
  57 `include "hi_simulate.v"
  58 `include "hi_iso14443a.v"
  59 `include "hi_sniffer.v"
  60 `include "hi_get_trace.v"
  61 `include "util.v"
  62
  63 module fpga_hf(
  64         input spck, output miso, input mosi, input ncs,
  65         input pck0, input ck_1356meg, input ck_1356megb,
  66         output pwr_lo, output pwr_hi,
  67         output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
  68         input [7:0] adc_d, output adc_clk, output adc_noe,
  69         output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
  70         input cross_hi, input cross_lo,
  71         output dbg
  72 );
  73
  74 //-----------------------------------------------------------------------------
  75 // The SPI receiver. This sets up the configuration word, which the rest of
  76 // the logic looks at to determine how to connect the A/D and the coil
  77 // drivers (i.e., which section gets it). Also assign some symbolic names
  78 // to the configuration bits, for use below.
  79 //-----------------------------------------------------------------------------
  80
  81 reg [15:0] shift_reg;
  82 reg [7:0] conf_word;
  83 reg trace_enable;
  84
  85 // We switch modes between transmitting to the 13.56 MHz tag and receiving
  86 // from it, which means that we must make sure that we can do so without
  87 // glitching, or else we will glitch the transmitted carrier.
  88 always @(posedge ncs)
  89 begin
  90         case(shift_reg[15:12])
  91                 4'b0001: conf_word <= shift_reg[7:0];       // FPGA_CMD_SET_CONFREG
  92                 4'b0010: trace_enable <= shift_reg[0];      // FPGA_CMD_TRACE_ENABLE
  93         endcase
  94 end
  95
  96 always @(posedge spck)
  97 begin
  98         if(~ncs)
  99         begin
 100                 shift_reg[15:1] <= shift_reg[14:0];
 101                 shift_reg[0] <= mosi;
 102         end
 103 end
 104
 105 // select module (outputs) based on major mode
 106 wire [2:0] major_mode = conf_word[7:5];
 107
 108 // configuring the HF reader
 109 wire [1:0] subcarrier_frequency = conf_word[4:3];
 110 wire [2:0] minor_mode = conf_word[2:0];
 111
 112 //-----------------------------------------------------------------------------
 113 // And then we instantiate the modules corresponding to each of the FPGA's
 114 // major modes, and use muxes to connect the outputs of the active mode to
 115 // the output pins.
 116 //-----------------------------------------------------------------------------
 117
 118 hi_reader hr(
 119         ck_1356megb,
 120         hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
 121         adc_d, hr_adc_clk,
 122         hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
 123         hr_dbg,
 124         subcarrier_frequency, minor_mode
 125 );
 126
 127 hi_simulate hs(
 128         ck_1356meg,
 129         hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
 130         adc_d, hs_adc_clk,
 131         hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
 132         hs_dbg,
 133         minor_mode
 134 );
 135
 136 hi_iso14443a hisn(
 137         ck_1356meg,
 138         hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
 139         adc_d, hisn_adc_clk,
 140         hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
 141         hisn_dbg,
 142         minor_mode
 143 );
 144
 145 hi_sniffer he(
 146         ck_1356megb,
 147         he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
 148         adc_d, he_adc_clk,
 149         he_ssp_frame, he_ssp_din, he_ssp_clk
 150 );
 151
 152 hi_get_trace gt(
 153         ck_1356megb,
 154         adc_d, trace_enable, major_mode,
 155         gt_ssp_frame, gt_ssp_din, gt_ssp_clk
 156 );
 157
 158 // Major modes:
 159
 160 //   000 --  HF reader; subcarrier frequency and modulation depth selectable
 161 //   001 --  HF simulated tag
 162 //   010 --  HF ISO14443-A
 163 //   011 --  HF Snoop
 164 //   100 --  HF get trace
 165 //   111 --  everything off
 166
 167 mux8 mux_ssp_clk        (major_mode, ssp_clk,   hr_ssp_clk,   hs_ssp_clk,   hisn_ssp_clk,   he_ssp_clk,   gt_ssp_clk,   1'b0, 1'b0, 1'b0);
 168 mux8 mux_ssp_din        (major_mode, ssp_din,   hr_ssp_din,   hs_ssp_din,   hisn_ssp_din,   he_ssp_din,   gt_ssp_din,   1'b0, 1'b0, 1'b0);
 169 mux8 mux_ssp_frame      (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, gt_ssp_frame, 1'b0, 1'b0, 1'b0);
 170 mux8 mux_pwr_oe1        (major_mode, pwr_oe1,   hr_pwr_oe1,   hs_pwr_oe1,   hisn_pwr_oe1,   he_pwr_oe1,   1'b0,         1'b0, 1'b0, 1'b0);
 171 mux8 mux_pwr_oe2        (major_mode, pwr_oe2,   hr_pwr_oe2,   hs_pwr_oe2,   hisn_pwr_oe2,   he_pwr_oe2,   1'b0,         1'b0, 1'b0, 1'b0);
 172 mux8 mux_pwr_oe3        (major_mode, pwr_oe3,   hr_pwr_oe3,   hs_pwr_oe3,   hisn_pwr_oe3,   he_pwr_oe3,   1'b0,         1'b0, 1'b0, 1'b0);
 173 mux8 mux_pwr_oe4        (major_mode, pwr_oe4,   hr_pwr_oe4,   hs_pwr_oe4,   hisn_pwr_oe4,   he_pwr_oe4,   1'b0,         1'b0, 1'b0, 1'b0);
 174 mux8 mux_pwr_lo         (major_mode, pwr_lo,    hr_pwr_lo,    hs_pwr_lo,    hisn_pwr_lo,    he_pwr_lo,    1'b0,         1'b0, 1'b0, 1'b0);
 175 mux8 mux_pwr_hi         (major_mode, pwr_hi,    hr_pwr_hi,    hs_pwr_hi,    hisn_pwr_hi,    he_pwr_hi,    1'b0,         1'b0, 1'b0, 1'b0);
 176 mux8 mux_adc_clk        (major_mode, adc_clk,   hr_adc_clk,   hs_adc_clk,   hisn_adc_clk,   he_adc_clk,   1'b0,         1'b0, 1'b0, 1'b0);
 177 mux8 mux_dbg            (major_mode, dbg,       hr_dbg,       hs_dbg,       hisn_dbg,       1'b0,         1'b0,         1'b0, 1'b0, 1'b0);
 178
 179 // In all modes, let the ADC's outputs be enabled.
 180 assign adc_noe = 1'b0;
 181
 182 // not used
 183 assign miso = 1'b0;
 184
 185 endmodule