cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/fpga.ucf

   1 # See the schematic for the pin assignment.
   2
   3 NET "adc_d<0>"  LOC = "P62"  ;
   4 NET "adc_d<1>"  LOC = "P60"  ;
   5 NET "adc_d<2>"  LOC = "P58"  ;
   6 NET "adc_d<3>"  LOC = "P57"  ;
   7 NET "adc_d<4>"  LOC = "P56"  ;
   8 NET "adc_d<5>"  LOC = "P55"  ;
   9 NET "adc_d<6>"  LOC = "P54"  ;
  10 NET "adc_d<7>"  LOC = "P53"  ;
  11 #NET "cross_hi"  LOC = "P88"  ;
  12 #NET "miso"  LOC = "P40"  ;
  13 #PACE: Start of Constraints generated by PACE
  14
  15 #PACE: Start of PACE I/O Pin Assignments
  16 NET "adc_clk"  LOC = "P46"  ;
  17 NET "adc_noe"  LOC = "P47"  ;
  18 NET "ck_1356meg"  LOC = "P91"  ;
  19 NET "ck_1356megb"  LOC = "P93"  ;
  20 NET "cross_lo"  LOC = "P87"  ;
  21 NET "dbg"  LOC = "P22"  ;
  22 NET "mosi"  LOC = "P43"  ;
  23 NET "ncs"  LOC = "P44"  ;
  24 NET "pck0"  LOC = "P36"  ;
  25 NET "pwr_hi"  LOC = "P80"  ;
  26 NET "pwr_lo"  LOC = "P81"  ;
  27 NET "pwr_oe1"  LOC = "P82"  ;
  28 NET "pwr_oe2"  LOC = "P83"  ;
  29 NET "pwr_oe3"  LOC = "P84"  ;
  30 NET "pwr_oe4"  LOC = "P86"  ;
  31 NET "spck"  LOC = "P39"  ;
  32 NET "ssp_clk"  LOC = "P71"  ;
  33 NET "ssp_din"  LOC = "P32"  ;
  34 NET "ssp_dout"  LOC = "P34"  ;
  35 NET "ssp_frame"  LOC = "P31"  ;
  36
  37 #PACE: Start of PACE Area Constraints
  38
  39 #PACE: Start of PACE Prohibit Constraints
  40
  41 #PACE: End of Constraints generated by PACE
  42
  43 # definition of Clock nets:
  44 NET "ck_1356meg" TNM_NET = "clk_net_1356" ;
  45 NET "ck_1356megb" TNM_NET = "clk_net_1356b" ;
  46 NET "pck0" TNM_NET = "clk_net_pck0" ;
  47 NET "spck" TNM_NET = "clk_net_spck" ;
  48
  49 # Timing specs of clock nets:
  50 TIMEGRP "clk_net_1356_all" = "clk_net_1356" "clk_net_1356b" ;
  51 TIMESPEC "TS_1356MHz" = PERIOD "clk_net_1356_all" 74 ns HIGH 37 ns ;
  52 TIMESPEC "TS_24MHz" = PERIOD "clk_net_pck0" 42 ns HIGH 21 ns ;
  53 TIMESPEC "TS_4MHz" = PERIOD "clk_net_spck" 250 ns HIGH 125 ns ;
  54