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Added Pm3-master changes from Holiman.
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "../include/proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "../common/crc16.h"
15 #include "../common/lfdemod.h"
16 #include "string.h"
17 #include "crapto1.h"
18 #include "mifareutil.h"
19 #include "../include/hitag2.h"
20
21 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
22 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
23 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
24 // T0 = TIMER_CLOCK1 / 125000 = 192
25 #define T0 192
26
27 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
28 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
29
30 void LFSetupFPGAForADC(int divisor, bool lf_field)
31 {
32 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
33 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
34 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
35 else if (divisor == 0)
36 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
37 else
38 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
39
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
41
42 // Connect the A/D to the peak-detected low-frequency path.
43 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
44
45 // Give it a bit of time for the resonant antenna to settle.
46 SpinDelay(150);
47
48 // Now set up the SSC to get the ADC samples that are now streaming at us.
49 FpgaSetupSsc();
50 }
51
52 void AcquireRawAdcSamples125k(int divisor)
53 {
54 LFSetupFPGAForADC(divisor, true);
55 DoAcquisition125k();
56 }
57
58 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
59 {
60 LFSetupFPGAForADC(divisor, false);
61 DoAcquisition125k_threshold(trigger_threshold);
62 }
63
64 // split into two routines so we can avoid timing issues after sending commands //
65 void DoAcquisition125k_internal(int trigger_threshold, bool silent)
66 {
67 uint8_t *dest = (uint8_t *)BigBuf;
68 uint16_t i = 0;
69 memset(dest, 0x00, BIGBUF_SIZE);
70
71 for(;;) {
72 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
73 AT91C_BASE_SSC->SSC_THR = 0x43;
74 LED_D_ON();
75 }
76 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
77 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
78 LED_D_OFF();
79 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
80 continue;
81 else
82 trigger_threshold = -1;
83 if (++i >= BIGBUF_SIZE) break;
84 }
85 }
86 if (!silent){
87 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
88 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
89 }
90 }
91 void DoAcquisition125k_threshold(int trigger_threshold) {
92 DoAcquisition125k_internal(trigger_threshold, true);
93 }
94 void DoAcquisition125k() {
95 DoAcquisition125k_internal(-1, true);
96 }
97
98 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
99 {
100 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
101
102 /* Make sure the tag is reset */
103 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
104 SpinDelay(2500);
105
106 int divisor = 95; // 125 KHz
107 // see if 'h' was specified
108 if (command[strlen((char *) command) - 1] == 'h')
109 divisor = 88; // 134.8 KHz
110
111 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
112 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
113 // Give it a bit of time for the resonant antenna to settle.
114 SpinDelay(2000);
115
116 // Now set up the SSC to get the ADC samples that are now streaming at us.
117 FpgaSetupSsc();
118
119 // now modulate the reader field
120 while(*command != '\0' && *command != ' ') {
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122 LED_D_OFF();
123 SpinDelayUs(delay_off);
124 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
125
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
127 LED_D_ON();
128 if(*(command++) == '0')
129 SpinDelayUs(period_0);
130 else
131 SpinDelayUs(period_1);
132 }
133 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
134 LED_D_OFF();
135 SpinDelayUs(delay_off);
136 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
138
139 // now do the read
140 DoAcquisition125k(-1);
141 }
142
143 /* blank r/w tag data stream
144 ...0000000000000000 01111111
145 1010101010101010101010101010101010101010101010101010101010101010
146 0011010010100001
147 01111111
148 101010101010101[0]000...
149
150 [5555fe852c5555555555555555fe0000]
151 */
152 void ReadTItag(void)
153 {
154 // some hardcoded initial params
155 // when we read a TI tag we sample the zerocross line at 2Mhz
156 // TI tags modulate a 1 as 16 cycles of 123.2Khz
157 // TI tags modulate a 0 as 16 cycles of 134.2Khz
158 #define FSAMPLE 2000000
159 #define FREQLO 123200
160 #define FREQHI 134200
161
162 signed char *dest = (signed char *)BigBuf;
163 int n = sizeof(BigBuf);
164
165 // 128 bit shift register [shift3:shift2:shift1:shift0]
166 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
167
168 int i, cycles=0, samples=0;
169 // how many sample points fit in 16 cycles of each frequency
170 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
171 // when to tell if we're close enough to one freq or another
172 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
173
174 // TI tags charge at 134.2Khz
175 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
176 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
177
178 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
179 // connects to SSP_DIN and the SSP_DOUT logic level controls
180 // whether we're modulating the antenna (high)
181 // or listening to the antenna (low)
182 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
183
184 // get TI tag data into the buffer
185 AcquireTiType();
186
187 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
188
189 for (i=0; i<n-1; i++) {
190 // count cycles by looking for lo to hi zero crossings
191 if ( (dest[i]<0) && (dest[i+1]>0) ) {
192 cycles++;
193 // after 16 cycles, measure the frequency
194 if (cycles>15) {
195 cycles=0;
196 samples=i-samples; // number of samples in these 16 cycles
197
198 // TI bits are coming to us lsb first so shift them
199 // right through our 128 bit right shift register
200 shift0 = (shift0>>1) | (shift1 << 31);
201 shift1 = (shift1>>1) | (shift2 << 31);
202 shift2 = (shift2>>1) | (shift3 << 31);
203 shift3 >>= 1;
204
205 // check if the cycles fall close to the number
206 // expected for either the low or high frequency
207 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
208 // low frequency represents a 1
209 shift3 |= (1<<31);
210 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
211 // high frequency represents a 0
212 } else {
213 // probably detected a gay waveform or noise
214 // use this as gaydar or discard shift register and start again
215 shift3 = shift2 = shift1 = shift0 = 0;
216 }
217 samples = i;
218
219 // for each bit we receive, test if we've detected a valid tag
220
221 // if we see 17 zeroes followed by 6 ones, we might have a tag
222 // remember the bits are backwards
223 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
224 // if start and end bytes match, we have a tag so break out of the loop
225 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
226 cycles = 0xF0B; //use this as a flag (ugly but whatever)
227 break;
228 }
229 }
230 }
231 }
232 }
233
234 // if flag is set we have a tag
235 if (cycles!=0xF0B) {
236 DbpString("Info: No valid tag detected.");
237 } else {
238 // put 64 bit data into shift1 and shift0
239 shift0 = (shift0>>24) | (shift1 << 8);
240 shift1 = (shift1>>24) | (shift2 << 8);
241
242 // align 16 bit crc into lower half of shift2
243 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
244
245 // if r/w tag, check ident match
246 if ( shift3&(1<<15) ) {
247 DbpString("Info: TI tag is rewriteable");
248 // only 15 bits compare, last bit of ident is not valid
249 if ( ((shift3>>16)^shift0)&0x7fff ) {
250 DbpString("Error: Ident mismatch!");
251 } else {
252 DbpString("Info: TI tag ident is valid");
253 }
254 } else {
255 DbpString("Info: TI tag is readonly");
256 }
257
258 // WARNING the order of the bytes in which we calc crc below needs checking
259 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
260 // bytes in reverse or something
261 // calculate CRC
262 uint32_t crc=0;
263
264 crc = update_crc16(crc, (shift0)&0xff);
265 crc = update_crc16(crc, (shift0>>8)&0xff);
266 crc = update_crc16(crc, (shift0>>16)&0xff);
267 crc = update_crc16(crc, (shift0>>24)&0xff);
268 crc = update_crc16(crc, (shift1)&0xff);
269 crc = update_crc16(crc, (shift1>>8)&0xff);
270 crc = update_crc16(crc, (shift1>>16)&0xff);
271 crc = update_crc16(crc, (shift1>>24)&0xff);
272
273 Dbprintf("Info: Tag data: %x%08x, crc=%x",
274 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
275 if (crc != (shift2&0xffff)) {
276 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
277 } else {
278 DbpString("Info: CRC is good");
279 }
280 }
281 }
282
283 void WriteTIbyte(uint8_t b)
284 {
285 int i = 0;
286
287 // modulate 8 bits out to the antenna
288 for (i=0; i<8; i++)
289 {
290 if (b&(1<<i)) {
291 // stop modulating antenna
292 SHORT_COIL();
293 SpinDelayUs(1000);
294 // modulate antenna
295 OPEN_COIL();
296 SpinDelayUs(1000);
297 } else {
298 // stop modulating antenna
299 SHORT_COIL();
300 SpinDelayUs(300);
301 // modulate antenna
302 OPEN_COIL();
303 SpinDelayUs(1700);
304 }
305 }
306 }
307
308 void AcquireTiType(void)
309 {
310 int i, j, n;
311 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
312 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
313 #define TIBUFLEN 1250
314
315 // clear buffer
316 memset(BigBuf,0,sizeof(BigBuf));
317
318 // Set up the synchronous serial port
319 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
320 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
321
322 // steal this pin from the SSP and use it to control the modulation
323 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
324 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
325
326 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
327 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
328
329 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
330 // 48/2 = 24 MHz clock must be divided by 12
331 AT91C_BASE_SSC->SSC_CMR = 12;
332
333 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
334 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
335 AT91C_BASE_SSC->SSC_TCMR = 0;
336 AT91C_BASE_SSC->SSC_TFMR = 0;
337
338 LED_D_ON();
339
340 // modulate antenna
341 HIGH(GPIO_SSC_DOUT);
342
343 // Charge TI tag for 50ms.
344 SpinDelay(50);
345
346 // stop modulating antenna and listen
347 LOW(GPIO_SSC_DOUT);
348
349 LED_D_OFF();
350
351 i = 0;
352 for(;;) {
353 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
354 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
355 i++; if(i >= TIBUFLEN) break;
356 }
357 WDT_HIT();
358 }
359
360 // return stolen pin to SSP
361 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
362 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
363
364 char *dest = (char *)BigBuf;
365 n = TIBUFLEN*32;
366 // unpack buffer
367 for (i=TIBUFLEN-1; i>=0; i--) {
368 for (j=0; j<32; j++) {
369 if(BigBuf[i] & (1 << j)) {
370 dest[--n] = 1;
371 } else {
372 dest[--n] = -1;
373 }
374 }
375 }
376 }
377
378 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
379 // if crc provided, it will be written with the data verbatim (even if bogus)
380 // if not provided a valid crc will be computed from the data and written.
381 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
382 {
383 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
384 if(crc == 0) {
385 crc = update_crc16(crc, (idlo)&0xff);
386 crc = update_crc16(crc, (idlo>>8)&0xff);
387 crc = update_crc16(crc, (idlo>>16)&0xff);
388 crc = update_crc16(crc, (idlo>>24)&0xff);
389 crc = update_crc16(crc, (idhi)&0xff);
390 crc = update_crc16(crc, (idhi>>8)&0xff);
391 crc = update_crc16(crc, (idhi>>16)&0xff);
392 crc = update_crc16(crc, (idhi>>24)&0xff);
393 }
394 Dbprintf("Writing to tag: %x%08x, crc=%x",
395 (unsigned int) idhi, (unsigned int) idlo, crc);
396
397 // TI tags charge at 134.2Khz
398 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
399 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
400 // connects to SSP_DIN and the SSP_DOUT logic level controls
401 // whether we're modulating the antenna (high)
402 // or listening to the antenna (low)
403 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
404 LED_A_ON();
405
406 // steal this pin from the SSP and use it to control the modulation
407 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
408 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
409
410 // writing algorithm:
411 // a high bit consists of a field off for 1ms and field on for 1ms
412 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
413 // initiate a charge time of 50ms (field on) then immediately start writing bits
414 // start by writing 0xBB (keyword) and 0xEB (password)
415 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
416 // finally end with 0x0300 (write frame)
417 // all data is sent lsb firts
418 // finish with 15ms programming time
419
420 // modulate antenna
421 HIGH(GPIO_SSC_DOUT);
422 SpinDelay(50); // charge time
423
424 WriteTIbyte(0xbb); // keyword
425 WriteTIbyte(0xeb); // password
426 WriteTIbyte( (idlo )&0xff );
427 WriteTIbyte( (idlo>>8 )&0xff );
428 WriteTIbyte( (idlo>>16)&0xff );
429 WriteTIbyte( (idlo>>24)&0xff );
430 WriteTIbyte( (idhi )&0xff );
431 WriteTIbyte( (idhi>>8 )&0xff );
432 WriteTIbyte( (idhi>>16)&0xff );
433 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
434 WriteTIbyte( (crc )&0xff ); // crc lo
435 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
436 WriteTIbyte(0x00); // write frame lo
437 WriteTIbyte(0x03); // write frame hi
438 HIGH(GPIO_SSC_DOUT);
439 SpinDelay(50); // programming time
440
441 LED_A_OFF();
442
443 // get TI tag data into the buffer
444 AcquireTiType();
445
446 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
447 DbpString("Now use tiread to check");
448 }
449
450
451
452 // PIO_CODR = Clear Output Data Register
453 // PIO_SODR = Set Output Data Register
454 //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
455 //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
456 void SimulateTagLowFrequency( uint16_t period, uint32_t gap, uint8_t ledcontrol)
457 {
458 LED_D_ON();
459
460 uint16_t i = 0;
461 uint8_t send = 0;
462
463 //int overflow = 0;
464 uint8_t *buf = (uint8_t *)BigBuf;
465
466 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
467 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
468 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
469 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
470 RELAY_OFF();
471
472 // Configure output pin that is connected to the FPGA (for modulating)
473 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
474 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
475
476 SHORT_COIL();
477
478 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
479 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
480
481 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
482 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
483 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
484
485 // Disable timer during configuration
486 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
487
488 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
489 // external trigger rising edge, load RA on rising edge of TIOA.
490 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
491
492 // Enable and reset counter
493 //AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
494 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
495
496 while(!BUTTON_PRESS()) {
497 WDT_HIT();
498
499 // Receive frame, watch for at most T0*EOF periods
500 while (AT91C_BASE_TC1->TC_CV < T0 * 55) {
501
502 // Check if rising edge in modulation is detected
503 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
504 // Retrieve the new timing values
505 //int ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow;
506 //Dbprintf("Timing value - %d %d", ra, overflow);
507 //overflow = 0;
508
509 // Reset timer every frame, we have to capture the last edge for timing
510 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
511 send = 1;
512
513 LED_B_ON();
514 }
515 }
516
517 if ( send ) {
518 // Disable timer 1 with external trigger to avoid triggers during our own modulation
519 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
520
521 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
522 // not that since the clock counts since the rising edge, but T_Wait1 is
523 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
524 // periods. The gap time T_Low varies (4..10). All timer values are in
525 // terms of T0 units
526 while(AT91C_BASE_TC0->TC_CV < T0 * 16 );
527
528 // datat kommer in som 1 bit för varje position i arrayn
529 for(i = 0; i < period; ++i) {
530
531 // Reset clock for the next bit
532 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
533
534 if ( buf[i] > 0 )
535 HIGH(GPIO_SSC_DOUT);
536 else
537 LOW(GPIO_SSC_DOUT);
538
539 while(AT91C_BASE_TC0->TC_CV < T0 * 1 );
540 }
541 // Drop modulation
542 LOW(GPIO_SSC_DOUT);
543
544 // Enable and reset external trigger in timer for capturing future frames
545 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
546 LED_B_OFF();
547 }
548
549 send = 0;
550
551 // Save the timer overflow, will be 0 when frame was received
552 //overflow += (AT91C_BASE_TC1->TC_CV/T0);
553
554 // Reset the timer to restart while-loop that receives frames
555 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
556 }
557
558 LED_B_OFF();
559 LED_D_OFF();
560 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
561 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
562 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
563
564 DbpString("Sim Stopped");
565 }
566
567
568 void SimulateTagLowFrequencyA(int len, int gap)
569 {
570 uint8_t *buf = (uint8_t *)BigBuf;
571
572 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
573 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
574 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE); // new izsh toggle mode!
575
576 // Connect the A/D to the peak-detected low-frequency path.
577 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
578
579 // Now set up the SSC to get the ADC samples that are now streaming at us.
580 FpgaSetupSsc();
581 SpinDelay(5);
582
583 AT91C_BASE_SSC->SSC_THR = 0x00;
584
585 int i = 0;
586 while(!BUTTON_PRESS()) {
587 WDT_HIT();
588 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
589
590 if ( buf[i] > 0 )
591 AT91C_BASE_SSC->SSC_THR = 0x43;
592 else
593 AT91C_BASE_SSC->SSC_THR = 0x00;
594
595 ++i;
596 LED_A_ON();
597 if (i >= len){
598 i = 0;
599 }
600 }
601
602 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
603 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
604 (void)r;
605 LED_A_OFF();
606 }
607 }
608 DbpString("lf simulate stopped");
609 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
610 }
611
612 #define DEBUG_FRAME_CONTENTS 1
613 void SimulateTagLowFrequencyBidir(int divisor, int t0)
614 {
615 }
616
617 // compose fc/8 fc/10 waveform
618 static void fc(int c, uint16_t *n) {
619 uint8_t *dest = (uint8_t *)BigBuf;
620 int idx;
621
622 // for when we want an fc8 pattern every 4 logical bits
623 if(c == 0) {
624 dest[((*n)++)]=1;
625 dest[((*n)++)]=1;
626 dest[((*n)++)]=0;
627 dest[((*n)++)]=0;
628 dest[((*n)++)]=0;
629 dest[((*n)++)]=0;
630 dest[((*n)++)]=0;
631 dest[((*n)++)]=0;
632 }
633 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
634 if(c == 8) {
635 for (idx=0; idx<6; idx++) {
636 dest[((*n)++)]=1;
637 dest[((*n)++)]=1;
638 dest[((*n)++)]=0;
639 dest[((*n)++)]=0;
640 dest[((*n)++)]=0;
641 dest[((*n)++)]=0;
642 dest[((*n)++)]=0;
643 dest[((*n)++)]=0;
644 }
645 }
646
647 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
648 if(c == 10) {
649 for (idx = 0; idx < 5; idx++) {
650 dest[((*n)++)]=1;
651 dest[((*n)++)]=1;
652 dest[((*n)++)]=1;
653 dest[((*n)++)]=0;
654 dest[((*n)++)]=0;
655 dest[((*n)++)]=0;
656 dest[((*n)++)]=0;
657 dest[((*n)++)]=0;
658 dest[((*n)++)]=0;
659 dest[((*n)++)]=0;
660 }
661 }
662 }
663
664 // prepare a waveform pattern in the buffer based on the ID given then
665 // simulate a HID tag until the button is pressed
666 void CmdHIDsimTAG(int hi, int lo, uint8_t ledcontrol)
667 {
668 uint16_t n = 0, i = 0;
669 /*
670 HID tag bitstream format
671 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
672 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
673 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
674 A fc8 is inserted before every 4 bits
675 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
676 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
677 */
678
679 if (hi > 0xFFF) {
680 DbpString("Tags can only have 44 bits.");
681 return;
682 }
683 fc(0, &n);
684 // special start of frame marker containing invalid bit sequences
685 fc(8, &n); fc(8, &n); // invalid
686 fc(8, &n); fc(10, &n); // logical 0
687 fc(10, &n); fc(10, &n); // invalid
688 fc(8, &n); fc(10, &n); // logical 0
689
690 WDT_HIT();
691 // manchester encode bits 43 to 32
692 for (i = 11; i >= 0; i--) {
693 if ((i % 4) == 3) fc(0, &n);
694 if ((hi >> i) & 1) {
695 fc(10, &n); fc(8, &n); // low-high transition
696 } else {
697 fc(8, &n); fc(10, &n); // high-low transition
698 }
699 }
700
701 WDT_HIT();
702 // manchester encode bits 31 to 0
703 for (i = 31; i >= 0; i--) {
704 if ((i % 4 ) == 3) fc(0, &n);
705 if ((lo >> i ) & 1) {
706 fc(10, &n); fc(8, &n); // low-high transition
707 } else {
708 fc(8, &n); fc(10, &n); // high-low transition
709 }
710 }
711
712 if (ledcontrol)
713 LED_A_ON();
714
715 SimulateTagLowFrequency(n, 0, ledcontrol);
716
717 if (ledcontrol)
718 LED_A_OFF();
719 }
720
721 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
722 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
723 {
724 uint8_t *dest = (uint8_t *)BigBuf;
725 uint32_t hi2 = 0, hi = 0, lo = 0;
726
727 // Configure to go in 125Khz listen mode
728 LFSetupFPGAForADC(0, true);
729
730 while(!BUTTON_PRESS()) {
731
732 WDT_HIT();
733 if (ledcontrol) LED_A_ON();
734
735 DoAcquisition125k_internal(-1,true);
736
737 // FSK demodulator
738 int bitLen = HIDdemodFSK(dest,BIGBUF_SIZE,&hi2,&hi,&lo);
739
740 WDT_HIT();
741
742 if (bitLen > 0 && lo > 0){
743
744 // final loop, go over previously decoded manchester data and decode into usable tag ID
745 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
746
747 if (hi2 != 0){
748 //extra large HID tags
749 Dbprintf("TAG ID: %x%08x%08x (%d)",
750 (unsigned int) hi2,
751 (unsigned int) hi,
752 (unsigned int) lo,
753 (unsigned int) (lo >> 1) & 0xFFFF);
754
755 } else {
756 //standard HID tags <38 bits
757 uint8_t bitlen = 0;
758 uint32_t fc = 0;
759 uint32_t cardnum = 0;
760
761 if ((( hi >> 5 ) & 1) ==1){//if bit 38 is set then < 37 bit format is used
762 uint32_t lo2 = 0;
763 lo2 = (((hi & 31) << 12) | (lo >> 20)); //get bits 21-37 to check for format len bit
764 uint8_t idx3 = 1;
765 while(lo2 > 1){ //find last bit set to 1 (format len bit)
766 lo2 = lo2 >> 1;
767 idx3++;
768 }
769 bitlen =idx3 + 19;
770 fc = 0;
771 cardnum = 0;
772 if(bitlen == 26){
773 cardnum = (lo >> 1) & 0xFFFF;
774 fc = (lo >> 17) & 0xFF;
775 }
776 if(bitlen == 37){
777 cardnum = (lo >> 1) & 0x7FFFF;
778 fc = ((hi & 0xF) << 12)|( lo >> 20);
779 }
780 if(bitlen == 34){
781 cardnum = (lo >> 1) & 0xFFFF;
782 fc = ((hi & 1) << 15) | (lo >> 17);
783 }
784 if(bitlen == 35){
785 cardnum = (lo >> 1 ) & 0xFFFFF;
786 fc = ((hi & 1) << 11 ) | ( lo >> 21);
787 }
788 }
789 else { //if bit 38 is not set then 37 bit format is used
790 bitlen = 37;
791 fc = 0;
792 cardnum = 0;
793 if(bitlen == 37){
794 cardnum = ( lo >> 1) & 0x7FFFF;
795 fc = ((hi & 0xF) << 12 ) |(lo >> 20);
796 }
797 }
798 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
799 (unsigned int) hi,
800 (unsigned int) lo,
801 (unsigned int) (lo >> 1) & 0xFFFF,
802 (unsigned int) bitlen,
803 (unsigned int) fc,
804 (unsigned int) cardnum);
805 }
806 if (findone){
807 if (ledcontrol) LED_A_OFF();
808 return;
809 }
810 // reset
811 hi2 = hi = lo = 0;
812 }
813 WDT_HIT();
814 }
815 DbpString("Stopped");
816 if (ledcontrol) LED_A_OFF();
817 }
818
819 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
820 {
821 uint8_t *dest = (uint8_t *)BigBuf;
822 uint32_t bitLen = 0;
823 int clk = 0, invert = 0, errCnt = 0;
824 uint64_t lo = 0;
825
826 // Configure to go in 125Khz listen mode
827 LFSetupFPGAForADC(0, true);
828
829 while(!BUTTON_PRESS()) {
830
831 WDT_HIT();
832 if (ledcontrol) LED_A_ON();
833
834 DoAcquisition125k_internal(-1,true);
835
836 // FSK demodulator
837 bitLen = BIGBUF_SIZE;
838 errCnt = askmandemod(dest,&bitLen,&clk,&invert);
839 if ( errCnt < 0 ) continue;
840
841 WDT_HIT();
842
843 lo = Em410xDecode(dest,bitLen);
844
845 if ( lo <= 0) continue;
846
847 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
848 (uint32_t)(lo >> 32),
849 (uint32_t)lo,
850 (uint32_t)(lo & 0xFFFF),
851 (uint32_t)((lo >> 16LL) & 0xFF),
852 (uint32_t)(lo & 0xFFFFFF)
853 );
854
855 if (findone){
856 if (ledcontrol) LED_A_OFF();
857 return;
858 }
859
860 WDT_HIT();
861 lo = clk = invert = errCnt = 0;
862 }
863 DbpString("Stopped");
864 if (ledcontrol) LED_A_OFF();
865 }
866
867 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
868 {
869 uint8_t *dest = (uint8_t *)BigBuf;
870 int idx = 0;
871 uint32_t code = 0, code2 = 0;
872 uint8_t version = 0;
873 uint8_t facilitycode = 0;
874 uint16_t number = 0;
875
876 LFSetupFPGAForADC(0, true);
877
878 while(!BUTTON_PRESS()) {
879
880 WDT_HIT();
881 if (ledcontrol) LED_A_ON();
882
883 DoAcquisition125k_internal(-1, true);
884
885 idx = IOdemodFSK(dest, BIGBUF_SIZE);
886
887 if ( idx < 0 )
888 continue;
889
890 WDT_HIT();
891
892 //Index map
893 //0 10 20 30 40 50 60
894 //| | | | | | |
895 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
896 //-----------------------------------------------------------------------------
897 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
898 //
899 //XSF(version)facility:codeone+codetwo
900 //Handle the data
901
902 if(findone){ //only print binary if we are doing one
903 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
904 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
905 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
906 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
907 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
908 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
909 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
910 }
911
912 code = bytebits_to_byte(dest+idx,32);
913 code2 = bytebits_to_byte(dest+idx+32,32);
914 version = bytebits_to_byte(dest+idx+27,8); //14,4
915 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
916 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
917
918 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)", version, facilitycode, number, code, code2);
919 if (findone){
920 if (ledcontrol) LED_A_OFF();
921 return;
922 }
923 code = code2 = 0;
924 version = facilitycode = 0;
925 number = 0;
926 idx = 0;
927 }
928
929 DbpString("Stopped");
930 if (ledcontrol) LED_A_OFF();
931 }
932
933 /*------------------------------
934 * T5555/T5557/T5567 routines
935 *------------------------------
936 */
937
938 /* T55x7 configuration register definitions */
939 #define T55x7_POR_DELAY 0x00000001
940 #define T55x7_ST_TERMINATOR 0x00000008
941 #define T55x7_PWD 0x00000010
942 #define T55x7_MAXBLOCK_SHIFT 5
943 #define T55x7_AOR 0x00000200
944 #define T55x7_PSKCF_RF_2 0
945 #define T55x7_PSKCF_RF_4 0x00000400
946 #define T55x7_PSKCF_RF_8 0x00000800
947 #define T55x7_MODULATION_DIRECT 0
948 #define T55x7_MODULATION_PSK1 0x00001000
949 #define T55x7_MODULATION_PSK2 0x00002000
950 #define T55x7_MODULATION_PSK3 0x00003000
951 #define T55x7_MODULATION_FSK1 0x00004000
952 #define T55x7_MODULATION_FSK2 0x00005000
953 #define T55x7_MODULATION_FSK1a 0x00006000
954 #define T55x7_MODULATION_FSK2a 0x00007000
955 #define T55x7_MODULATION_MANCHESTER 0x00008000
956 #define T55x7_MODULATION_BIPHASE 0x00010000
957 #define T55x7_BITRATE_RF_8 0
958 #define T55x7_BITRATE_RF_16 0x00040000
959 #define T55x7_BITRATE_RF_32 0x00080000
960 #define T55x7_BITRATE_RF_40 0x000C0000
961 #define T55x7_BITRATE_RF_50 0x00100000
962 #define T55x7_BITRATE_RF_64 0x00140000
963 #define T55x7_BITRATE_RF_100 0x00180000
964 #define T55x7_BITRATE_RF_128 0x001C0000
965
966 /* T5555 (Q5) configuration register definitions */
967 #define T5555_ST_TERMINATOR 0x00000001
968 #define T5555_MAXBLOCK_SHIFT 0x00000001
969 #define T5555_MODULATION_MANCHESTER 0
970 #define T5555_MODULATION_PSK1 0x00000010
971 #define T5555_MODULATION_PSK2 0x00000020
972 #define T5555_MODULATION_PSK3 0x00000030
973 #define T5555_MODULATION_FSK1 0x00000040
974 #define T5555_MODULATION_FSK2 0x00000050
975 #define T5555_MODULATION_BIPHASE 0x00000060
976 #define T5555_MODULATION_DIRECT 0x00000070
977 #define T5555_INVERT_OUTPUT 0x00000080
978 #define T5555_PSK_RF_2 0
979 #define T5555_PSK_RF_4 0x00000100
980 #define T5555_PSK_RF_8 0x00000200
981 #define T5555_USE_PWD 0x00000400
982 #define T5555_USE_AOR 0x00000800
983 #define T5555_BITRATE_SHIFT 12
984 #define T5555_FAST_WRITE 0x00004000
985 #define T5555_PAGE_SELECT 0x00008000
986
987 /*
988 * Relevant times in microsecond
989 * To compensate antenna falling times shorten the write times
990 * and enlarge the gap ones.
991 */
992 #define START_GAP 30*8 // 10 - 50fc 250
993 #define WRITE_GAP 20*8 // 8 - 30fc
994 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
995 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
996
997 // VALUES TAKEN FROM EM4x function: SendForward
998 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
999 // WRITE_GAP = 128; (16*8)
1000 // WRITE_1 = 256 32*8; (32*8)
1001
1002 // These timings work for 4469/4269/4305 (with the 55*8 above)
1003 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1004
1005 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1006
1007 // Write one bit to card
1008 void T55xxWriteBit(int bit)
1009 {
1010 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1011 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1012 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1013 if (!bit)
1014 SpinDelayUs(WRITE_0);
1015 else
1016 SpinDelayUs(WRITE_1);
1017 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1018 SpinDelayUs(WRITE_GAP);
1019 }
1020
1021 // Write one card block in page 0, no lock
1022 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1023 {
1024 uint32_t i = 0;
1025
1026 // Set up FPGA, 125kHz
1027 // Wait for config.. (192+8190xPOW)x8 == 67ms
1028 LFSetupFPGAForADC(0, true);
1029
1030 // Now start writting
1031 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1032 SpinDelayUs(START_GAP);
1033
1034 // Opcode
1035 T55xxWriteBit(1);
1036 T55xxWriteBit(0); //Page 0
1037 if (PwdMode == 1){
1038 // Pwd
1039 for (i = 0x80000000; i != 0; i >>= 1)
1040 T55xxWriteBit(Pwd & i);
1041 }
1042 // Lock bit
1043 T55xxWriteBit(0);
1044
1045 // Data
1046 for (i = 0x80000000; i != 0; i >>= 1)
1047 T55xxWriteBit(Data & i);
1048
1049 // Block
1050 for (i = 0x04; i != 0; i >>= 1)
1051 T55xxWriteBit(Block & i);
1052
1053 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1054 // so wait a little more)
1055 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1056 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1057 SpinDelay(20);
1058 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1059 }
1060
1061 // Read one card block in page 0
1062 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1063 {
1064 uint8_t *dest = get_bigbufptr_recvrespbuf();
1065 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1066 uint32_t i = 0;
1067
1068 // Clear destination buffer before sending the command 0x80 = average.
1069 memset(dest, 0x80, bufferlength);
1070
1071 // Set up FPGA, 125kHz
1072 // Wait for config.. (192+8190xPOW)x8 == 67ms
1073 LFSetupFPGAForADC(0, true);
1074
1075 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1076 SpinDelayUs(START_GAP);
1077
1078 // Opcode
1079 T55xxWriteBit(1);
1080 T55xxWriteBit(0); //Page 0
1081 if (PwdMode == 1){
1082 // Pwd
1083 for (i = 0x80000000; i != 0; i >>= 1)
1084 T55xxWriteBit(Pwd & i);
1085 }
1086 // Lock bit
1087 T55xxWriteBit(0);
1088 // Block
1089 for (i = 0x04; i != 0; i >>= 1)
1090 T55xxWriteBit(Block & i);
1091
1092 // Turn field on to read the response
1093 TurnReadLFOn();
1094
1095 // Now do the acquisition
1096 i = 0;
1097 for(;;) {
1098 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1099 AT91C_BASE_SSC->SSC_THR = 0x43;
1100 //AT91C_BASE_SSC->SSC_THR = 0xff;
1101 LED_D_ON();
1102 }
1103 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1104 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1105 ++i;
1106 LED_D_OFF();
1107 if (i >= bufferlength) break;
1108 }
1109 }
1110
1111 cmd_send(CMD_ACK,0,0,0,0,0);
1112 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1113 LED_D_OFF();
1114 }
1115
1116 // Read card traceability data (page 1)
1117 void T55xxReadTrace(void){
1118 uint8_t *dest = get_bigbufptr_recvrespbuf();
1119 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1120 uint32_t i = 0;
1121
1122 // Clear destination buffer before sending the command 0x80 = average
1123 memset(dest, 0x80, bufferlength);
1124
1125 LFSetupFPGAForADC(0, true);
1126
1127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1128 SpinDelayUs(START_GAP);
1129
1130 // Opcode
1131 T55xxWriteBit(1);
1132 T55xxWriteBit(1); //Page 1
1133
1134 // Turn field on to read the response
1135 TurnReadLFOn();
1136
1137 // Now do the acquisition
1138 for(;;) {
1139 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1140 AT91C_BASE_SSC->SSC_THR = 0x43;
1141 LED_D_ON();
1142 }
1143 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1144 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1145 ++i;
1146 LED_D_OFF();
1147
1148 if (i >= bufferlength) break;
1149 }
1150 }
1151
1152 cmd_send(CMD_ACK,0,0,0,0,0);
1153 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1154 LED_D_OFF();
1155 }
1156
1157 void TurnReadLFOn(){
1158 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1159 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1160 // Give it a bit of time for the resonant antenna to settle.
1161 //SpinDelay(30);
1162 SpinDelayUs(8*150);
1163 }
1164
1165 /*-------------- Cloning routines -----------*/
1166 // Copy HID id to card and setup block 0 config
1167 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1168 {
1169 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1170 int last_block = 0;
1171
1172 if (longFMT){
1173 // Ensure no more than 84 bits supplied
1174 if (hi2>0xFFFFF) {
1175 DbpString("Tags can only have 84 bits.");
1176 return;
1177 }
1178 // Build the 6 data blocks for supplied 84bit ID
1179 last_block = 6;
1180 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1181 for (int i=0;i<4;i++) {
1182 if (hi2 & (1<<(19-i)))
1183 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1184 else
1185 data1 |= (1<<((3-i)*2)); // 0 -> 01
1186 }
1187
1188 data2 = 0;
1189 for (int i=0;i<16;i++) {
1190 if (hi2 & (1<<(15-i)))
1191 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1192 else
1193 data2 |= (1<<((15-i)*2)); // 0 -> 01
1194 }
1195
1196 data3 = 0;
1197 for (int i=0;i<16;i++) {
1198 if (hi & (1<<(31-i)))
1199 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1200 else
1201 data3 |= (1<<((15-i)*2)); // 0 -> 01
1202 }
1203
1204 data4 = 0;
1205 for (int i=0;i<16;i++) {
1206 if (hi & (1<<(15-i)))
1207 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1208 else
1209 data4 |= (1<<((15-i)*2)); // 0 -> 01
1210 }
1211
1212 data5 = 0;
1213 for (int i=0;i<16;i++) {
1214 if (lo & (1<<(31-i)))
1215 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1216 else
1217 data5 |= (1<<((15-i)*2)); // 0 -> 01
1218 }
1219
1220 data6 = 0;
1221 for (int i=0;i<16;i++) {
1222 if (lo & (1<<(15-i)))
1223 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1224 else
1225 data6 |= (1<<((15-i)*2)); // 0 -> 01
1226 }
1227 }
1228 else {
1229 // Ensure no more than 44 bits supplied
1230 if (hi>0xFFF) {
1231 DbpString("Tags can only have 44 bits.");
1232 return;
1233 }
1234
1235 // Build the 3 data blocks for supplied 44bit ID
1236 last_block = 3;
1237
1238 data1 = 0x1D000000; // load preamble
1239
1240 for (int i=0;i<12;i++) {
1241 if (hi & (1<<(11-i)))
1242 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1243 else
1244 data1 |= (1<<((11-i)*2)); // 0 -> 01
1245 }
1246
1247 data2 = 0;
1248 for (int i=0;i<16;i++) {
1249 if (lo & (1<<(31-i)))
1250 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1251 else
1252 data2 |= (1<<((15-i)*2)); // 0 -> 01
1253 }
1254
1255 data3 = 0;
1256 for (int i=0;i<16;i++) {
1257 if (lo & (1<<(15-i)))
1258 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1259 else
1260 data3 |= (1<<((15-i)*2)); // 0 -> 01
1261 }
1262 }
1263
1264 LED_D_ON();
1265 // Program the data blocks for supplied ID
1266 // and the block 0 for HID format
1267 T55xxWriteBlock(data1,1,0,0);
1268 T55xxWriteBlock(data2,2,0,0);
1269 T55xxWriteBlock(data3,3,0,0);
1270
1271 if (longFMT) { // if long format there are 6 blocks
1272 T55xxWriteBlock(data4,4,0,0);
1273 T55xxWriteBlock(data5,5,0,0);
1274 T55xxWriteBlock(data6,6,0,0);
1275 }
1276
1277 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1278 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1279 T55x7_MODULATION_FSK2a |
1280 last_block << T55x7_MAXBLOCK_SHIFT,
1281 0,0,0);
1282
1283 LED_D_OFF();
1284
1285 DbpString("DONE!");
1286 }
1287
1288 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1289 {
1290 int data1=0, data2=0; //up to six blocks for long format
1291
1292 data1 = hi; // load preamble
1293 data2 = lo;
1294
1295 LED_D_ON();
1296 // Program the data blocks for supplied ID
1297 // and the block 0 for HID format
1298 T55xxWriteBlock(data1,1,0,0);
1299 T55xxWriteBlock(data2,2,0,0);
1300
1301 //Config Block
1302 T55xxWriteBlock(0x00147040,0,0,0);
1303 LED_D_OFF();
1304
1305 DbpString("DONE!");
1306 }
1307
1308 // Define 9bit header for EM410x tags
1309 #define EM410X_HEADER 0x1FF
1310 #define EM410X_ID_LENGTH 40
1311
1312 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1313 {
1314 int i, id_bit;
1315 uint64_t id = EM410X_HEADER;
1316 uint64_t rev_id = 0; // reversed ID
1317 int c_parity[4]; // column parity
1318 int r_parity = 0; // row parity
1319 uint32_t clock = 0;
1320
1321 // Reverse ID bits given as parameter (for simpler operations)
1322 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1323 if (i < 32) {
1324 rev_id = (rev_id << 1) | (id_lo & 1);
1325 id_lo >>= 1;
1326 } else {
1327 rev_id = (rev_id << 1) | (id_hi & 1);
1328 id_hi >>= 1;
1329 }
1330 }
1331
1332 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1333 id_bit = rev_id & 1;
1334
1335 if (i % 4 == 0) {
1336 // Don't write row parity bit at start of parsing
1337 if (i)
1338 id = (id << 1) | r_parity;
1339 // Start counting parity for new row
1340 r_parity = id_bit;
1341 } else {
1342 // Count row parity
1343 r_parity ^= id_bit;
1344 }
1345
1346 // First elements in column?
1347 if (i < 4)
1348 // Fill out first elements
1349 c_parity[i] = id_bit;
1350 else
1351 // Count column parity
1352 c_parity[i % 4] ^= id_bit;
1353
1354 // Insert ID bit
1355 id = (id << 1) | id_bit;
1356 rev_id >>= 1;
1357 }
1358
1359 // Insert parity bit of last row
1360 id = (id << 1) | r_parity;
1361
1362 // Fill out column parity at the end of tag
1363 for (i = 0; i < 4; ++i)
1364 id = (id << 1) | c_parity[i];
1365
1366 // Add stop bit
1367 id <<= 1;
1368
1369 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1370 LED_D_ON();
1371
1372 // Write EM410x ID
1373 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1374 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1375
1376 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1377 if (card) {
1378 // Clock rate is stored in bits 8-15 of the card value
1379 clock = (card & 0xFF00) >> 8;
1380 Dbprintf("Clock rate: %d", clock);
1381 switch (clock)
1382 {
1383 case 32:
1384 clock = T55x7_BITRATE_RF_32;
1385 break;
1386 case 16:
1387 clock = T55x7_BITRATE_RF_16;
1388 break;
1389 case 0:
1390 // A value of 0 is assumed to be 64 for backwards-compatibility
1391 // Fall through...
1392 case 64:
1393 clock = T55x7_BITRATE_RF_64;
1394 break;
1395 default:
1396 Dbprintf("Invalid clock rate: %d", clock);
1397 return;
1398 }
1399
1400 // Writing configuration for T55x7 tag
1401 T55xxWriteBlock(clock |
1402 T55x7_MODULATION_MANCHESTER |
1403 2 << T55x7_MAXBLOCK_SHIFT,
1404 0, 0, 0);
1405 }
1406 else
1407 // Writing configuration for T5555(Q5) tag
1408 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1409 T5555_MODULATION_MANCHESTER |
1410 2 << T5555_MAXBLOCK_SHIFT,
1411 0, 0, 0);
1412
1413 LED_D_OFF();
1414 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1415 (uint32_t)(id >> 32), (uint32_t)id);
1416 }
1417
1418 // Clone Indala 64-bit tag by UID to T55x7
1419 void CopyIndala64toT55x7(int hi, int lo)
1420 {
1421 //Program the 2 data blocks for supplied 64bit UID
1422 // and the block 0 for Indala64 format
1423 T55xxWriteBlock(hi,1,0,0);
1424 T55xxWriteBlock(lo,2,0,0);
1425 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1426 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1427 T55x7_MODULATION_PSK1 |
1428 2 << T55x7_MAXBLOCK_SHIFT,
1429 0, 0, 0);
1430 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1431 // T5567WriteBlock(0x603E1042,0);
1432
1433 DbpString("DONE!");
1434 }
1435
1436 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1437 {
1438 //Program the 7 data blocks for supplied 224bit UID
1439 // and the block 0 for Indala224 format
1440 T55xxWriteBlock(uid1,1,0,0);
1441 T55xxWriteBlock(uid2,2,0,0);
1442 T55xxWriteBlock(uid3,3,0,0);
1443 T55xxWriteBlock(uid4,4,0,0);
1444 T55xxWriteBlock(uid5,5,0,0);
1445 T55xxWriteBlock(uid6,6,0,0);
1446 T55xxWriteBlock(uid7,7,0,0);
1447 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1448 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1449 T55x7_MODULATION_PSK1 |
1450 7 << T55x7_MAXBLOCK_SHIFT,
1451 0,0,0);
1452 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1453 // T5567WriteBlock(0x603E10E2,0);
1454
1455 DbpString("DONE!");
1456 }
1457
1458
1459 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1460 #define max(x,y) ( x<y ? y:x)
1461
1462 int DemodPCF7931(uint8_t **outBlocks) {
1463 uint8_t BitStream[256];
1464 uint8_t Blocks[8][16];
1465 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1466 int GraphTraceLen = sizeof(BigBuf);
1467 int i, j, lastval, bitidx, half_switch;
1468 int clock = 64;
1469 int tolerance = clock / 8;
1470 int pmc, block_done;
1471 int lc, warnings = 0;
1472 int num_blocks = 0;
1473 int lmin=128, lmax=128;
1474 uint8_t dir;
1475
1476 AcquireRawAdcSamples125k(0);
1477
1478 lmin = 64;
1479 lmax = 192;
1480
1481 i = 2;
1482
1483 /* Find first local max/min */
1484 if(GraphBuffer[1] > GraphBuffer[0]) {
1485 while(i < GraphTraceLen) {
1486 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1487 break;
1488 i++;
1489 }
1490 dir = 0;
1491 }
1492 else {
1493 while(i < GraphTraceLen) {
1494 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1495 break;
1496 i++;
1497 }
1498 dir = 1;
1499 }
1500
1501 lastval = i++;
1502 half_switch = 0;
1503 pmc = 0;
1504 block_done = 0;
1505
1506 for (bitidx = 0; i < GraphTraceLen; i++)
1507 {
1508 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1509 {
1510 lc = i - lastval;
1511 lastval = i;
1512
1513 // Switch depending on lc length:
1514 // Tolerance is 1/8 of clock rate (arbitrary)
1515 if (abs(lc-clock/4) < tolerance) {
1516 // 16T0
1517 if((i - pmc) == lc) { /* 16T0 was previous one */
1518 /* It's a PMC ! */
1519 i += (128+127+16+32+33+16)-1;
1520 lastval = i;
1521 pmc = 0;
1522 block_done = 1;
1523 }
1524 else {
1525 pmc = i;
1526 }
1527 } else if (abs(lc-clock/2) < tolerance) {
1528 // 32TO
1529 if((i - pmc) == lc) { /* 16T0 was previous one */
1530 /* It's a PMC ! */
1531 i += (128+127+16+32+33)-1;
1532 lastval = i;
1533 pmc = 0;
1534 block_done = 1;
1535 }
1536 else if(half_switch == 1) {
1537 BitStream[bitidx++] = 0;
1538 half_switch = 0;
1539 }
1540 else
1541 half_switch++;
1542 } else if (abs(lc-clock) < tolerance) {
1543 // 64TO
1544 BitStream[bitidx++] = 1;
1545 } else {
1546 // Error
1547 warnings++;
1548 if (warnings > 10)
1549 {
1550 Dbprintf("Error: too many detection errors, aborting.");
1551 return 0;
1552 }
1553 }
1554
1555 if(block_done == 1) {
1556 if(bitidx == 128) {
1557 for(j=0; j<16; j++) {
1558 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1559 64*BitStream[j*8+6]+
1560 32*BitStream[j*8+5]+
1561 16*BitStream[j*8+4]+
1562 8*BitStream[j*8+3]+
1563 4*BitStream[j*8+2]+
1564 2*BitStream[j*8+1]+
1565 BitStream[j*8];
1566 }
1567 num_blocks++;
1568 }
1569 bitidx = 0;
1570 block_done = 0;
1571 half_switch = 0;
1572 }
1573 if(i < GraphTraceLen)
1574 {
1575 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1576 else dir = 1;
1577 }
1578 }
1579 if(bitidx==255)
1580 bitidx=0;
1581 warnings = 0;
1582 if(num_blocks == 4) break;
1583 }
1584 memcpy(outBlocks, Blocks, 16*num_blocks);
1585 return num_blocks;
1586 }
1587
1588 int IsBlock0PCF7931(uint8_t *Block) {
1589 // Assume RFU means 0 :)
1590 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1591 return 1;
1592 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1593 return 1;
1594 return 0;
1595 }
1596
1597 int IsBlock1PCF7931(uint8_t *Block) {
1598 // Assume RFU means 0 :)
1599 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1600 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1601 return 1;
1602
1603 return 0;
1604 }
1605 #define ALLOC 16
1606
1607 void ReadPCF7931() {
1608 uint8_t Blocks[8][17];
1609 uint8_t tmpBlocks[4][16];
1610 int i, j, ind, ind2, n;
1611 int num_blocks = 0;
1612 int max_blocks = 8;
1613 int ident = 0;
1614 int error = 0;
1615 int tries = 0;
1616
1617 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1618
1619 do {
1620 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1621 n = DemodPCF7931((uint8_t**)tmpBlocks);
1622 if(!n)
1623 error++;
1624 if(error==10 && num_blocks == 0) {
1625 Dbprintf("Error, no tag or bad tag");
1626 return;
1627 }
1628 else if (tries==20 || error==10) {
1629 Dbprintf("Error reading the tag");
1630 Dbprintf("Here is the partial content");
1631 goto end;
1632 }
1633
1634 for(i=0; i<n; i++)
1635 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1636 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1637 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1638 if(!ident) {
1639 for(i=0; i<n; i++) {
1640 if(IsBlock0PCF7931(tmpBlocks[i])) {
1641 // Found block 0 ?
1642 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1643 // Found block 1!
1644 // \o/
1645 ident = 1;
1646 memcpy(Blocks[0], tmpBlocks[i], 16);
1647 Blocks[0][ALLOC] = 1;
1648 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1649 Blocks[1][ALLOC] = 1;
1650 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1651 // Debug print
1652 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1653 num_blocks = 2;
1654 // Handle following blocks
1655 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1656 if(j==n) j=0;
1657 if(j==i) break;
1658 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1659 Blocks[ind2][ALLOC] = 1;
1660 }
1661 break;
1662 }
1663 }
1664 }
1665 }
1666 else {
1667 for(i=0; i<n; i++) { // Look for identical block in known blocks
1668 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1669 for(j=0; j<max_blocks; j++) {
1670 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1671 // Found an identical block
1672 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1673 if(ind2 < 0)
1674 ind2 = max_blocks;
1675 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1676 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1677 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1678 Blocks[ind2][ALLOC] = 1;
1679 num_blocks++;
1680 if(num_blocks == max_blocks) goto end;
1681 }
1682 }
1683 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1684 if(ind2 > max_blocks)
1685 ind2 = 0;
1686 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1687 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1688 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1689 Blocks[ind2][ALLOC] = 1;
1690 num_blocks++;
1691 if(num_blocks == max_blocks) goto end;
1692 }
1693 }
1694 }
1695 }
1696 }
1697 }
1698 }
1699 tries++;
1700 if (BUTTON_PRESS()) return;
1701 } while (num_blocks != max_blocks);
1702 end:
1703 Dbprintf("-----------------------------------------");
1704 Dbprintf("Memory content:");
1705 Dbprintf("-----------------------------------------");
1706 for(i=0; i<max_blocks; i++) {
1707 if(Blocks[i][ALLOC]==1)
1708 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1709 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1710 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1711 else
1712 Dbprintf("<missing block %d>", i);
1713 }
1714 Dbprintf("-----------------------------------------");
1715
1716 return ;
1717 }
1718
1719
1720 //-----------------------------------
1721 // EM4469 / EM4305 routines
1722 //-----------------------------------
1723 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1724 #define FWD_CMD_WRITE 0xA
1725 #define FWD_CMD_READ 0x9
1726 #define FWD_CMD_DISABLE 0x5
1727
1728
1729 uint8_t forwardLink_data[64]; //array of forwarded bits
1730 uint8_t * forward_ptr; //ptr for forward message preparation
1731 uint8_t fwd_bit_sz; //forwardlink bit counter
1732 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1733
1734 //====================================================================
1735 // prepares command bits
1736 // see EM4469 spec
1737 //====================================================================
1738 //--------------------------------------------------------------------
1739 uint8_t Prepare_Cmd( uint8_t cmd ) {
1740 //--------------------------------------------------------------------
1741
1742 *forward_ptr++ = 0; //start bit
1743 *forward_ptr++ = 0; //second pause for 4050 code
1744
1745 *forward_ptr++ = cmd;
1746 cmd >>= 1;
1747 *forward_ptr++ = cmd;
1748 cmd >>= 1;
1749 *forward_ptr++ = cmd;
1750 cmd >>= 1;
1751 *forward_ptr++ = cmd;
1752
1753 return 6; //return number of emited bits
1754 }
1755
1756 //====================================================================
1757 // prepares address bits
1758 // see EM4469 spec
1759 //====================================================================
1760
1761 //--------------------------------------------------------------------
1762 uint8_t Prepare_Addr( uint8_t addr ) {
1763 //--------------------------------------------------------------------
1764
1765 register uint8_t line_parity;
1766
1767 uint8_t i;
1768 line_parity = 0;
1769 for(i=0;i<6;i++) {
1770 *forward_ptr++ = addr;
1771 line_parity ^= addr;
1772 addr >>= 1;
1773 }
1774
1775 *forward_ptr++ = (line_parity & 1);
1776
1777 return 7; //return number of emited bits
1778 }
1779
1780 //====================================================================
1781 // prepares data bits intreleaved with parity bits
1782 // see EM4469 spec
1783 //====================================================================
1784
1785 //--------------------------------------------------------------------
1786 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1787 //--------------------------------------------------------------------
1788
1789 register uint8_t line_parity;
1790 register uint8_t column_parity;
1791 register uint8_t i, j;
1792 register uint16_t data;
1793
1794 data = data_low;
1795 column_parity = 0;
1796
1797 for(i=0; i<4; i++) {
1798 line_parity = 0;
1799 for(j=0; j<8; j++) {
1800 line_parity ^= data;
1801 column_parity ^= (data & 1) << j;
1802 *forward_ptr++ = data;
1803 data >>= 1;
1804 }
1805 *forward_ptr++ = line_parity;
1806 if(i == 1)
1807 data = data_hi;
1808 }
1809
1810 for(j=0; j<8; j++) {
1811 *forward_ptr++ = column_parity;
1812 column_parity >>= 1;
1813 }
1814 *forward_ptr = 0;
1815
1816 return 45; //return number of emited bits
1817 }
1818
1819 //====================================================================
1820 // Forward Link send function
1821 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1822 // fwd_bit_count set with number of bits to be sent
1823 //====================================================================
1824 void SendForward(uint8_t fwd_bit_count) {
1825
1826 fwd_write_ptr = forwardLink_data;
1827 fwd_bit_sz = fwd_bit_count;
1828
1829 LED_D_ON();
1830
1831 //Field on
1832 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1833 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1834 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1835
1836 // Give it a bit of time for the resonant antenna to settle.
1837 // And for the tag to fully power up
1838 SpinDelay(150);
1839
1840 // force 1st mod pulse (start gap must be longer for 4305)
1841 fwd_bit_sz--; //prepare next bit modulation
1842 fwd_write_ptr++;
1843 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1844 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1845 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1846 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1847 SpinDelayUs(16*8); //16 cycles on (8us each)
1848
1849 // now start writting
1850 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1851 if(((*fwd_write_ptr++) & 1) == 1)
1852 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1853 else {
1854 //These timings work for 4469/4269/4305 (with the 55*8 above)
1855 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1856 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1857 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1858 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1859 SpinDelayUs(9*8); //16 cycles on (8us each)
1860 }
1861 }
1862 }
1863
1864
1865 void EM4xLogin(uint32_t Password) {
1866
1867 uint8_t fwd_bit_count;
1868
1869 forward_ptr = forwardLink_data;
1870 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1871 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1872
1873 SendForward(fwd_bit_count);
1874
1875 //Wait for command to complete
1876 SpinDelay(20);
1877
1878 }
1879
1880 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1881
1882 uint8_t *dest = (uint8_t *)BigBuf;
1883 uint16_t bufferlength = 12000;
1884 uint32_t i = 0;
1885
1886 // Clear destination buffer before sending the command 0x80 = average.
1887 memset(dest, 0x80, bufferlength);
1888
1889 uint8_t fwd_bit_count;
1890
1891 //If password mode do login
1892 if (PwdMode == 1) EM4xLogin(Pwd);
1893
1894 forward_ptr = forwardLink_data;
1895 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1896 fwd_bit_count += Prepare_Addr( Address );
1897
1898 // Connect the A/D to the peak-detected low-frequency path.
1899 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1900 // Now set up the SSC to get the ADC samples that are now streaming at us.
1901 FpgaSetupSsc();
1902
1903 SendForward(fwd_bit_count);
1904
1905 // // Turn field on to read the response
1906 // TurnReadLFOn();
1907
1908 // Now do the acquisition
1909 i = 0;
1910 for(;;) {
1911 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1912 AT91C_BASE_SSC->SSC_THR = 0x43;
1913 }
1914 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1915 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1916 ++i;
1917 if (i >= bufferlength) break;
1918 }
1919 }
1920
1921 cmd_send(CMD_ACK,0,0,0,0,0);
1922 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1923 LED_D_OFF();
1924 }
1925
1926 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1927
1928 uint8_t fwd_bit_count;
1929
1930 //If password mode do login
1931 if (PwdMode == 1) EM4xLogin(Pwd);
1932
1933 forward_ptr = forwardLink_data;
1934 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1935 fwd_bit_count += Prepare_Addr( Address );
1936 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1937
1938 SendForward(fwd_bit_count);
1939
1940 //Wait for write to complete
1941 SpinDelay(20);
1942 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1943 LED_D_OFF();
1944 }
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