cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/ticks.c

   1 //-----------------------------------------------------------------------------
   2 // Jonathan Westhues, Sept 2005
   3 // Iceman, Sept 2016
   4 //
   5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
   6 // at your option, any later version. See the LICENSE.txt file for the text of
   7 // the license.
   8 //-----------------------------------------------------------------------------
   9 // Timers, Clocks functions used in LF or Legic where you would need detailed time.
  10 //-----------------------------------------------------------------------------
  11
  12 #include "ticks.h"
  13
  14 // attempt at high resolution microsecond timer
  15 // beware: timer counts in 21.3uS increments (1024/48Mhz)
  16 void SpinDelayUs(int us) {
  17         int ticks = (48 * us) >> 10;
  18
  19         // Borrow a PWM unit for my real-time clock
  20         AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
  21
  22         // 48 MHz / 1024 gives 46.875 kHz
  23         AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
  24         AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
  25         AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
  26
  27         uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
  28
  29         for(;;) {
  30                 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
  31                 if (now == (uint16_t)(start + ticks))
  32                         return;
  33
  34                 WDT_HIT();
  35         }
  36 }
  37
  38 void SpinDelay(int ms) {
  39   // convert to uS and call microsecond delay function
  40         SpinDelayUs(ms*1000);
  41 }
  42 //  -------------------------------------------------------------------------
  43 //  timer lib
  44 //  -------------------------------------------------------------------------
  45 //  test procedure:
  46 //
  47 //      ti = GetTickCount();
  48 //      SpinDelay(1000);
  49 //      ti = GetTickCount() - ti;
  50 //      Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
  51
  52 void StartTickCount() {
  53         // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
  54         // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
  55     uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;         // = 16 * main clock frequency (16MHz) / slow clock frequency
  56         // set RealTimeCounter divider to count at 1kHz:
  57         AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
  58         // note: worst case precision is approx 2.5%
  59 }
  60
  61 /*
  62 * Get the current count.
  63 */
  64 uint32_t RAMFUNC GetTickCount(){
  65         return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
  66 }
  67
  68 //  -------------------------------------------------------------------------
  69 //  microseconds timer
  70 //  -------------------------------------------------------------------------
  71 void StartCountUS() {
  72         AT91C_BASE_PMC->PMC_PCER |= (1 << 12) | (1 << 13) | (1 << 14);
  73         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
  74
  75         // fast clock
  76         // tick=1.5mks
  77         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
  78         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
  79                                                                 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
  80                                                                 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
  81         AT91C_BASE_TC0->TC_RA = 1;
  82         AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
  83
  84         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
  85         AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
  86
  87         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
  88         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
  89         AT91C_BASE_TCB->TCB_BCR = 1;
  90
  91         while (AT91C_BASE_TC1->TC_CV >= 1);
  92 }
  93
  94 uint32_t RAMFUNC GetCountUS(){
  95         //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
  96         //  By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
  97         return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3);
  98 }
  99 void ResetUSClock(void) {
 100         //enable clock of timer and software trigger
 101         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 102         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 103         while (AT91C_BASE_TC1->TC_CV >= 1);
 104 }
 105 // attempt at high resolution microsecond timer
 106 // beware: timer counts in 21.3uS increments (1024/48Mhz)
 107 void SpinDelayCountUs(uint32_t us) {
 108         if (us < 8) return;
 109         us += GetCountUS();
 110         while ( GetCountUS() < us ){}
 111 }
 112 // static uint32_t GlobalUsCounter = 0;
 113 // uint32_t RAMFUNC GetDeltaCountUS(){
 114         // uint32_t g_cnt = GetCountUS();
 115         // uint32_t g_res = g_cnt - GlobalUsCounter;
 116         // GlobalUsCounter = g_cnt;
 117         // return g_res;
 118 // }
 119 //  -------------------------------------------------------------------------
 120 //  Timer for iso14443 commands. Uses ssp_clk from FPGA
 121 //  -------------------------------------------------------------------------
 122 void StartCountSspClk() {
 123         AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
 124         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1
 125                                                         | AT91C_TCB_TC1XC1S_NONE                // XC1 Clock = none
 126                                                         | AT91C_TCB_TC2XC2S_TIOA0;              // XC2 Clock = TIOA0
 127
 128         // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
 129         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC1
 130         AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
 131                                                         | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
 132                                                         | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event
 133                                                         | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
 134                                                         | AT91C_TC_ENETRG                               // Enable external trigger event
 135                                                         | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
 136                                                         | AT91C_TC_WAVE                                 // Waveform Mode
 137                                                         | AT91C_TC_AEEVT_SET                    // Set TIOA1 on external event
 138                                                         | AT91C_TC_ACPC_CLEAR;                  // Clear TIOA1 on RC Compare
 139         AT91C_BASE_TC1->TC_RC = 0x04;                                                   // RC Compare value = 0x04
 140
 141         // use TC0 to count TIOA1 pulses
 142         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0
 143         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0                              // TC0 clock = XC0 clock = TIOA1
 144                                                         | AT91C_TC_WAVE                                 // Waveform Mode
 145                                                         | AT91C_TC_WAVESEL_UP                   // just count
 146                                                         | AT91C_TC_ACPA_CLEAR                   // Clear TIOA0 on RA Compare
 147                                                         | AT91C_TC_ACPC_SET;                    // Set TIOA0 on RC Compare
 148         AT91C_BASE_TC0->TC_RA = 1;                                                              // RA Compare value = 1; pulse width to TC2
 149         AT91C_BASE_TC0->TC_RC = 0;                                                              // RC Compare value = 0; increment TC2 on overflow
 150
 151         // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
 152         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC2
 153         AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2                              // TC2 clock = XC2 clock = TIOA0
 154                                                         | AT91C_TC_WAVE                                 // Waveform Mode
 155                                                         | AT91C_TC_WAVESEL_UP;                  // just count
 156
 157         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC0
 158         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC1
 159         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC2
 160
 161         // synchronize the counter with the ssp_frame signal.
 162         // Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present
 163         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
 164         while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
 165         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high
 166
 167         // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
 168         // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
 169         AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)
 170         // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
 171         // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
 172         // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
 173         // (just started with the transfer of the 4th Bit).
 174
 175         // The high word of the counter (TC2) will not reset until the low word (TC0) overflows.
 176         // Therefore need to wait quite some time before we can use the counter.
 177         while (AT91C_BASE_TC2->TC_CV >= 1);
 178 }
 179 void ResetSspClk(void) {
 180         //enable clock of timer and software trigger
 181         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 182         AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 183         AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 184 }
 185
 186 uint32_t RAMFUNC GetCountSspClk(){
 187
 188         uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
 189         if ((tmp_count & 0x0000ffff) == 0)  //small chance that we may have missed an increment in TC2
 190                 return (AT91C_BASE_TC2->TC_CV << 16);
 191         return tmp_count;
 192 }
 193
 194
 195 void StartTicks(void){
 196         //initialization of the timer
 197         AT91C_BASE_PMC->PMC_PCER |= (1 << 12) | (1 << 13) | (1 << 14);
 198         AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
 199
 200         // fast clock TC0
 201         // tick=1.5mks
 202         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
 203         AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;  //clock at 48/32 MHz
 204
 205         // Enable and reset timer
 206         AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 207         AT91C_BASE_TCB->TCB_BCR = 1;
 208         // wait until timer becomes zero.
 209         while (AT91C_BASE_TC0->TC_CV > 1);
 210 }
 211 // Wait - Spindelay in ticks.
 212 // if called with a high number, this will trigger the WDT...
 213 void WaitTicks(uint32_t ticks){
 214         if ( ticks == 0 ) return;
 215         ticks += GET_TICKS;
 216         while (GET_TICKS < ticks);
 217 }
 218 // Wait / Spindelay in us (microseconds)
 219 // 1us = 1.5ticks.
 220 void WaitUS(uint16_t us){
 221         if ( us == 0 ) return;
 222         WaitTicks(  (uint32_t)(us * 1.5) );
 223 }
 224 void WaitMS(uint16_t ms){
 225         if (ms == 0) return;
 226         WaitTicks( (uint32_t)(ms * 1500) );
 227 }
 228 // Starts Clock and waits until its reset
 229 void ResetTicks(){
 230         ResetTimer(AT91C_BASE_TC0);
 231 }
 232 void ResetTimer(AT91PS_TC timer){
 233         timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 234         while(timer->TC_CV > 1) ;
 235 }