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1 //-----------------------------------------------------------------------------
2 // Incomplete register definitions for the AT91SAM7S128 chip.
3 // Jonathan Westhues, Jul 2005
4 //-----------------------------------------------------------------------------
5
6 #ifndef __AT91SAM7S128_H
7 #define __AT91SAM7S128_H
8
9 #define REG(x) (*(volatile unsigned long *)(x))
10
11 //-------------
12 // Peripheral IDs
13
14 #define PERIPH_AIC_FIQ 0
15 #define PERIPH_SYSIRQ 1
16 #define PERIPH_PIOA 2
17 #define PERIPH_ADC 4
18 #define PERIPH_SPI 5
19 #define PERIPH_US0 6
20 #define PERIPH_US1 7
21 #define PERIPH_SSC 8
22 #define PERIPH_TWI 9
23 #define PERIPH_PWMC 10
24 #define PERIPH_UDP 11
25 #define PERIPH_TC0 12
26 #define PERIPH_TC1 13
27 #define PERIPH_TC2 14
28 #define PERIPH_AIC_IRQ0 30
29 #define PERIPH_AIC_IRQ1 31
30
31 //-------------
32 // Reset Controller
33
34 #define RSTC_BASE (0xfffffd00)
35
36 #define RSTC_CONTROL REG(RSTC_BASE+0x00)
37
38 #define RST_CONTROL_KEY (0xa5<<24)
39 #define RST_CONTROL_PROCESSOR_RESET (1<<0)
40
41 //-------------
42 // PWM Controller
43
44 #define PWM_BASE (0xfffcc000)
45
46 #define PWM_MODE REG(PWM_BASE+0x00)
47 #define PWM_ENABLE REG(PWM_BASE+0x04)
48 #define PWM_DISABLE REG(PWM_BASE+0x08)
49 #define PWM_STATUS REG(PWM_BASE+0x0c)
50 #define PWM_INTERRUPT_ENABLE REG(PWM_BASE+0x10)
51 #define PWM_INTERRUPT_DISABLE REG(PWM_BASE+0x14)
52 #define PWM_INTERRUPT_MASK REG(PWM_BASE+0x18)
53 #define PWM_INTERRUPT_STATUS REG(PWM_BASE+0x1c)
54 #define PWM_CH_MODE(x) REG(PWM_BASE+0x200+((x)*0x20))
55 #define PWM_CH_DUTY_CYCLE(x) REG(PWM_BASE+0x204+((x)*0x20))
56 #define PWM_CH_PERIOD(x) REG(PWM_BASE+0x208+((x)*0x20))
57 #define PWM_CH_COUNTER(x) REG(PWM_BASE+0x20c+((x)*0x20))
58 #define PWM_CH_UPDATE(x) REG(PWM_BASE+0x210+((x)*0x20))
59
60 #define PWM_MODE_DIVA(x) ((x)<<0)
61 #define PWM_MODE_PREA(x) ((x)<<8)
62 #define PWM_MODE_DIVB(x) ((x)<<16)
63 #define PWM_MODE_PREB(x) ((x)<<24)
64
65 #define PWM_CHANNEL(x) (1<<(x))
66
67 #define PWM_CH_MODE_PRESCALER(x) ((x)<<0)
68 #define PWM_CH_MODE_PERIOD_CENTER_ALIGNED (1<<8)
69 #define PWM_CH_MODE_POLARITY_STARTS_HIGH (1<<9)
70 #define PWM_CH_MODE_UPDATE_UPDATES_PERIOD (1<<10)
71
72 //-------------
73 // Debug Unit
74
75 #define DBG_BASE (0xfffff200)
76
77 #define DBGU_CR REG(DBG_BASE+0x0000)
78 #define DBGU_MR REG(DBG_BASE+0x0004)
79 #define DBGU_IER REG(DBG_BASE+0x0008)
80 #define DBGU_IDR REG(DBG_BASE+0x000C)
81 #define DBGU_IMR REG(DBG_BASE+0x0010)
82 #define DBGU_SR REG(DBG_BASE+0x0014)
83 #define DBGU_RHR REG(DBG_BASE+0x0018)
84 #define DBGU_THR REG(DBG_BASE+0x001C)
85 #define DBGU_BRGR REG(DBG_BASE+0x0020)
86 #define DBGU_CIDR REG(DBG_BASE+0x0040)
87 #define DBGU_EXID REG(DBG_BASE+0x0044)
88 #define DBGU_FNR REG(DBG_BASE+0x0048)
89
90 //-------------
91 // Embedded Flash Controller
92
93 #define MC_BASE (0xffffff00)
94
95 #define MC_FLASH_MODE0 REG(MC_BASE+0x60)
96 #define MC_FLASH_COMMAND REG(MC_BASE+0x64)
97 #define MC_FLASH_STATUS REG(MC_BASE+0x68)
98 #define MC_FLASH_MODE1 REG(MC_BASE+0x70)
99
100 #define MC_FLASH_MODE_READY_INTERRUPT_ENABLE (1<<0)
101 #define MC_FLASH_MODE_LOCK_INTERRUPT_ENABLE (1<<2)
102 #define MC_FLASH_MODE_PROG_ERROR_INTERRUPT_ENABLE (1<<3)
103 #define MC_FLASH_MODE_NO_ERASE_BEFORE_PROGRAMMING (1<<7)
104 #define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)
105 #define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)
106
107 #define MC_FLASH_COMMAND_FCMD(x) ((x)<<0)
108 #define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)
109 #define MC_FLASH_COMMAND_KEY ((0x5a)<<24)
110
111 #define FCMD_NOP 0x0
112 #define FCMD_WRITE_PAGE 0x1
113 #define FCMD_SET_LOCK_BIT 0x2
114 #define FCMD_WRITE_PAGE_LOCK 0x3
115 #define FCMD_CLEAR_LOCK_BIT 0x4
116 #define FCMD_ERASE_ALL 0x8
117 #define FCMD_SET_GP_NVM_BIT 0xb
118 #define FCMD_SET_SECURITY_BIT 0xf
119
120 #define MC_FLASH_STATUS_READY (1<<0)
121 #define MC_FLASH_STATUS_LOCK_ERROR (1<<2)
122 #define MC_FLASH_STATUS_PROGRAMMING_ERROR (1<<3)
123 #define MC_FLASH_STATUS_SECURITY_BIT_ACTIVE (1<<4)
124 #define MC_FLASH_STATUS_GP_NVM_ACTIVE_0 (1<<8)
125 #define MC_FLASH_STATUS_GP_NVM_ACTIVE_1 (1<<9)
126 #define MC_FLASH_STATUS_LOCK_ACTIVE(x) (1<<((x)+16))
127
128 #define FLASH_PAGE_SIZE_BYTES 256
129 #define FLASH_PAGE_COUNT 512
130
131 //-------------
132 // Watchdog Timer - 12 bit down counter, uses slow clock divided by 128 as source
133
134 #define WDT_BASE (0xfffffd40)
135
136 #define WDT_CONTROL REG(WDT_BASE+0x00)
137 #define WDT_MODE REG(WDT_BASE+0x04)
138 #define WDT_STATUS REG(WDT_BASE+0x08)
139
140 #define WDT_HIT() WDT_CONTROL = 0xa5000001
141
142 #define WDT_MODE_COUNT(x) ((x)<<0)
143 #define WDT_MODE_INTERRUPT_ON_EVENT (1<<12)
144 #define WDT_MODE_RESET_ON_EVENT_ENABLE (1<<13)
145 #define WDT_MODE_RESET_ON_EVENT (1<<14)
146 #define WDT_MODE_WATCHDOG_DELTA(x) ((x)<<16)
147 #define WDT_MODE_HALT_IN_DEBUG_MODE (1<<28)
148 #define WDT_MODE_HALT_IN_IDLE_MODE (1<<29)
149 #define WDT_MODE_DISABLE (1<<15)
150
151 //-------------
152 // Parallel Input/Output Controller
153
154 #define PIO_BASE (0xfffff400)
155
156 #define PIO_ENABLE REG(PIO_BASE+0x000)
157 #define PIO_DISABLE REG(PIO_BASE+0x004)
158 #define PIO_STATUS REG(PIO_BASE+0x008)
159 #define PIO_OUTPUT_ENABLE REG(PIO_BASE+0x010)
160 #define PIO_OUTPUT_DISABLE REG(PIO_BASE+0x014)
161 #define PIO_OUTPUT_STATUS REG(PIO_BASE+0x018)
162 #define PIO_GLITCH_ENABLE REG(PIO_BASE+0x020)
163 #define PIO_GLITCH_DISABLE REG(PIO_BASE+0x024)
164 #define PIO_GLITCH_STATUS REG(PIO_BASE+0x028)
165 #define PIO_OUTPUT_DATA_SET REG(PIO_BASE+0x030)
166 #define PIO_OUTPUT_DATA_CLEAR REG(PIO_BASE+0x034)
167 #define PIO_OUTPUT_DATA_STATUS REG(PIO_BASE+0x038)
168 #define PIO_PIN_DATA_STATUS REG(PIO_BASE+0x03c)
169 #define PIO_OPEN_DRAIN_ENABLE REG(PIO_BASE+0x050)
170 #define PIO_OPEN_DRAIN_DISABLE REG(PIO_BASE+0x054)
171 #define PIO_OPEN_DRAIN_STATUS REG(PIO_BASE+0x058)
172 #define PIO_NO_PULL_UP_ENABLE REG(PIO_BASE+0x060)
173 #define PIO_NO_PULL_UP_DISABLE REG(PIO_BASE+0x064)
174 #define PIO_NO_PULL_UP_STATUS REG(PIO_BASE+0x068)
175 #define PIO_PERIPHERAL_A_SEL REG(PIO_BASE+0x070)
176 #define PIO_PERIPHERAL_B_SEL REG(PIO_BASE+0x074)
177 #define PIO_PERIPHERAL_WHICH REG(PIO_BASE+0x078)
178 #define PIO_OUT_WRITE_ENABLE REG(PIO_BASE+0x0a0)
179 #define PIO_OUT_WRITE_DISABLE REG(PIO_BASE+0x0a4)
180 #define PIO_OUT_WRITE_STATUS REG(PIO_BASE+0x0a8)
181
182 //-------------
183 // USB Device Port
184
185 #define UDP_BASE (0xfffb0000)
186
187 #define UDP_FRAME_NUMBER REG(UDP_BASE+0x0000)
188 #define UDP_GLOBAL_STATE REG(UDP_BASE+0x0004)
189 #define UDP_FUNCTION_ADDR REG(UDP_BASE+0x0008)
190 #define UDP_INTERRUPT_ENABLE REG(UDP_BASE+0x0010)
191 #define UDP_INTERRUPT_DISABLE REG(UDP_BASE+0x0014)
192 #define UDP_INTERRUPT_MASK REG(UDP_BASE+0x0018)
193 #define UDP_INTERRUPT_STATUS REG(UDP_BASE+0x001c)
194 #define UDP_INTERRUPT_CLEAR REG(UDP_BASE+0x0020)
195 #define UDP_RESET_ENDPOINT REG(UDP_BASE+0x0028)
196 #define UDP_ENDPOINT_CSR(x) REG(UDP_BASE+0x0030+((x)*4))
197 #define UDP_ENDPOINT_FIFO(x) REG(UDP_BASE+0x0050+((x)*4))
198 #define UDP_TRANSCEIVER_CTRL REG(UDP_BASE+0x0074)
199
200 #define UDP_GLOBAL_STATE_ADDRESSED (1<<0)
201 #define UDP_GLOBAL_STATE_CONFIGURED (1<<1)
202 #define UDP_GLOBAL_STATE_SEND_RESUME_ENABLED (1<<2)
203 #define UDP_GLOBAL_STATE_RESUME_RECEIVED (1<<3)
204 #define UDP_GLOBAL_STATE_REMOTE_WAKE_UP_ENABLED (1<<4)
205
206 #define UDP_FUNCTION_ADDR_ENABLED (1<<8)
207
208 #define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))
209 #define UDP_INTERRUPT_SUSPEND (1<<8)
210 #define UDP_INTERRUPT_RESUME (1<<9)
211 #define UDP_INTERRUPT_EXTERNAL_RESUME (1<<10)
212 #define UDP_INTERRUPT_SOF (1<<11)
213 #define UDP_INTERRUPT_END_OF_BUS_RESET (1<<12)
214 #define UDP_INTERRUPT_WAKEUP (1<<13)
215
216 #define UDP_RESET_ENDPOINT_NUMBER(x) (1<<(x))
217
218 #define UDP_CSR_TX_PACKET_ACKED (1<<0)
219 #define UDP_CSR_RX_PACKET_RECEIVED_BANK_0 (1<<1)
220 #define UDP_CSR_RX_HAVE_READ_SETUP_DATA (1<<2)
221 #define UDP_CSR_STALL_SENT (1<<3)
222 #define UDP_CSR_TX_PACKET (1<<4)
223 #define UDP_CSR_FORCE_STALL (1<<5)
224 #define UDP_CSR_RX_PACKET_RECEIVED_BANK_1 (1<<6)
225 #define UDP_CSR_CONTROL_DATA_DIR (1<<7)
226 #define UDP_CSR_EPTYPE_CONTROL (0<<8)
227 #define UDP_CSR_EPTYPE_ISOCHRON_OUT (1<<8)
228 #define UDP_CSR_EPTYPE_ISOCHRON_IN (5<<8)
229 #define UDP_CSR_EPTYPE_BULK_OUT (2<<8)
230 #define UDP_CSR_EPTYPE_BULK_IN (6<<8)
231 #define UDP_CSR_EPTYPE_INTERRUPT_OUT (3<<8)
232 #define UDP_CSR_EPTYPE_INTERRUPT_IN (7<<8)
233 #define UDP_CSR_IS_DATA1 (1<<11)
234 #define UDP_CSR_ENABLE_EP (1<<15)
235 #define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)
236
237 #define UDP_TRANSCEIVER_CTRL_DISABLE (1<<8)
238
239 //-------------
240 // Power Management Controller
241
242 #define PMC_BASE (0xfffffc00)
243
244 #define PMC_SYS_CLK_ENABLE REG(PMC_BASE+0x0000)
245 #define PMC_SYS_CLK_DISABLE REG(PMC_BASE+0x0004)
246 #define PMC_SYS_CLK_STATUS REG(PMC_BASE+0x0008)
247 #define PMC_PERIPHERAL_CLK_ENABLE REG(PMC_BASE+0x0010)
248 #define PMC_PERIPHERAL_CLK_DISABLE REG(PMC_BASE+0x0014)
249 #define PMC_PERIPHERAL_CLK_STATUS REG(PMC_BASE+0x0018)
250 #define PMC_MAIN_OSCILLATOR REG(PMC_BASE+0x0020)
251 #define PMC_MAIN_CLK_FREQUENCY REG(PMC_BASE+0x0024)
252 #define PMC_PLL REG(PMC_BASE+0x002c)
253 #define PMC_MASTER_CLK REG(PMC_BASE+0x0030)
254 #define PMC_PROGRAMMABLE_CLK_0 REG(PMC_BASE+0x0040)
255 #define PMC_PROGRAMMABLE_CLK_1 REG(PMC_BASE+0x0044)
256 #define PMC_INTERRUPT_ENABLE REG(PMC_BASE+0x0060)
257 #define PMC_INTERRUPT_DISABLE REG(PMC_BASE+0x0064)
258 #define PMC_INTERRUPT_STATUS REG(PMC_BASE+0x0068)
259 #define PMC_INTERRUPT_MASK REG(PMC_BASE+0x006c)
260
261 #define PMC_SYS_CLK_PROCESSOR_CLK (1<<0)
262 #define PMC_SYS_CLK_UDP_CLK (1<<7)
263 #define PMC_SYS_CLK_PROGRAMMABLE_CLK_0 (1<<8)
264 #define PMC_SYS_CLK_PROGRAMMABLE_CLK_1 (1<<9)
265 #define PMC_SYS_CLK_PROGRAMMABLE_CLK_2 (1<<10)
266
267 #define PMC_MAIN_OSCILLATOR_STABILIZED (1<<0)
268 #define PMC_MAIN_OSCILLATOR_PLL_LOCK (1<<2)
269 #define PMC_MAIN_OSCILLATOR_MCK_READY (1<<3)
270 #define PMC_MAIN_OSCILLATOR_ENABLE (1<<0)
271 #define PMC_MAIN_OSCILLATOR_BYPASS (1<<1)
272 #define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x) ((x)<<8)
273
274 #define PMC_PLL_DIVISOR(x) (x)
275 #define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)
276 #define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)
277 #define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)
278 #define PMC_PLL_USB_DIVISOR(x) ((x)<<28)
279
280 #define PMC_CLK_SELECTION_PLL_CLOCK (3<<0)
281 #define PMC_CLK_SELECTION_MAIN_CLOCK (1<<0)
282 #define PMC_CLK_SELECTION_SLOW_CLOCK (0<<0)
283 #define PMC_CLK_PRESCALE_DIV_1 (0<<2)
284 #define PMC_CLK_PRESCALE_DIV_2 (1<<2)
285 #define PMC_CLK_PRESCALE_DIV_4 (2<<2)
286 #define PMC_CLK_PRESCALE_DIV_8 (3<<2)
287 #define PMC_CLK_PRESCALE_DIV_16 (4<<2)
288 #define PMC_CLK_PRESCALE_DIV_32 (5<<2)
289 #define PMC_CLK_PRESCALE_DIV_64 (6<<2)
290
291 //-------------
292 // Serial Peripheral Interface (SPI)
293
294 #define SPI_BASE (0xfffe0000)
295
296 #define SPI_CONTROL REG(SPI_BASE+0x00)
297 #define SPI_MODE REG(SPI_BASE+0x04)
298 #define SPI_RX_DATA REG(SPI_BASE+0x08)
299 #define SPI_TX_DATA REG(SPI_BASE+0x0c)
300 #define SPI_STATUS REG(SPI_BASE+0x10)
301 #define SPI_INTERRUPT_ENABLE REG(SPI_BASE+0x14)
302 #define SPI_INTERRUPT_DISABLE REG(SPI_BASE+0x18)
303 #define SPI_INTERRUPT_MASK REG(SPI_BASE+0x1c)
304 #define SPI_FOR_CHIPSEL_0 REG(SPI_BASE+0x30)
305 #define SPI_FOR_CHIPSEL_1 REG(SPI_BASE+0x34)
306 #define SPI_FOR_CHIPSEL_2 REG(SPI_BASE+0x38)
307 #define SPI_FOR_CHIPSEL_3 REG(SPI_BASE+0x3c)
308
309 #define SPI_CONTROL_ENABLE (1<<0)
310 #define SPI_CONTROL_DISABLE (1<<1)
311 #define SPI_CONTROL_RESET (1<<7)
312 #define SPI_CONTROL_LAST_TRANSFER (1<<24)
313
314 #define SPI_MODE_MASTER (1<<0)
315 #define SPI_MODE_VARIABLE_CHIPSEL (1<<1)
316 #define SPI_MODE_CHIPSELS_DECODED (1<<2)
317 #define SPI_MODE_USE_DIVIDED_CLOCK (1<<3)
318 #define SPI_MODE_MODE_FAULT_DETECTION_OFF (1<<4)
319 #define SPI_MODE_LOOPBACK (1<<7)
320 #define SPI_MODE_CHIPSEL(x) ((x)<<16)
321 #define SPI_MODE_DELAY_BETWEEN_CHIPSELS(x) ((x)<<24)
322
323 #define SPI_RX_DATA_CHIPSEL(x) (((x)>>16)&0xf)
324
325 #define SPI_TX_DATA_CHIPSEL(x) ((x)<<16)
326 #define SPI_TX_DATA_LAST_TRANSFER (1<<24)
327
328 #define SPI_STATUS_RECEIVE_FULL (1<<0)
329 #define SPI_STATUS_TRANSMIT_EMPTY (1<<1)
330 #define SPI_STATUS_MODE_FAULT (1<<2)
331 #define SPI_STATUS_OVERRUN (1<<3)
332 #define SPI_STATUS_END_OF_RX_BUFFER (1<<4)
333 #define SPI_STATUS_END_OF_TX_BUFFER (1<<5)
334 #define SPI_STATUS_RX_BUFFER_FULL (1<<6)
335 #define SPI_STATUS_TX_BUFFER_EMPTY (1<<7)
336 #define SPI_STATUS_NSS_RISING_DETECTED (1<<8)
337 #define SPI_STATUS_TX_EMPTY (1<<9)
338 #define SPI_STATUS_SPI_ENABLED (1<<16)
339
340 #define SPI_FOR_CHIPSEL_INACTIVE_CLK_1 (1<<0)
341 #define SPI_FOR_CHIPSEL_PHASE (1<<1)
342 #define SPI_FOR_CHIPSEL_LEAVE_CHIPSEL_LOW (1<<3)
343 #define SPI_FOR_CHIPSEL_BITS_IN_WORD(x) ((x)<<4)
344 #define SPI_FOR_CHIPSEL_DIVISOR(x) ((x)<<8)
345 #define SPI_FOR_CHIPSEL_DELAY_BEFORE_CLK(x) ((x)<<16)
346 #define SPI_FOR_CHIPSEL_INTERWORD_DELAY(x) ((x)<<24)
347
348 //-------------
349 // Analog to Digital Converter
350
351 #define ADC_BASE (0xfffd8000)
352
353 #define ADC_CONTROL REG(ADC_BASE+0x00)
354 #define ADC_MODE REG(ADC_BASE+0x04)
355 #define ADC_CHANNEL_ENABLE REG(ADC_BASE+0x10)
356 #define ADC_CHANNEL_DISABLE REG(ADC_BASE+0x14)
357 #define ADC_CHANNEL_STATUS REG(ADC_BASE+0x18)
358 #define ADC_STATUS REG(ADC_BASE+0x1c)
359 #define ADC_LAST_CONVERTED_DATA REG(ADC_BASE+0x20)
360 #define ADC_INTERRUPT_ENABLE REG(ADC_BASE+0x24)
361 #define ADC_INTERRUPT_DISABLE REG(ADC_BASE+0x28)
362 #define ADC_INTERRUPT_MASK REG(ADC_BASE+0x2c)
363 #define ADC_CHANNEL_DATA(x) REG(ADC_BASE+0x30+(4*(x)))
364
365 #define ADC_CONTROL_RESET (1<<0)
366 #define ADC_CONTROL_START (1<<1)
367
368 #define ADC_MODE_HW_TRIGGERS_ENABLED (1<<0)
369 #define ADC_MODE_8_BIT_RESOLUTION (1<<4)
370 #define ADC_MODE_SLEEP (1<<5)
371 #define ADC_MODE_PRESCALE(x) ((x)<<8)
372 #define ADC_MODE_STARTUP_TIME(x) ((x)<<16)
373 #define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)
374
375 #define ADC_CHANNEL(x) (1<<(x))
376
377 #define ADC_END_OF_CONVERSION(x) (1<<(x))
378 #define ADC_OVERRUN_ERROR(x) (1<<(8+(x)))
379 #define ADC_DATA_READY (1<<16)
380 #define ADC_GENERAL_OVERRUN (1<<17)
381 #define ADC_END_OF_RX_BUFFER (1<<18)
382 #define ADC_RX_BUFFER_FULL (1<<19)
383
384 #define ADC_CHAN_LF 4
385 #define ADC_CHAN_HF 5
386 //-------------
387 // Synchronous Serial Controller
388
389 #define SSC_BASE (0xfffd4000)
390
391 #define SSC_CONTROL REG(SSC_BASE+0x00)
392 #define SSC_CLOCK_DIVISOR REG(SSC_BASE+0x04)
393 #define SSC_RECEIVE_CLOCK_MODE REG(SSC_BASE+0x10)
394 #define SSC_RECEIVE_FRAME_MODE REG(SSC_BASE+0x14)
395 #define SSC_TRANSMIT_CLOCK_MODE REG(SSC_BASE+0x18)
396 #define SSC_TRANSMIT_FRAME_MODE REG(SSC_BASE+0x1c)
397 #define SSC_RECEIVE_HOLDING REG(SSC_BASE+0x20)
398 #define SSC_TRANSMIT_HOLDING REG(SSC_BASE+0x24)
399 #define SSC_RECEIVE_SYNC_HOLDING REG(SSC_BASE+0x30)
400 #define SSC_TRANSMIT_SYNC_HOLDING REG(SSC_BASE+0x34)
401 #define SSC_STATUS REG(SSC_BASE+0x40)
402 #define SSC_INTERRUPT_ENABLE REG(SSC_BASE+0x44)
403 #define SSC_INTERRUPT_DISABLE REG(SSC_BASE+0x48)
404 #define SSC_INTERRUPT_MASK REG(SSC_BASE+0x4c)
405
406 #define SSC_CONTROL_RX_ENABLE (1<<0)
407 #define SSC_CONTROL_RX_DISABLE (1<<1)
408 #define SSC_CONTROL_TX_ENABLE (1<<8)
409 #define SSC_CONTROL_TX_DISABLE (1<<9)
410 #define SSC_CONTROL_RESET (1<<15)
411
412 #define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)
413 #define SSC_CLOCK_MODE_OUTPUT(x) ((x)<<2)
414 #define SSC_CLOCK_MODE_INVERT (1<<5)
415 #define SSC_CLOCK_MODE_START(x) ((x)<<8)
416 #define SSC_CLOCK_MODE_START_DELAY(x) ((x)<<16)
417 #define SSC_CLOCK_MODE_FRAME_PERIOD(x) ((x)<<24)
418
419 #define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)
420 #define SSC_FRAME_MODE_LOOPBACK (1<<5) // for RX
421 #define SSC_FRAME_MODE_DEFAULT_IS_1 (1<<5) // for TX
422 #define SSC_FRAME_MODE_MSB_FIRST (1<<7)
423 #define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)
424 #define SSC_FRAME_MODE_FRAME_SYNC_LEN(x) ((x)<<16)
425 #define SSC_FRAME_MODE_FRAME_SYNC_TYPE(x) ((x)<<20)
426 #define SSC_FRAME_MODE_SYNC_DATA_ENABLE (1<<23) // for TX only
427 #define SSC_FRAME_MODE_NEGATIVE_EDGE (1<<24)
428
429 #define SSC_STATUS_TX_READY (1<<0)
430 #define SSC_STATUS_TX_EMPTY (1<<1)
431 #define SSC_STATUS_TX_ENDED (1<<2)
432 #define SSC_STATUS_TX_BUF_EMPTY (1<<3)
433 #define SSC_STATUS_RX_READY (1<<4)
434 #define SSC_STATUS_RX_OVERRUN (1<<5)
435 #define SSC_STATUS_RX_ENDED (1<<6)
436 #define SSC_STATUS_RX_BUF_FULL (1<<7)
437 #define SSC_STATUS_TX_SYNC_OCCURRED (1<<10)
438 #define SSC_STATUS_RX_SYNC_OCCURRED (1<<11)
439 #define SSC_STATUS_TX_ENABLED (1<<16)
440 #define SSC_STATUS_RX_ENABLED (1<<17)
441
442 //-------------
443 // Peripheral DMA Controller
444 //
445 // There is one set of registers for every peripheral that supports DMA.
446
447 #define PDC_RX_POINTER(x) REG((x)+0x100)
448 #define PDC_RX_COUNTER(x) REG((x)+0x104)
449 #define PDC_TX_POINTER(x) REG((x)+0x108)
450 #define PDC_TX_COUNTER(x) REG((x)+0x10c)
451 #define PDC_RX_NEXT_POINTER(x) REG((x)+0x110)
452 #define PDC_RX_NEXT_COUNTER(x) REG((x)+0x114)
453 #define PDC_TX_NEXT_POINTER(x) REG((x)+0x118)
454 #define PDC_TX_NEXT_COUNTER(x) REG((x)+0x11c)
455 #define PDC_CONTROL(x) REG((x)+0x120)
456 #define PDC_STATUS(x) REG((x)+0x124)
457
458 #define PDC_RX_ENABLE (1<<0)
459 #define PDC_RX_DISABLE (1<<1)
460 #define PDC_TX_ENABLE (1<<8)
461 #define PDC_TX_DISABLE (1<<9)
462
463 //-------------
464 // Timer/Counter base
465
466 #define TC_BASE (0xfffa0000)
467
468 #define TC_BCR REG(TC_BASE+0xC0)
469 #define TC_BMR REG(TC_BASE+0xC4)
470
471 #define TC_BCR_SYNC (1<<0)
472
473 #define TC_CCR_CLKEN (1<<0)
474 #define TC_CCR_CLKDIS (1<<1)
475 #define TC_CCR_SWTRG (1<<2)
476
477 #define TC_CMR_TCCLKS (7<<0)
478 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)
479 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (1<<0)
480 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (2<<0)
481 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (3<<0)
482 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (4<<0)
483 #define TC_CMR_TCCLKS_XC0 (5<<0)
484 #define TC_CMR_TCCLKS_XC1 (6<<0)
485 #define TC_CMR_TCCLKS_XC2 (7<<0)
486 #define TC_CMR_CLKI (1<<3)
487 #define TC_CMR_BURST (3<<4)
488 #define TC_CMR_BURST_XC0 (1<<4)
489 #define TC_CMR_BURST_XC1 (2<<4)
490 #define TC_CMR_BURST_XC2 (3<<4)
491 #define TC_CMR_LDBSTOP (1<<6)
492 #define TC_CMR_CPCSTOP (1<<6)
493 #define TC_CMR_LDBDIS (1<<7)
494 #define TC_CMR_CPCDIS (1<<7)
495 #define TC_CMR_ETRGEDG (3<<8)
496 #define TC_CMR_ETRGEDG_NONE (0<<8)
497 #define TC_CMR_ETRGEDG_RISING (1<<8)
498 #define TC_CMR_ETRGEDG_FALLING (2<<8)
499 #define TC_CMR_ETRGEDG_EACH (3<<8)
500 #define TC_CMR_EEVTEDG (3<<8)
501 #define TC_CMR_EEVTEDG_NONE (0<<8)
502 #define TC_CMR_EEVTEDG_RISING (1<<8)
503 #define TC_CMR_EEVTEDG_FALLING (2<<8)
504 #define TC_CMR_EEVTEDG_EACH (3<<8)
505 #define TC_CMR_ABETRG (1<<10)
506 #define TC_CMR_EEVT (3<<10)
507 #define TC_CMR_EEVT_TIOB (0<<10)
508 #define TC_CMR_EEVT_XC0 (1<<10)
509 #define TC_CMR_EEVT_XC1 (2<<10)
510 #define TC_CMR_EEVT_XC2 (3<<10)
511 #define TC_CMR_ENETRG (1<<12)
512 #define TC_CMR_WAVSEL (3<<13)
513 #define TC_CMR_WAVSEL_UP (0<<13)
514 #define TC_CMR_WAVSEL_UP_AUTO (2<<13)
515 #define TC_CMR_WAVSEL_UPDOWN (1<<13)
516 #define TC_CMR_WAVSEL_UPDOWN_AUTO (3<<13)
517 #define TC_CMR_CPCTRG (1<<14)
518 #define TC_CMR_WAVE (1<<15)
519 #define TC_CMR_LDRA (3<<16)
520 #define TC_CMR_LDRA_NONE (0<<16)
521 #define TC_CMR_LDRA_RISING (1<<16)
522 #define TC_CMR_LDRA_FALLING (2<<16)
523 #define TC_CMR_LDRA_EACH (3<<16)
524 #define TC_CMR_ACPA (3<<16)
525 #define TC_CMR_ACPA_NONE (0<<16)
526 #define TC_CMR_ACPA_SET (1<<16)
527 #define TC_CMR_ACPA_CLEAR (2<<16)
528 #define TC_CMR_ACPA_TOGGLE (3<<16)
529 #define TC_CMR_LDRB (3<<18)
530 #define TC_CMR_LDRB_NONE (0<<18)
531 #define TC_CMR_LDRB_RISING (1<<18)
532 #define TC_CMR_LDRB_FALLING (2<<18)
533 #define TC_CMR_LDRB_EACH (3<<18)
534 #define TC_CMR_ACPC (3<<18)
535 #define TC_CMR_ACPC_NONE (0<<18)
536 #define TC_CMR_ACPC_SET (1<<18)
537 #define TC_CMR_ACPC_CLEAR (2<<18)
538 #define TC_CMR_ACPC_TOGGLE (3<<18)
539 #define TC_CMR_AEEVT (3<<20)
540 #define TC_CMR_AEEVT_NONE (0<<20)
541 #define TC_CMR_AEEVT_SET (1<<20)
542 #define TC_CMR_AEEVT_CLEAR (2<<20)
543 #define TC_CMR_AEEVT_TOGGLE (3<<20)
544 #define TC_CMR_ASWTRG (3<<22)
545 #define TC_CMR_ASWTRG_NONE (0<<22)
546 #define TC_CMR_ASWTRG_SET (1<<22)
547 #define TC_CMR_ASWTRG_CLEAR (2<<22)
548 #define TC_CMR_ASWTRG_TOGGLE (3<<22)
549 #define TC_CMR_BCPB (3<<24)
550 #define TC_CMR_BCPB_NONE (0<<24)
551 #define TC_CMR_BCPB_SET (1<<24)
552 #define TC_CMR_BCPB_CLEAR (2<<24)
553 #define TC_CMR_BCPB_TOGGLE (3<<24)
554 #define TC_CMR_BCPC (3<<26)
555 #define TC_CMR_BCPC_NONE (0<<26)
556 #define TC_CMR_BCPC_SET (1<<26)
557 #define TC_CMR_BCPC_CLEAR (2<<26)
558 #define TC_CMR_BCPC_TOGGLE (3<<26)
559 #define TC_CMR_BEEVT (3<<28)
560 #define TC_CMR_BEEVT_NONE (0<<28)
561 #define TC_CMR_BEEVT_SET (1<<28)
562 #define TC_CMR_BEEVT_CLEAR (2<<28)
563 #define TC_CMR_BEEVT_TOGGLE (3<<28)
564 #define TC_CMR_BSWTRG (3<<30)
565 #define TC_CMR_BSWTRG_NONE (0<<30)
566 #define TC_CMR_BSWTRG_SET (1<<30)
567 #define TC_CMR_BSWTRG_CLEAR (2<<30)
568 #define TC_CMR_BSWTRG_TOGGLE (3<<30)
569
570 #define TC_SR_COVFS (1<<0)
571 #define TC_SR_LOVFS (1<<1)
572 #define TC_SR_CPAS (1<<2)
573 #define TC_SR_CPBS (1<<3)
574 #define TC_SR_CPCS (1<<4)
575 #define TC_SR_LDRAS (1<<5)
576 #define TC_SR_LDRBS (1<<6)
577 #define TC_SR_ETRGS (1<<7)
578 #define TC_SR_CLKSTA (1<<16)
579 #define TC_SR_MTIOA (1<<17)
580 #define TC_SR_MTIOB (1<<18)
581
582 //-------------
583 // Timer/Counter 0
584
585 #define TC0_BASE (TC_BASE+0x40*0)
586
587 #define TC0_CCR REG(TC0_BASE+0x00)
588 #define TC0_CMR REG(TC0_BASE+0x04)
589 #define TC0_CV REG(TC0_BASE+0x10)
590 #define TC0_RA REG(TC0_BASE+0x14)
591 #define TC0_RB REG(TC0_BASE+0x18)
592 #define TC0_RC REG(TC0_BASE+0x1C)
593 #define TC0_SR REG(TC0_BASE+0x20)
594 #define TC0_IER REG(TC0_BASE+0x24)
595 #define TC0_IDR REG(TC0_BASE+0x28)
596 #define TC0_IMR REG(TC0_BASE+0x2C)
597
598 //-------------
599 // Timer/Counter 1
600
601 #define TC1_BASE (TC_BASE+0x40*1)
602
603 #define TC1_CCR REG(TC1_BASE+0x00)
604 #define TC1_CMR REG(TC1_BASE+0x04)
605 #define TC1_CV REG(TC1_BASE+0x10)
606 #define TC1_RA REG(TC1_BASE+0x14)
607 #define TC1_RB REG(TC1_BASE+0x18)
608 #define TC1_RC REG(TC1_BASE+0x1C)
609 #define TC1_SR REG(TC1_BASE+0x20)
610 #define TC1_IER REG(TC1_BASE+0x24)
611 #define TC1_IDR REG(TC1_BASE+0x28)
612 #define TC1_IMR REG(TC1_BASE+0x2C)
613
614 //-------------
615 // Timer/Counter 2
616
617 #define TC2_BASE (TC_BASE+0x40*2)
618
619 #define TC2_CCR REG(TC2_BASE+0x00)
620 #define TC2_CMR REG(TC2_BASE+0x04)
621 #define TC2_CV REG(TC2_BASE+0x10)
622 #define TC2_RA REG(TC2_BASE+0x14)
623 #define TC2_RB REG(TC2_BASE+0x18)
624 #define TC2_RC REG(TC2_BASE+0x1C)
625 #define TC2_SR REG(TC2_BASE+0x20)
626 #define TC2_IER REG(TC2_BASE+0x24)
627 #define TC2_IDR REG(TC2_BASE+0x28)
628 #define TC2_IMR REG(TC2_BASE+0x2C)
629
630
631 #endif
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