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Legic TagSim: increased reader timeout (#771)
[proxmark3-svn] / fpga / hi_read_rx_xcorr.v
1 //-----------------------------------------------------------------------------
2 //
3 // Jonathan Westhues, April 2006
4 //-----------------------------------------------------------------------------
5
6 module hi_read_rx_xcorr(
7 pck0, ck_1356meg, ck_1356megb,
8 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
9 adc_d, adc_clk,
10 ssp_frame, ssp_din, ssp_dout, ssp_clk,
11 cross_hi, cross_lo,
12 dbg,
13 xcorr_is_848, snoop, xcorr_quarter_freq, hi_read_rx_xcorr_amplitude
14 );
15 input pck0, ck_1356meg, ck_1356megb;
16 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
17 input [7:0] adc_d;
18 output adc_clk;
19 input ssp_dout;
20 output ssp_frame, ssp_din, ssp_clk;
21 input cross_hi, cross_lo;
22 output dbg;
23 input xcorr_is_848, snoop, xcorr_quarter_freq, hi_read_rx_xcorr_amplitude;
24
25 // Carrier is steady on through this, unless we're snooping.
26 assign pwr_hi = ck_1356megb & (~snoop);
27 assign pwr_oe1 = 1'b0;
28 assign pwr_oe3 = 1'b0;
29 assign pwr_oe4 = 1'b0;
30 // Unused.
31 assign pwr_lo = 1'b0;
32 assign pwr_oe2 = 1'b0;
33
34 assign adc_clk = ck_1356megb; // sample frequency is 13,56 MHz
35
36 // When we're a reader, we just need to do the BPSK demod; but when we're an
37 // eavesdropper, we also need to pick out the commands sent by the reader,
38 // using AM. Do this the same way that we do it for the simulated tag.
39 reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
40 reg [11:0] has_been_low_for;
41 always @(negedge adc_clk)
42 begin
43 if(& adc_d[7:0]) after_hysteresis <= 1'b1;
44 else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
45
46 if(after_hysteresis)
47 begin
48 has_been_low_for <= 7'b0;
49 end
50 else
51 begin
52 if(has_been_low_for == 12'd4095)
53 begin
54 has_been_low_for <= 12'd0;
55 after_hysteresis <= 1'b1;
56 end
57 else
58 has_been_low_for <= has_been_low_for + 1;
59 end
60 end
61
62
63 // Let us report a correlation every 64 samples. I.e.
64 // one Q/I pair after 4 subcarrier cycles for the 848kHz subcarrier,
65 // one Q/I pair after 2 subcarrier cycles for the 424kHz subcarriers,
66 // one Q/I pair for each subcarrier cyle for the 212kHz subcarrier.
67 // We need a 6-bit counter for the timing.
68 reg [5:0] corr_i_cnt;
69 always @(negedge adc_clk)
70 begin
71 corr_i_cnt <= corr_i_cnt + 1;
72 end
73
74 // And a couple of registers in which to accumulate the correlations. From the 64 samples
75 // we would add at most 32 times the difference between unmodulated and modulated signal. It should
76 // be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
77 // 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
78 // Temporary we might need more bits. For the 212kHz subcarrier we could possible add 32 times the
79 // maximum signal value before a first subtraction would occur. 32 * 255 = 8160 can be held in 13 bits.
80 // Add one bit for sign -> need 14 bit registers but final result will fit into 12 bits.
81 reg signed [13:0] corr_i_accum;
82 reg signed [13:0] corr_q_accum;
83 // we will report maximum 8 significant bits
84 reg signed [7:0] corr_i_out;
85 reg signed [7:0] corr_q_out;
86
87 // clock and frame signal for communication to ARM
88 reg ssp_clk;
89 reg ssp_frame;
90
91
92
93 // the amplitude of the subcarrier is sqrt(ci^2 + cq^2).
94 // approximate by amplitude = max(|ci|,|cq|) + 1/2*min(|ci|,|cq|)
95 reg [13:0] corr_amplitude, abs_ci, abs_cq, max_ci_cq, min_ci_cq;
96
97
98 always @(corr_i_accum or corr_q_accum)
99 begin
100 if (corr_i_accum[13] == 1'b0)
101 abs_ci <= corr_i_accum;
102 else
103 abs_ci <= -corr_i_accum;
104
105 if (corr_q_accum[13] == 1'b0)
106 abs_cq <= corr_q_accum;
107 else
108 abs_cq <= -corr_q_accum;
109
110 if (abs_ci > abs_cq)
111 begin
112 max_ci_cq <= abs_ci;
113 min_ci_cq <= abs_cq;
114 end
115 else
116 begin
117 max_ci_cq <= abs_cq;
118 min_ci_cq <= abs_ci;
119 end
120
121 corr_amplitude <= max_ci_cq + min_ci_cq/2;
122
123 end
124
125
126 // The subcarrier reference signals
127 reg subcarrier_I;
128 reg subcarrier_Q;
129
130 always @(corr_i_cnt or xcorr_is_848 or xcorr_quarter_freq)
131 begin
132 if (xcorr_is_848 & ~xcorr_quarter_freq) // 848 kHz
133 begin
134 subcarrier_I = ~corr_i_cnt[3];
135 subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
136 end
137 else if (xcorr_is_848 & xcorr_quarter_freq) // 212 kHz
138 begin
139 subcarrier_I = ~corr_i_cnt[5];
140 subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
141 end
142 else
143 begin // 424 kHz
144 subcarrier_I = ~corr_i_cnt[4];
145 subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
146 end
147 end
148
149
150 // ADC data appears on the rising edge, so sample it on the falling edge
151 always @(negedge adc_clk)
152 begin
153 // These are the correlators: we correlate against in-phase and quadrature
154 // versions of our reference signal, and keep the (signed) results or the
155 // resulting amplitude to send out later over the SSP.
156 if(corr_i_cnt == 6'd0)
157 begin
158 if(snoop)
159 begin
160 if (hi_read_rx_xcorr_amplitude)
161 begin
162 // send amplitude plus 2 bits reader signal
163 corr_i_out <= corr_amplitude[13:6];
164 corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
165 end
166 else
167 begin
168 // Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
169 if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
170 corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
171 else // truncate to maximum value
172 if (corr_i_accum[13] == 1'b0)
173 corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
174 else
175 corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
176 // Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
177 if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
178 corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
179 else // truncate to maximum value
180 if (corr_q_accum[13] == 1'b0)
181 corr_q_out <= {7'b0111111, after_hysteresis_prev};
182 else
183 corr_q_out <= {7'b1000000, after_hysteresis_prev};
184 end
185 end
186 else
187 begin
188 if (hi_read_rx_xcorr_amplitude)
189 begin
190 // send amplitude
191 corr_i_out <= {2'b00, corr_amplitude[13:8]};
192 corr_q_out <= corr_amplitude[7:0];
193 end
194 else
195 begin
196 // Send 8 bits of in phase tag signal
197 if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
198 corr_i_out <= corr_i_accum[11:4];
199 else // truncate to maximum value
200 if (corr_i_accum[13] == 1'b0)
201 corr_i_out <= 8'b01111111;
202 else
203 corr_i_out <= 8'b10000000;
204 // Send 8 bits of quadrature phase tag signal
205 if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
206 corr_q_out <= corr_q_accum[11:4];
207 else // truncate to maximum value
208 if (corr_q_accum[13] == 1'b0)
209 corr_q_out <= 8'b01111111;
210 else
211 corr_q_out <= 8'b10000000;
212 end
213 end
214
215 // for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
216 after_hysteresis_prev_prev <= after_hysteresis;
217 // Initialize next correlation.
218 // Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate.
219 corr_i_accum <= $signed({1'b0,adc_d});
220 corr_q_accum <= $signed({1'b0,adc_d});
221 end
222 else
223 begin
224 if (subcarrier_I)
225 corr_i_accum <= corr_i_accum + $signed({1'b0,adc_d});
226 else
227 corr_i_accum <= corr_i_accum - $signed({1'b0,adc_d});
228
229 if (subcarrier_Q)
230 corr_q_accum <= corr_q_accum + $signed({1'b0,adc_d});
231 else
232 corr_q_accum <= corr_q_accum - $signed({1'b0,adc_d});
233 end
234
235 // for each Q/I pair report two reader signal samples when sniffing. Store the 2nd.
236 if(corr_i_cnt == 6'd32)
237 after_hysteresis_prev <= after_hysteresis;
238
239 // Then the result from last time is serialized and send out to the ARM.
240 // We get one report each cycle, and each report is 16 bits, so the
241 // ssp_clk should be the adc_clk divided by 64/16 = 4.
242 // ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
243
244 if(corr_i_cnt[1:0] == 2'b10)
245 ssp_clk <= 1'b0;
246
247 if(corr_i_cnt[1:0] == 2'b00)
248 begin
249 ssp_clk <= 1'b1;
250 // Don't shift if we just loaded new data, obviously.
251 if(corr_i_cnt != 6'd0)
252 begin
253 corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
254 corr_q_out[7:1] <= corr_q_out[6:0];
255 end
256 end
257
258 // set ssp_frame signal for corr_i_cnt = 0..3
259 // (send one frame with 16 Bits)
260 if(corr_i_cnt[5:2] == 4'b0000)
261 ssp_frame = 1'b1;
262 else
263 ssp_frame = 1'b0;
264
265 end
266
267 assign ssp_din = corr_i_out[7];
268
269 assign dbg = corr_i_cnt[3];
270
271 endmodule
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