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CHG: "hf legic write" with these I managed to get one byte written. Its a start.
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 // 2016 Iceman
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // LEGIC RF simulation code
10 //-----------------------------------------------------------------------------
11 #include "legicrf.h"
12
13 static struct legic_frame {
14 uint8_t bits;
15 uint32_t data;
16 } current_frame;
17
18 static enum {
19 STATE_DISCON,
20 STATE_IV,
21 STATE_CON,
22 } legic_state;
23
24 static crc_t legic_crc;
25 static int legic_read_count;
26 static uint32_t legic_prng_bc;
27 static uint32_t legic_prng_iv;
28
29 static int legic_phase_drift;
30 static int legic_frame_drift;
31 static int legic_reqresp_drift;
32
33 AT91PS_TC timer;
34 AT91PS_TC prng_timer;
35
36 /*
37 static void setup_timer(void) {
38 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
39 // this it won't be terribly accurate but should be good enough.
40 //
41 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
42 timer = AT91C_BASE_TC1;
43 timer->TC_CCR = AT91C_TC_CLKDIS;
44 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
45 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
46
47 //
48 // Set up Timer 2 to use for measuring time between frames in
49 // tag simulation mode. Runs 4x faster as Timer 1
50 //
51 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
52 prng_timer = AT91C_BASE_TC2;
53 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
54 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
55 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 }
57
58 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
59 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
60
61 // fast clock
62 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
63 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
64 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
65 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
66 AT91C_BASE_TC0->TC_RA = 1;
67 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
68
69 */
70
71 // At TIMER_CLOCK3 (MCK/32)
72 // testing calculating in (us) microseconds.
73 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
74 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
75 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
76 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
77 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
78
79 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
80
81 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
82 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
83
84 #define OFFSET_LOG 1024
85
86 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
87
88 #ifndef SHORT_COIL
89 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
90 #endif
91 #ifndef OPEN_COIL
92 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
93 #endif
94 #ifndef LINE_IN
95 # define LINE_IN AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
96 #endif
97 // Pause pulse, off in 20us / 30ticks,
98 // ONE / ZERO bit pulse,
99 // one == 80us / 120ticks
100 // zero == 40us / 60ticks
101 #ifndef COIL_PULSE
102 # define COIL_PULSE(x) \
103 do { \
104 SHORT_COIL; \
105 WaitTicks( (RWD_TIME_PAUSE) ); \
106 OPEN_COIL; \
107 WaitTicks((x)); \
108 } while (0);
109 #endif
110
111 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
112 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
113 #define LEGIC_CARD_MEMSIZE 1024
114 static uint8_t* cardmem;
115
116 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
117 // Overflow, won't happen
118 if (f->bits >= 31) return;
119
120 f->data |= (bit << f->bits);
121 f->bits++;
122 }
123
124 static void frame_clean(struct legic_frame * const f) {
125 f->data = 0;
126 f->bits = 0;
127 }
128
129 // Prng works when waiting in 99.1us cycles.
130 // and while sending/receiving in bit frames (100, 60)
131 /*static void CalibratePrng( uint32_t time){
132 // Calculate Cycles based on timer 100us
133 uint32_t i = (time - sendFrameStop) / 100 ;
134
135 // substract cycles of finished frames
136 int k = i - legic_prng_count()+1;
137
138 // substract current frame length, rewind to beginning
139 if ( k > 0 )
140 legic_prng_forward(k);
141 }
142 */
143
144 /* Generate Keystream */
145 uint32_t get_key_stream(int skip, int count) {
146
147 int i;
148
149 // Use int to enlarge timer tc to 32bit
150 legic_prng_bc += prng_timer->TC_CV;
151
152 // reset the prng timer.
153
154 /* If skip == -1, forward prng time based */
155 if(skip == -1) {
156 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
157 i -= legic_prng_count(); /* substract cycles of finished frames */
158 i -= count; /* substract current frame length, rewind to beginning */
159 legic_prng_forward(i);
160 } else {
161 legic_prng_forward(skip);
162 }
163
164 i = (count == 6) ? -1 : legic_read_count;
165
166 /* Generate KeyStream */
167 return legic_prng_get_bits(count);
168 }
169
170 /* Send a frame in tag mode, the FPGA must have been set up by
171 * LegicRfSimulate
172 */
173 void frame_send_tag(uint16_t response, uint8_t bits) {
174
175 uint16_t mask = 1;
176
177 /* Bitbang the response */
178 SHORT_COIL;
179 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
180 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
181
182 /* TAG_FRAME_WAIT -> shift by 2 */
183 legic_prng_forward(2);
184 response ^= legic_prng_get_bits(bits);
185
186 /* Wait for the frame start */
187 WaitTicks( TAG_FRAME_WAIT );
188
189 for (; mask < BITMASK(bits); mask <<= 1) {
190 if (response & mask)
191 OPEN_COIL
192 else
193 SHORT_COIL
194 WaitTicks(TAG_BIT_PERIOD);
195 }
196 SHORT_COIL;
197 }
198
199 /* Send a frame in reader mode, the FPGA must have been set up by
200 * LegicRfReader
201 */
202 void frame_sendAsReader(uint32_t data, uint8_t bits){
203
204 uint32_t starttime = GET_TICKS, send = 0, mask = 1;
205
206 // xor lsfr onto data.
207 send = data ^ legic_prng_get_bits(bits);
208
209 for (; mask < BITMASK(bits); mask <<= 1) {
210 if (send & mask)
211 COIL_PULSE(RWD_TIME_1)
212 else
213 COIL_PULSE(RWD_TIME_0)
214 }
215
216 // Final pause to mark the end of the frame
217 COIL_PULSE(0);
218
219 // log
220 uint8_t cmdbytes[] = {bits, BYTEx(data,0), BYTEx(data,1), BYTEx(data,2) , BYTEx(send,0), BYTEx(send,1)};
221 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
222 }
223
224 /* Receive a frame from the card in reader emulation mode, the FPGA and
225 * timer must have been set up by LegicRfReader and frame_sendAsReader.
226 *
227 * The LEGIC RF protocol from card to reader does not include explicit
228 * frame start/stop information or length information. The reader must
229 * know beforehand how many bits it wants to receive. (Notably: a card
230 * sending a stream of 0-bits is indistinguishable from no card present.)
231 *
232 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
233 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
234 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
235 * for edges. Count the edges in each bit interval. If they are approximately
236 * 0 this was a 0-bit, if they are approximately equal to the number of edges
237 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
238 * timer that's still running from frame_sendAsReader in order to get a synchronization
239 * with the frame that we just sent.
240 *
241 * FIXME: Because we're relying on the hysteresis to just do the right thing
242 * the range is severely reduced (and you'll probably also need a good antenna).
243 * So this should be fixed some time in the future for a proper receiver.
244 */
245 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
246
247 if ( bits > 32 ) return;
248
249 uint8_t i = bits, edges = 0;
250 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
251 uint32_t old_level = 0;
252 volatile uint32_t level = 0;
253
254 frame_clean(f);
255
256 // calibrate the prng.
257 legic_prng_forward(2);
258 data = legic_prng_get_bits(bits);
259
260 //FIXED time between sending frame and now listening frame. 330us
261 uint32_t starttime = GET_TICKS;
262 // its about 9+9 ticks delay from end-send to here.
263 WaitTicks( 477 );
264
265 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
266
267 while ( i-- ){
268 edges = 0;
269 while ( GET_TICKS < next_bit_at) {
270
271 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
272
273 if (level != old_level)
274 ++edges;
275
276 old_level = level;
277 }
278
279 next_bit_at += TAG_BIT_PERIOD;
280
281 // We expect 42 edges (ONE)
282 if ( edges > 20 )
283 data ^= the_bit;
284
285 the_bit <<= 1;
286 }
287
288 // output
289 f->data = data;
290 f->bits = bits;
291
292 // log
293 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
294 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
295 }
296
297 // Setup pm3 as a Legic Reader
298 static uint32_t setup_phase_reader(uint8_t iv) {
299
300 // Switch on carrier and let the tag charge for 1ms
301 HIGH(GPIO_SSC_DOUT);
302 WaitUS(5000);
303
304 ResetTicks();
305
306 // no keystream yet
307 legic_prng_init(0);
308
309 // send IV handshake
310 frame_sendAsReader(iv, 7);
311
312 // Now both tag and reader has same IV. Prng can start.
313 legic_prng_init(iv);
314
315 frame_receiveAsReader(&current_frame, 6);
316
317 // 292us (438t) - fixed delay before sending ack.
318 // minus log and stuff 100tick?
319 WaitTicks(338);
320 legic_prng_forward(3);
321
322 // Send obsfuscated acknowledgment frame.
323 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
324 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
325 switch ( current_frame.data ) {
326 case 0x0D: frame_sendAsReader(0x19, 6); break;
327 case 0x1D:
328 case 0x3D: frame_sendAsReader(0x39, 6); break;
329 default: break;
330 }
331
332 legic_prng_forward(2);
333 return current_frame.data;
334 }
335
336 static void LegicCommonInit(void) {
337
338 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
339 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
340 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
341
342 /* Bitbang the transmitter */
343 SHORT_COIL;
344 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
345 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
346 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
347
348 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
349 cardmem = BigBuf_get_EM_addr();
350 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
351
352 clear_trace();
353 set_tracing(TRUE);
354 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
355
356 StartTicks();
357 }
358
359 // Switch off carrier, make sure tag is reset
360 static void switch_off_tag_rwd(void) {
361 SHORT_COIL;
362 WaitUS(20);
363 WDT_HIT();
364 }
365
366 // calculate crc4 for a legic READ command
367 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
368 crc_clear(&legic_crc);
369 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
370 crc_update(&legic_crc, temp, cmd_sz + 8 );
371 return crc_finish(&legic_crc);
372 }
373
374 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
375
376 uint8_t byte, crc, calcCrc = 0;
377 uint32_t cmd = (index << 1) | LEGIC_READ;
378
379 // 90ticks = 60us (should be 100us but crc calc takes time.)
380 //WaitTicks(330); // 330ticks prng(4) - works
381 WaitTicks(240); // 240ticks prng(3) - works
382
383 frame_sendAsReader(cmd, cmd_sz);
384 frame_receiveAsReader(&current_frame, 12);
385
386 // CRC check.
387 byte = BYTEx(current_frame.data, 0);
388 crc = BYTEx(current_frame.data, 1);
389 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
390
391 if( calcCrc != crc ) {
392 Dbprintf("!!! crc mismatch: %x != %x !!!", calcCrc, crc);
393 return -1;
394 }
395
396 legic_prng_forward(3);
397 return byte;
398 }
399
400 /*
401 * - assemble a write_cmd_frame with crc and send it
402 * - wait until the tag sends back an ACK ('1' bit unencrypted)
403 * - forward the prng based on the timing
404 */
405 bool legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
406
407 bool isOK = false;
408 int8_t i = 40;
409 uint8_t edges = 0;
410 uint8_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd;
411 uint32_t steps = 0, next_bit_at, start, crc, old_level = 0;
412
413 /*
414 crc_clear(&legic_crc);
415 crc_update(&legic_crc, 0, 1); // CMD_WRITE
416 crc_update(&legic_crc, index, addr_sz);
417 crc_update(&legic_crc, byte, 8);
418 crc = crc_finish(&legic_crc);
419 */
420 crc = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1);
421
422 // send write command
423 uint32_t cmd = LEGIC_WRITE;
424 cmd |= index << 1; // index
425 cmd |= byte << (addr_sz+1); // Data
426 cmd |= (crc & 0xF ) << (addr_sz+1+8); // CRC
427
428 /* Bitbang the response */
429 //AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
430
431 WaitTicks(240);
432
433 frame_sendAsReader(cmd, cmd_sz);
434
435 LINE_IN;
436
437 start = GET_TICKS;
438
439 // ACK, - one single "1" bit after 3.6ms
440 // 3.6ms = 3600us * 1.5 = 5400ticks.
441 WaitTicks(5300);
442
443 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
444
445 while ( i-- ) {
446 WDT_HIT();
447 edges = 0;
448 while ( GET_TICKS < next_bit_at) {
449
450 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
451
452 if (level != old_level)
453 ++edges;
454
455 old_level = level;
456 }
457
458 next_bit_at += TAG_BIT_PERIOD;
459
460 // We expect 42 edges (ONE)
461 if(edges > 20 ) {
462 steps = ( (GET_TICKS - start) / TAG_BIT_PERIOD);
463 legic_prng_forward(steps);
464 isOK = true;
465 goto OUT;
466 }
467 }
468
469 OUT: ;
470 // log
471 uint8_t cmdbytes[] = {1, isOK, BYTEx(steps, 0), BYTEx(steps, 1) };
472 LogTrace(cmdbytes, sizeof(cmdbytes), start, GET_TICKS, NULL, FALSE);
473 return isOK;
474 }
475
476 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
477
478 uint16_t i = 0;
479 uint8_t isOK = 1;
480 legic_card_select_t card;
481
482 LegicCommonInit();
483
484 if ( legic_select_card_iv(&card, iv) ) {
485 isOK = 0;
486 goto OUT;
487 }
488
489 if (len + offset >= card.cardsize)
490 len = card.cardsize - offset;
491
492 LED_B_ON();
493 while (i < len) {
494 int r = legic_read_byte(offset + i, card.cmdsize);
495
496 if (r == -1 || BUTTON_PRESS()) {
497 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
498 isOK = 0;
499 goto OUT;
500 }
501 cardmem[i++] = r;
502 WDT_HIT();
503 }
504
505 OUT:
506 WDT_HIT();
507 switch_off_tag_rwd();
508 LEDsoff();
509 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
510 return 0;
511 }
512
513 void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
514
515 #define LOWERLIMIT 4
516 uint8_t isOK = 1;
517 legic_card_select_t card;
518
519 // uid NOT is writeable.
520 if ( offset <= LOWERLIMIT ) {
521 isOK = 0;
522 goto OUT;
523 }
524
525 LegicCommonInit();
526
527 if ( legic_select_card_iv(&card, iv) ) {
528 isOK = 0;
529 goto OUT;
530 }
531
532 if ( len + offset + LOWERLIMIT >= card.cardsize) {
533 isOK = 0;
534 goto OUT;
535 }
536
537 LED_B_ON();
538 while( len > 0 ) {
539 --len;
540 if ( !legic_write_byte( len + offset, data[len], card.addrsize) ) {
541 Dbprintf("operation failed | %02X | %02X | %02X", len + offset, len, data[len] );
542 isOK = 0;
543 goto OUT;
544 }
545 WDT_HIT();
546 }
547 OUT:
548 cmd_send(CMD_ACK, isOK, 0,0,0,0);
549 switch_off_tag_rwd();
550 LEDsoff();
551 }
552
553 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
554
555 if ( p_card == NULL ) return 1;
556
557 p_card->tagtype = setup_phase_reader(iv);
558
559 switch(p_card->tagtype) {
560 case 0x0d:
561 p_card->cmdsize = 6;
562 p_card->addrsize = 5;
563 p_card->cardsize = 22;
564 break;
565 case 0x1d:
566 p_card->cmdsize = 9;
567 p_card->addrsize = 8;
568 p_card->cardsize = 256;
569 break;
570 case 0x3d:
571 p_card->cmdsize = 11;
572 p_card->addrsize = 10;
573 p_card->cardsize = 1024;
574 break;
575 default:
576 p_card->cmdsize = 0;
577 p_card->addrsize = 0;
578 p_card->cardsize = 0;
579 return 2;
580 }
581 return 0;
582 }
583 int legic_select_card(legic_card_select_t *p_card){
584 return legic_select_card_iv(p_card, 0x01);
585 }
586
587 //-----------------------------------------------------------------------------
588 // Work with emulator memory
589 //
590 // Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not
591 // involved in dealing with emulator memory. But if it is called later, it might
592 // destroy the Emulator Memory.
593 //-----------------------------------------------------------------------------
594 // arg0 = offset
595 // arg1 = num of bytes
596 void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) {
597 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
598 legic_emlset_mem(data, arg0, arg1);
599 }
600 // arg0 = offset
601 // arg1 = num of bytes
602 void LegicEMemGet(uint32_t arg0, uint32_t arg1) {
603 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
604 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
605 legic_emlget_mem(buf, arg0, arg1);
606 LED_B_ON();
607 cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE);
608 LED_B_OFF();
609 }
610 void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) {
611 cardmem = BigBuf_get_EM_addr();
612 memcpy(cardmem + offset, data, numofbytes);
613 }
614 void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) {
615 cardmem = BigBuf_get_EM_addr();
616 memcpy(data, cardmem + offset, numofbytes);
617 }
618
619 void LegicRfInfo(void){
620
621 int r;
622
623 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
624 legic_card_select_t *card = (legic_card_select_t*) buf;
625
626 LegicCommonInit();
627
628 if ( legic_select_card(card) ) {
629 cmd_send(CMD_ACK,0,0,0,0,0);
630 goto OUT;
631 }
632
633 // read UID bytes
634 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
635 r = legic_read_byte(i, card->cmdsize);
636 if ( r == -1 ) {
637 cmd_send(CMD_ACK,0,0,0,0,0);
638 goto OUT;
639 }
640 card->uid[i] = r & 0xFF;
641 }
642
643 // MCC byte.
644 r = legic_read_byte(4, card->cmdsize);
645 uint32_t calc_mcc = CRC8Legic(card->uid, 4);;
646 if ( r != calc_mcc) {
647 cmd_send(CMD_ACK,0,0,0,0,0);
648 goto OUT;
649 }
650
651 // OK
652 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
653
654 OUT:
655 switch_off_tag_rwd();
656 LEDsoff();
657 }
658
659 /* Handle (whether to respond) a frame in tag mode
660 * Only called when simulating a tag.
661 */
662 static void frame_handle_tag(struct legic_frame const * const f)
663 {
664 // log
665 //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
666 //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
667
668 cardmem = BigBuf_get_EM_addr();
669
670 /* First Part of Handshake (IV) */
671 if(f->bits == 7) {
672
673 LED_C_ON();
674
675 // Reset prng timer
676 ResetTimer(prng_timer);
677
678 // IV from reader.
679 legic_prng_init(f->data);
680
681 // We should have three tagtypes with three different answers.
682 frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */
683
684 legic_state = STATE_IV;
685 legic_read_count = 0;
686 legic_prng_bc = 0;
687 legic_prng_iv = f->data;
688
689
690 ResetTimer(timer);
691 WaitUS(280);
692 return;
693 }
694
695 /* 0x19==??? */
696 if(legic_state == STATE_IV) {
697 uint32_t local_key = get_key_stream(3, 6);
698 int xored = 0x39 ^ local_key;
699 if((f->bits == 6) && (f->data == xored)) {
700 legic_state = STATE_CON;
701
702 ResetTimer(timer);
703 WaitUS(200);
704 return;
705
706 } else {
707 legic_state = STATE_DISCON;
708 LED_C_OFF();
709 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
710 return;
711 }
712 }
713
714 /* Read */
715 if(f->bits == 11) {
716 if(legic_state == STATE_CON) {
717 uint32_t key = get_key_stream(2, 11); //legic_phase_drift, 11);
718 uint16_t addr = f->data ^ key;
719 addr >>= 1;
720 uint8_t data = cardmem[addr];
721 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
722
723 legic_read_count++;
724 legic_prng_forward(legic_reqresp_drift);
725
726 frame_send_tag(hash | data, 12);
727 ResetTimer(timer);
728 legic_prng_forward(2);
729 WaitTicks(330);
730 return;
731 }
732 }
733
734 /* Write */
735 if(f->bits == 23) {
736 uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23);
737 uint16_t addr = f->data ^ key;
738 addr >>= 1;
739 addr &= 0x3ff;
740 uint32_t data = f->data ^ key;
741 data >>= 11;
742 data &= 0xff;
743
744 cardmem[addr] = data;
745 /* write command */
746 legic_state = STATE_DISCON;
747 LED_C_OFF();
748 Dbprintf("write - addr: %x, data: %x", addr, data);
749 // should send a ACK within 3.5ms too
750 return;
751 }
752
753 if(legic_state != STATE_DISCON) {
754 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
755 Dbprintf("IV: %03.3x", legic_prng_iv);
756 }
757
758 legic_state = STATE_DISCON;
759 legic_read_count = 0;
760 SpinDelay(10);
761 LED_C_OFF();
762 return;
763 }
764
765 /* Read bit by bit untill full frame is received
766 * Call to process frame end answer
767 */
768 static void emit(int bit) {
769
770 switch (bit) {
771 case 1:
772 frame_append_bit(&current_frame, 1);
773 break;
774 case 0:
775 frame_append_bit(&current_frame, 0);
776 break;
777 default:
778 if(current_frame.bits <= 4) {
779 frame_clean(&current_frame);
780 } else {
781 frame_handle_tag(&current_frame);
782 frame_clean(&current_frame);
783 }
784 WDT_HIT();
785 break;
786 }
787 }
788
789 void LegicRfSimulate(int phase, int frame, int reqresp)
790 {
791 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
792 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
793 * envelope waveform on DIN and should send our response on DOUT.
794 *
795 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
796 * measure the time between two rising edges on DIN, and no encoding on the
797 * subcarrier from card to reader, so we'll just shift out our verbatim data
798 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
799 * seems to be 300us-ish.
800 */
801
802 int old_level = 0, active = 0;
803 legic_state = STATE_DISCON;
804
805 legic_phase_drift = phase;
806 legic_frame_drift = frame;
807 legic_reqresp_drift = reqresp;
808
809 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
810 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
811 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
812
813 /* Bitbang the receiver */
814 LINE_IN;
815
816 // need a way to determine which tagtype we are simulating
817
818 // hook up emulator memory
819 cardmem = BigBuf_get_EM_addr();
820
821 clear_trace();
822 set_tracing(TRUE);
823
824 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
825
826 StartTicks();
827
828 LED_B_ON();
829 DbpString("Starting Legic emulator, press button to end");
830
831 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
832 volatile uint32_t level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
833
834 uint32_t time = GET_TICKS;
835
836 if (level != old_level) {
837
838 if (level) {
839
840 ResetTicks();
841
842 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
843 /* 1 bit */
844 emit(1);
845 active = 1;
846 LED_A_ON();
847 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
848 /* 0 bit */
849 emit(0);
850 active = 1;
851 LED_A_ON();
852 } else if (active) {
853 /* invalid */
854 emit(-1);
855 active = 0;
856 LED_A_OFF();
857 }
858 }
859 }
860
861 /* Frame end */
862 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
863 emit(-1);
864 active = 0;
865 LED_A_OFF();
866 }
867
868 /*
869 * Disable the counter, Then wait for the clock to acknowledge the
870 * shutdown in its status register. Reading the SR has the
871 * side-effect of clearing any pending state in there.
872 */
873 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
874 StopTicks();
875
876 old_level = level;
877 WDT_HIT();
878 }
879
880 WDT_HIT();
881 switch_off_tag_rwd();
882 LEDsoff();
883 cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
884 }
885
886 //-----------------------------------------------------------------------------
887 // Code up a string of octets at layer 2 (including CRC, we don't generate
888 // that here) so that they can be transmitted to the reader. Doesn't transmit
889 // them yet, just leaves them ready to send in ToSend[].
890 //-----------------------------------------------------------------------------
891 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
892 // {
893 // int i;
894
895 // ToSendReset();
896
897 // // Transmit a burst of ones, as the initial thing that lets the
898 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
899 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
900 // // so I will too.
901 // for(i = 0; i < 20; i++) {
902 // ToSendStuffBit(1);
903 // ToSendStuffBit(1);
904 // ToSendStuffBit(1);
905 // ToSendStuffBit(1);
906 // }
907
908 // // Send SOF.
909 // for(i = 0; i < 10; i++) {
910 // ToSendStuffBit(0);
911 // ToSendStuffBit(0);
912 // ToSendStuffBit(0);
913 // ToSendStuffBit(0);
914 // }
915 // for(i = 0; i < 2; i++) {
916 // ToSendStuffBit(1);
917 // ToSendStuffBit(1);
918 // ToSendStuffBit(1);
919 // ToSendStuffBit(1);
920 // }
921
922 // for(i = 0; i < len; i++) {
923 // int j;
924 // uint8_t b = cmd[i];
925
926 // // Start bit
927 // ToSendStuffBit(0);
928 // ToSendStuffBit(0);
929 // ToSendStuffBit(0);
930 // ToSendStuffBit(0);
931
932 // // Data bits
933 // for(j = 0; j < 8; j++) {
934 // if(b & 1) {
935 // ToSendStuffBit(1);
936 // ToSendStuffBit(1);
937 // ToSendStuffBit(1);
938 // ToSendStuffBit(1);
939 // } else {
940 // ToSendStuffBit(0);
941 // ToSendStuffBit(0);
942 // ToSendStuffBit(0);
943 // ToSendStuffBit(0);
944 // }
945 // b >>= 1;
946 // }
947
948 // // Stop bit
949 // ToSendStuffBit(1);
950 // ToSendStuffBit(1);
951 // ToSendStuffBit(1);
952 // ToSendStuffBit(1);
953 // }
954
955 // // Send EOF.
956 // for(i = 0; i < 10; i++) {
957 // ToSendStuffBit(0);
958 // ToSendStuffBit(0);
959 // ToSendStuffBit(0);
960 // ToSendStuffBit(0);
961 // }
962 // for(i = 0; i < 2; i++) {
963 // ToSendStuffBit(1);
964 // ToSendStuffBit(1);
965 // ToSendStuffBit(1);
966 // ToSendStuffBit(1);
967 // }
968
969 // // Convert from last byte pos to length
970 // ToSendMax++;
971 // }
972
973 //-----------------------------------------------------------------------------
974 // The software UART that receives commands from the reader, and its state
975 // variables.
976 //-----------------------------------------------------------------------------
977 /*
978 static struct {
979 enum {
980 STATE_UNSYNCD,
981 STATE_GOT_FALLING_EDGE_OF_SOF,
982 STATE_AWAITING_START_BIT,
983 STATE_RECEIVING_DATA
984 } state;
985 uint16_t shiftReg;
986 int bitCnt;
987 int byteCnt;
988 int byteCntMax;
989 int posCnt;
990 uint8_t *output;
991 } Uart;
992 */
993 /* Receive & handle a bit coming from the reader.
994 *
995 * This function is called 4 times per bit (every 2 subcarrier cycles).
996 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
997 *
998 * LED handling:
999 * LED A -> ON once we have received the SOF and are expecting the rest.
1000 * LED A -> OFF once we have received EOF or are in error state or unsynced
1001 *
1002 * Returns: true if we received a EOF
1003 * false if we are still waiting for some more
1004 */
1005 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1006 // {
1007 // switch(Uart.state) {
1008 // case STATE_UNSYNCD:
1009 // if(!bit) {
1010 // // we went low, so this could be the beginning of an SOF
1011 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1012 // Uart.posCnt = 0;
1013 // Uart.bitCnt = 0;
1014 // }
1015 // break;
1016
1017 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1018 // Uart.posCnt++;
1019 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1020 // if(bit) {
1021 // if(Uart.bitCnt > 9) {
1022 // // we've seen enough consecutive
1023 // // zeros that it's a valid SOF
1024 // Uart.posCnt = 0;
1025 // Uart.byteCnt = 0;
1026 // Uart.state = STATE_AWAITING_START_BIT;
1027 // LED_A_ON(); // Indicate we got a valid SOF
1028 // } else {
1029 // // didn't stay down long enough
1030 // // before going high, error
1031 // Uart.state = STATE_UNSYNCD;
1032 // }
1033 // } else {
1034 // // do nothing, keep waiting
1035 // }
1036 // Uart.bitCnt++;
1037 // }
1038 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1039 // if(Uart.bitCnt > 12) {
1040 // // Give up if we see too many zeros without
1041 // // a one, too.
1042 // LED_A_OFF();
1043 // Uart.state = STATE_UNSYNCD;
1044 // }
1045 // break;
1046
1047 // case STATE_AWAITING_START_BIT:
1048 // Uart.posCnt++;
1049 // if(bit) {
1050 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1051 // // stayed high for too long between
1052 // // characters, error
1053 // Uart.state = STATE_UNSYNCD;
1054 // }
1055 // } else {
1056 // // falling edge, this starts the data byte
1057 // Uart.posCnt = 0;
1058 // Uart.bitCnt = 0;
1059 // Uart.shiftReg = 0;
1060 // Uart.state = STATE_RECEIVING_DATA;
1061 // }
1062 // break;
1063
1064 // case STATE_RECEIVING_DATA:
1065 // Uart.posCnt++;
1066 // if(Uart.posCnt == 2) {
1067 // // time to sample a bit
1068 // Uart.shiftReg >>= 1;
1069 // if(bit) {
1070 // Uart.shiftReg |= 0x200;
1071 // }
1072 // Uart.bitCnt++;
1073 // }
1074 // if(Uart.posCnt >= 4) {
1075 // Uart.posCnt = 0;
1076 // }
1077 // if(Uart.bitCnt == 10) {
1078 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1079 // {
1080 // // this is a data byte, with correct
1081 // // start and stop bits
1082 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1083 // Uart.byteCnt++;
1084
1085 // if(Uart.byteCnt >= Uart.byteCntMax) {
1086 // // Buffer overflowed, give up
1087 // LED_A_OFF();
1088 // Uart.state = STATE_UNSYNCD;
1089 // } else {
1090 // // so get the next byte now
1091 // Uart.posCnt = 0;
1092 // Uart.state = STATE_AWAITING_START_BIT;
1093 // }
1094 // } else if (Uart.shiftReg == 0x000) {
1095 // // this is an EOF byte
1096 // LED_A_OFF(); // Finished receiving
1097 // Uart.state = STATE_UNSYNCD;
1098 // if (Uart.byteCnt != 0) {
1099 // return TRUE;
1100 // }
1101 // } else {
1102 // // this is an error
1103 // LED_A_OFF();
1104 // Uart.state = STATE_UNSYNCD;
1105 // }
1106 // }
1107 // break;
1108
1109 // default:
1110 // LED_A_OFF();
1111 // Uart.state = STATE_UNSYNCD;
1112 // break;
1113 // }
1114
1115 // return FALSE;
1116 // }
1117 /*
1118
1119 static void UartReset() {
1120 Uart.byteCntMax = 3;
1121 Uart.state = STATE_UNSYNCD;
1122 Uart.byteCnt = 0;
1123 Uart.bitCnt = 0;
1124 Uart.posCnt = 0;
1125 memset(Uart.output, 0x00, 3);
1126 }
1127 */
1128 // static void UartInit(uint8_t *data) {
1129 // Uart.output = data;
1130 // UartReset();
1131 // }
1132
1133 //=============================================================================
1134 // An LEGIC reader. We take layer two commands, code them
1135 // appropriately, and then send them to the tag. We then listen for the
1136 // tag's response, which we leave in the buffer to be demodulated on the
1137 // PC side.
1138 //=============================================================================
1139 /*
1140 static struct {
1141 enum {
1142 DEMOD_UNSYNCD,
1143 DEMOD_PHASE_REF_TRAINING,
1144 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1145 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1146 DEMOD_AWAITING_START_BIT,
1147 DEMOD_RECEIVING_DATA
1148 } state;
1149 int bitCount;
1150 int posCount;
1151 int thisBit;
1152 uint16_t shiftReg;
1153 uint8_t *output;
1154 int len;
1155 int sumI;
1156 int sumQ;
1157 } Demod;
1158 */
1159 /*
1160 * Handles reception of a bit from the tag
1161 *
1162 * This function is called 2 times per bit (every 4 subcarrier cycles).
1163 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1164 *
1165 * LED handling:
1166 * LED C -> ON once we have received the SOF and are expecting the rest.
1167 * LED C -> OFF once we have received EOF or are unsynced
1168 *
1169 * Returns: true if we received a EOF
1170 * false if we are still waiting for some more
1171 *
1172 */
1173
1174 /*
1175 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1176 {
1177 int v = 0;
1178 int ai = ABS(ci);
1179 int aq = ABS(cq);
1180 int halfci = (ai >> 1);
1181 int halfcq = (aq >> 1);
1182
1183 switch(Demod.state) {
1184 case DEMOD_UNSYNCD:
1185
1186 CHECK_FOR_SUBCARRIER()
1187
1188 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1189 Demod.state = DEMOD_PHASE_REF_TRAINING;
1190 Demod.sumI = ci;
1191 Demod.sumQ = cq;
1192 Demod.posCount = 1;
1193 }
1194 break;
1195
1196 case DEMOD_PHASE_REF_TRAINING:
1197 if(Demod.posCount < 8) {
1198
1199 CHECK_FOR_SUBCARRIER()
1200
1201 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1202 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1203 // note: synchronization time > 80 1/fs
1204 Demod.sumI += ci;
1205 Demod.sumQ += cq;
1206 ++Demod.posCount;
1207 } else {
1208 // subcarrier lost
1209 Demod.state = DEMOD_UNSYNCD;
1210 }
1211 } else {
1212 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1213 }
1214 break;
1215
1216 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1217
1218 MAKE_SOFT_DECISION()
1219
1220 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1221 // logic '0' detected
1222 if (v <= 0) {
1223
1224 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1225
1226 // start of SOF sequence
1227 Demod.posCount = 0;
1228 } else {
1229 // maximum length of TR1 = 200 1/fs
1230 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1231 }
1232 ++Demod.posCount;
1233 break;
1234
1235 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1236 ++Demod.posCount;
1237
1238 MAKE_SOFT_DECISION()
1239
1240 if(v > 0) {
1241 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1242 if(Demod.posCount < 10*2) {
1243 Demod.state = DEMOD_UNSYNCD;
1244 } else {
1245 LED_C_ON(); // Got SOF
1246 Demod.state = DEMOD_AWAITING_START_BIT;
1247 Demod.posCount = 0;
1248 Demod.len = 0;
1249 }
1250 } else {
1251 // low phase of SOF too long (> 12 etu)
1252 if(Demod.posCount > 13*2) {
1253 Demod.state = DEMOD_UNSYNCD;
1254 LED_C_OFF();
1255 }
1256 }
1257 break;
1258
1259 case DEMOD_AWAITING_START_BIT:
1260 ++Demod.posCount;
1261
1262 MAKE_SOFT_DECISION()
1263
1264 if(v > 0) {
1265 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1266 if(Demod.posCount > 3*2) {
1267 Demod.state = DEMOD_UNSYNCD;
1268 LED_C_OFF();
1269 }
1270 } else {
1271 // start bit detected
1272 Demod.bitCount = 0;
1273 Demod.posCount = 1; // this was the first half
1274 Demod.thisBit = v;
1275 Demod.shiftReg = 0;
1276 Demod.state = DEMOD_RECEIVING_DATA;
1277 }
1278 break;
1279
1280 case DEMOD_RECEIVING_DATA:
1281
1282 MAKE_SOFT_DECISION()
1283
1284 if(Demod.posCount == 0) {
1285 // first half of bit
1286 Demod.thisBit = v;
1287 Demod.posCount = 1;
1288 } else {
1289 // second half of bit
1290 Demod.thisBit += v;
1291 Demod.shiftReg >>= 1;
1292 // logic '1'
1293 if(Demod.thisBit > 0)
1294 Demod.shiftReg |= 0x200;
1295
1296 ++Demod.bitCount;
1297
1298 if(Demod.bitCount == 10) {
1299
1300 uint16_t s = Demod.shiftReg;
1301
1302 if((s & 0x200) && !(s & 0x001)) {
1303 // stop bit == '1', start bit == '0'
1304 uint8_t b = (s >> 1);
1305 Demod.output[Demod.len] = b;
1306 ++Demod.len;
1307 Demod.state = DEMOD_AWAITING_START_BIT;
1308 } else {
1309 Demod.state = DEMOD_UNSYNCD;
1310 LED_C_OFF();
1311
1312 if(s == 0x000) {
1313 // This is EOF (start, stop and all data bits == '0'
1314 return TRUE;
1315 }
1316 }
1317 }
1318 Demod.posCount = 0;
1319 }
1320 break;
1321
1322 default:
1323 Demod.state = DEMOD_UNSYNCD;
1324 LED_C_OFF();
1325 break;
1326 }
1327 return FALSE;
1328 }
1329 */
1330 /*
1331 // Clear out the state of the "UART" that receives from the tag.
1332 static void DemodReset() {
1333 Demod.len = 0;
1334 Demod.state = DEMOD_UNSYNCD;
1335 Demod.posCount = 0;
1336 Demod.sumI = 0;
1337 Demod.sumQ = 0;
1338 Demod.bitCount = 0;
1339 Demod.thisBit = 0;
1340 Demod.shiftReg = 0;
1341 memset(Demod.output, 0x00, 3);
1342 }
1343
1344 static void DemodInit(uint8_t *data) {
1345 Demod.output = data;
1346 DemodReset();
1347 }
1348 */
1349
1350 /*
1351 * Demodulate the samples we received from the tag, also log to tracebuffer
1352 * quiet: set to 'TRUE' to disable debug output
1353 */
1354
1355 /*
1356 #define LEGIC_DMA_BUFFER_SIZE 256
1357
1358 static void GetSamplesForLegicDemod(int n, bool quiet)
1359 {
1360 int max = 0;
1361 bool gotFrame = FALSE;
1362 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1363 int ci, cq, samples = 0;
1364
1365 BigBuf_free();
1366
1367 // And put the FPGA in the appropriate mode
1368 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1369
1370 // The response (tag -> reader) that we're receiving.
1371 // Set up the demodulator for tag -> reader responses.
1372 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1373
1374 // The DMA buffer, used to stream samples from the FPGA
1375 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1376 int8_t *upTo = dmaBuf;
1377
1378 // Setup and start DMA.
1379 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1380 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1381 return;
1382 }
1383
1384 // Signal field is ON with the appropriate LED:
1385 LED_D_ON();
1386 for(;;) {
1387 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1388 if(behindBy > max) max = behindBy;
1389
1390 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1391 ci = upTo[0];
1392 cq = upTo[1];
1393 upTo += 2;
1394 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1395 upTo = dmaBuf;
1396 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1397 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1398 }
1399 lastRxCounter -= 2;
1400 if(lastRxCounter <= 0)
1401 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1402
1403 samples += 2;
1404
1405 gotFrame = HandleLegicSamplesDemod(ci , cq );
1406 if ( gotFrame )
1407 break;
1408 }
1409
1410 if(samples > n || gotFrame)
1411 break;
1412 }
1413
1414 FpgaDisableSscDma();
1415
1416 if (!quiet && Demod.len == 0) {
1417 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1418 max,
1419 samples,
1420 gotFrame,
1421 Demod.len,
1422 Demod.sumI,
1423 Demod.sumQ
1424 );
1425 }
1426
1427 //Tracing
1428 if (Demod.len > 0) {
1429 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1430 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1431 }
1432 }
1433
1434 */
1435
1436 //-----------------------------------------------------------------------------
1437 // Transmit the command (to the tag) that was placed in ToSend[].
1438 //-----------------------------------------------------------------------------
1439 /*
1440 static void TransmitForLegic(void)
1441 {
1442 int c;
1443
1444 FpgaSetupSsc();
1445
1446 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1447 AT91C_BASE_SSC->SSC_THR = 0xff;
1448
1449 // Signal field is ON with the appropriate Red LED
1450 LED_D_ON();
1451
1452 // Signal we are transmitting with the Green LED
1453 LED_B_ON();
1454 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1455
1456 for(c = 0; c < 10;) {
1457 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1458 AT91C_BASE_SSC->SSC_THR = 0xff;
1459 c++;
1460 }
1461 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1462 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1463 (void)r;
1464 }
1465 WDT_HIT();
1466 }
1467
1468 c = 0;
1469 for(;;) {
1470 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1471 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1472 legic_prng_forward(1); // forward the lfsr
1473 c++;
1474 if(c >= ToSendMax) {
1475 break;
1476 }
1477 }
1478 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1479 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1480 (void)r;
1481 }
1482 WDT_HIT();
1483 }
1484 LED_B_OFF();
1485 }
1486 */
1487
1488 //-----------------------------------------------------------------------------
1489 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1490 // so that it is ready to transmit to the tag using TransmitForLegic().
1491 //-----------------------------------------------------------------------------
1492 /*
1493 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1494 {
1495 int i, j;
1496 uint8_t b;
1497
1498 ToSendReset();
1499
1500 // Send SOF
1501 for(i = 0; i < 7; i++)
1502 ToSendStuffBit(1);
1503
1504
1505 for(i = 0; i < cmdlen; i++) {
1506 // Start bit
1507 ToSendStuffBit(0);
1508
1509 // Data bits
1510 b = cmd[i];
1511 for(j = 0; j < bits; j++) {
1512 if(b & 1) {
1513 ToSendStuffBit(1);
1514 } else {
1515 ToSendStuffBit(0);
1516 }
1517 b >>= 1;
1518 }
1519 }
1520
1521 // Convert from last character reference to length
1522 ++ToSendMax;
1523 }
1524 */
1525 /**
1526 Convenience function to encode, transmit and trace Legic comms
1527 **/
1528 /*
1529 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1530 {
1531 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1532 TransmitForLegic();
1533 if (tracing) {
1534 uint8_t parity[1] = {0x00};
1535 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1536 }
1537 }
1538
1539 */
1540 // Set up LEGIC communication
1541 /*
1542 void ice_legic_setup() {
1543
1544 // standard things.
1545 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1546 BigBuf_free(); BigBuf_Clear_ext(false);
1547 clear_trace();
1548 set_tracing(TRUE);
1549 DemodReset();
1550 UartReset();
1551
1552 // Set up the synchronous serial port
1553 FpgaSetupSsc();
1554
1555 // connect Demodulated Signal to ADC:
1556 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1557
1558 // Signal field is on with the appropriate LED
1559 LED_D_ON();
1560 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1561 SpinDelay(20);
1562 // Start the timer
1563 //StartCountSspClk();
1564
1565 // initalize CRC
1566 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1567
1568 // initalize prng
1569 legic_prng_init(0);
1570 }
1571 */
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