cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c

   1 //-----------------------------------------------------------------------------
   2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
   3 // at your option, any later version. See the LICENSE.txt file for the text of
   4 // the license.
   5 //-----------------------------------------------------------------------------
   6 // Miscellaneous routines for low frequency tag operations.
   7 // Tags supported here so far are Texas Instruments (TI), HID
   8 // Also routines for raw mode reading/simulating of LF waveform
   9 //-----------------------------------------------------------------------------
  10
  11 #include "proxmark3.h"
  12 #include "apps.h"
  13 #include "util.h"
  14 #include "hitag2.h"
  15 #include "crc16.h"
  16 #include "string.h"
  17 #include "lfdemod.h"
  18
  19
  20 /**
  21 * Does the sample acquisition. If threshold is specified, the actual sampling
  22 * is not commenced until the threshold has been reached.
  23 * @param trigger_threshold - the threshold
  24 * @param silent - is true, now outputs are made. If false, dbprints the status
  25 */
  26 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
  27 {
  28     uint8_t *dest = BigBuf_get_addr();
  29     int n = BigBuf_max_traceLen();
  30     int i;
  31
  32     memset(dest, 0, n);
  33     i = 0;
  34     for(;;) {
  35         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
  36             AT91C_BASE_SSC->SSC_THR = 0x43;
  37             LED_D_ON();
  38         }
  39         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
  40             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
  41             LED_D_OFF();
  42             if (trigger_threshold != -1 && dest[i] < trigger_threshold)
  43                 continue;
  44             else
  45                 trigger_threshold = -1;
  46             if (++i >= n) break;
  47         }
  48     }
  49     if(!silent)
  50     {
  51         Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
  52                  dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
  53
  54     }
  55 }
  56 /**
  57 * Perform sample aquisition.
  58 */
  59 void DoAcquisition125k(int trigger_threshold)
  60 {
  61     DoAcquisition125k_internal(trigger_threshold, false);
  62 }
  63
  64 /**
  65 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
  66 * if not already loaded, sets divisor and starts up the antenna.
  67 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
  68 *                                  0 or 95 ==> 125 KHz
  69 *
  70 **/
  71 void LFSetupFPGAForADC(int divisor, bool lf_field)
  72 {
  73     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
  74     if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
  75         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
  76     else if (divisor == 0)
  77         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
  78     else
  79         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
  80
  81     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
  82
  83     // Connect the A/D to the peak-detected low-frequency path.
  84     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
  85     // Give it a bit of time for the resonant antenna to settle.
  86     SpinDelay(50);
  87     // Now set up the SSC to get the ADC samples that are now streaming at us.
  88     FpgaSetupSsc();
  89 }
  90 /**
  91 * Initializes the FPGA, and acquires the samples.
  92 **/
  93 void AcquireRawAdcSamples125k(int divisor)
  94 {
  95     LFSetupFPGAForADC(divisor, true);
  96     // Now call the acquisition routine
  97     DoAcquisition125k_internal(-1,false);
  98 }
  99 /**
 100 * Initializes the FPGA for snoop-mode, and acquires the samples.
 101 **/
 102
 103 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
 104 {
 105     LFSetupFPGAForADC(divisor, false);
 106     DoAcquisition125k(trigger_threshold);
 107 }
 108
 109 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 110 {
 111
 112     /* Make sure the tag is reset */
 113     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 114     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 115     SpinDelay(2500);
 116
 117
 118     int divisor_used = 95; // 125 KHz
 119     // see if 'h' was specified
 120
 121     if (command[strlen((char *) command) - 1] == 'h')
 122         divisor_used = 88; // 134.8 KHz
 123
 124
 125     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 126     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 127     // Give it a bit of time for the resonant antenna to settle.
 128     SpinDelay(50);
 129
 130     // And a little more time for the tag to fully power up
 131     SpinDelay(2000);
 132
 133     // Now set up the SSC to get the ADC samples that are now streaming at us.
 134     FpgaSetupSsc();
 135
 136     // now modulate the reader field
 137     while(*command != '\0' && *command != ' ') {
 138         FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 139         LED_D_OFF();
 140         SpinDelayUs(delay_off);
 141         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 142
 143         FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 144         LED_D_ON();
 145         if(*(command++) == '0')
 146             SpinDelayUs(period_0);
 147         else
 148             SpinDelayUs(period_1);
 149     }
 150     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 151     LED_D_OFF();
 152     SpinDelayUs(delay_off);
 153     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 154
 155     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 156
 157     // now do the read
 158     DoAcquisition125k(-1);
 159 }
 160
 161 /* blank r/w tag data stream
 162 ...0000000000000000 01111111
 163 1010101010101010101010101010101010101010101010101010101010101010
 164 0011010010100001
 165 01111111
 166 101010101010101[0]000...
 167
 168 [5555fe852c5555555555555555fe0000]
 169 */
 170 void ReadTItag(void)
 171 {
 172     // some hardcoded initial params
 173     // when we read a TI tag we sample the zerocross line at 2Mhz
 174     // TI tags modulate a 1 as 16 cycles of 123.2Khz
 175     // TI tags modulate a 0 as 16 cycles of 134.2Khz
 176  #define FSAMPLE 2000000
 177  #define FREQLO 123200
 178  #define FREQHI 134200
 179
 180     signed char *dest = (signed char *)BigBuf_get_addr();
 181     uint16_t n = BigBuf_max_traceLen();
 182     // 128 bit shift register [shift3:shift2:shift1:shift0]
 183     uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
 184
 185     int i, cycles=0, samples=0;
 186     // how many sample points fit in 16 cycles of each frequency
 187     uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
 188     // when to tell if we're close enough to one freq or another
 189     uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 190
 191     // TI tags charge at 134.2Khz
 192     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 193     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 194
 195     // Place FPGA in passthrough mode, in this mode the CROSS_LO line
 196     // connects to SSP_DIN and the SSP_DOUT logic level controls
 197     // whether we're modulating the antenna (high)
 198     // or listening to the antenna (low)
 199     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
 200
 201     // get TI tag data into the buffer
 202     AcquireTiType();
 203
 204     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 205
 206     for (i=0; i<n-1; i++) {
 207         // count cycles by looking for lo to hi zero crossings
 208         if ( (dest[i]<0) && (dest[i+1]>0) ) {
 209             cycles++;
 210             // after 16 cycles, measure the frequency
 211             if (cycles>15) {
 212                 cycles=0;
 213                 samples=i-samples; // number of samples in these 16 cycles
 214
 215                 // TI bits are coming to us lsb first so shift them
 216                 // right through our 128 bit right shift register
 217                 shift0 = (shift0>>1) | (shift1 << 31);
 218                 shift1 = (shift1>>1) | (shift2 << 31);
 219                 shift2 = (shift2>>1) | (shift3 << 31);
 220                 shift3 >>= 1;
 221
 222                 // check if the cycles fall close to the number
 223                 // expected for either the low or high frequency
 224                 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
 225                     // low frequency represents a 1
 226                     shift3 |= (1<<31);
 227                 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
 228                     // high frequency represents a 0
 229                 } else {
 230                     // probably detected a gay waveform or noise
 231                     // use this as gaydar or discard shift register and start again
 232                     shift3 = shift2 = shift1 = shift0 = 0;
 233                 }
 234                 samples = i;
 235
 236                 // for each bit we receive, test if we've detected a valid tag
 237
 238                 // if we see 17 zeroes followed by 6 ones, we might have a tag
 239                 // remember the bits are backwards
 240                 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
 241                     // if start and end bytes match, we have a tag so break out of the loop
 242                     if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
 243                         cycles = 0xF0B; //use this as a flag (ugly but whatever)
 244                         break;
 245                     }
 246                 }
 247             }
 248         }
 249     }
 250
 251     // if flag is set we have a tag
 252     if (cycles!=0xF0B) {
 253         DbpString("Info: No valid tag detected.");
 254     } else {
 255         // put 64 bit data into shift1 and shift0
 256         shift0 = (shift0>>24) | (shift1 << 8);
 257         shift1 = (shift1>>24) | (shift2 << 8);
 258
 259         // align 16 bit crc into lower half of shift2
 260         shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
 261
 262         // if r/w tag, check ident match
 263                 if (shift3 & (1<<15) ) {
 264             DbpString("Info: TI tag is rewriteable");
 265             // only 15 bits compare, last bit of ident is not valid
 266                         if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
 267                 DbpString("Error: Ident mismatch!");
 268             } else {
 269                 DbpString("Info: TI tag ident is valid");
 270             }
 271         } else {
 272             DbpString("Info: TI tag is readonly");
 273         }
 274
 275         // WARNING the order of the bytes in which we calc crc below needs checking
 276         // i'm 99% sure the crc algorithm is correct, but it may need to eat the
 277         // bytes in reverse or something
 278         // calculate CRC
 279         uint32_t crc=0;
 280
 281         crc = update_crc16(crc, (shift0)&0xff);
 282         crc = update_crc16(crc, (shift0>>8)&0xff);
 283         crc = update_crc16(crc, (shift0>>16)&0xff);
 284         crc = update_crc16(crc, (shift0>>24)&0xff);
 285         crc = update_crc16(crc, (shift1)&0xff);
 286         crc = update_crc16(crc, (shift1>>8)&0xff);
 287         crc = update_crc16(crc, (shift1>>16)&0xff);
 288         crc = update_crc16(crc, (shift1>>24)&0xff);
 289
 290         Dbprintf("Info: Tag data: %x%08x, crc=%x",
 291                  (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
 292         if (crc != (shift2&0xffff)) {
 293             Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
 294         } else {
 295             DbpString("Info: CRC is good");
 296         }
 297     }
 298 }
 299
 300 void WriteTIbyte(uint8_t b)
 301 {
 302     int i = 0;
 303
 304     // modulate 8 bits out to the antenna
 305     for (i=0; i<8; i++)
 306     {
 307         if (b&(1<<i)) {
 308             // stop modulating antenna
 309             LOW(GPIO_SSC_DOUT);
 310             SpinDelayUs(1000);
 311             // modulate antenna
 312             HIGH(GPIO_SSC_DOUT);
 313             SpinDelayUs(1000);
 314         } else {
 315             // stop modulating antenna
 316             LOW(GPIO_SSC_DOUT);
 317             SpinDelayUs(300);
 318             // modulate antenna
 319             HIGH(GPIO_SSC_DOUT);
 320             SpinDelayUs(1700);
 321         }
 322     }
 323 }
 324
 325 void AcquireTiType(void)
 326 {
 327     int i, j, n;
 328     // tag transmission is <20ms, sampling at 2M gives us 40K samples max
 329     // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
 330  #define TIBUFLEN 1250
 331
 332     // clear buffer
 333         uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
 334     memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
 335
 336     // Set up the synchronous serial port
 337     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
 338     AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
 339
 340     // steal this pin from the SSP and use it to control the modulation
 341     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 342     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 343
 344     AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
 345     AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
 346
 347     // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
 348     // 48/2 = 24 MHz clock must be divided by 12
 349     AT91C_BASE_SSC->SSC_CMR = 12;
 350
 351     AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
 352     AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
 353     AT91C_BASE_SSC->SSC_TCMR = 0;
 354     AT91C_BASE_SSC->SSC_TFMR = 0;
 355
 356     LED_D_ON();
 357
 358     // modulate antenna
 359     HIGH(GPIO_SSC_DOUT);
 360
 361     // Charge TI tag for 50ms.
 362     SpinDelay(50);
 363
 364     // stop modulating antenna and listen
 365     LOW(GPIO_SSC_DOUT);
 366
 367     LED_D_OFF();
 368
 369     i = 0;
 370     for(;;) {
 371         if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
 372             BigBuf[i] = AT91C_BASE_SSC->SSC_RHR;        // store 32 bit values in buffer
 373             i++; if(i >= TIBUFLEN) break;
 374         }
 375         WDT_HIT();
 376     }
 377
 378     // return stolen pin to SSP
 379     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
 380     AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
 381
 382     char *dest = (char *)BigBuf_get_addr();
 383     n = TIBUFLEN*32;
 384     // unpack buffer
 385     for (i=TIBUFLEN-1; i>=0; i--) {
 386         for (j=0; j<32; j++) {
 387             if(BigBuf[i] & (1 << j)) {
 388                 dest[--n] = 1;
 389             } else {
 390                 dest[--n] = -1;
 391             }
 392         }
 393     }
 394 }
 395
 396 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
 397 // if crc provided, it will be written with the data verbatim (even if bogus)
 398 // if not provided a valid crc will be computed from the data and written.
 399 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 400 {
 401     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 402     if(crc == 0) {
 403         crc = update_crc16(crc, (idlo)&0xff);
 404         crc = update_crc16(crc, (idlo>>8)&0xff);
 405         crc = update_crc16(crc, (idlo>>16)&0xff);
 406         crc = update_crc16(crc, (idlo>>24)&0xff);
 407         crc = update_crc16(crc, (idhi)&0xff);
 408         crc = update_crc16(crc, (idhi>>8)&0xff);
 409         crc = update_crc16(crc, (idhi>>16)&0xff);
 410         crc = update_crc16(crc, (idhi>>24)&0xff);
 411     }
 412     Dbprintf("Writing to tag: %x%08x, crc=%x",
 413              (unsigned int) idhi, (unsigned int) idlo, crc);
 414
 415     // TI tags charge at 134.2Khz
 416     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 417     // Place FPGA in passthrough mode, in this mode the CROSS_LO line
 418     // connects to SSP_DIN and the SSP_DOUT logic level controls
 419     // whether we're modulating the antenna (high)
 420     // or listening to the antenna (low)
 421     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
 422     LED_A_ON();
 423
 424     // steal this pin from the SSP and use it to control the modulation
 425     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 426     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 427
 428     // writing algorithm:
 429     // a high bit consists of a field off for 1ms and field on for 1ms
 430     // a low bit consists of a field off for 0.3ms and field on for 1.7ms
 431     // initiate a charge time of 50ms (field on) then immediately start writing bits
 432     // start by writing 0xBB (keyword) and 0xEB (password)
 433     // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
 434     // finally end with 0x0300 (write frame)
 435     // all data is sent lsb firts
 436     // finish with 15ms programming time
 437
 438     // modulate antenna
 439     HIGH(GPIO_SSC_DOUT);
 440     SpinDelay(50);      // charge time
 441
 442     WriteTIbyte(0xbb); // keyword
 443     WriteTIbyte(0xeb); // password
 444     WriteTIbyte( (idlo    )&0xff );
 445     WriteTIbyte( (idlo>>8 )&0xff );
 446     WriteTIbyte( (idlo>>16)&0xff );
 447     WriteTIbyte( (idlo>>24)&0xff );
 448     WriteTIbyte( (idhi    )&0xff );
 449     WriteTIbyte( (idhi>>8 )&0xff );
 450     WriteTIbyte( (idhi>>16)&0xff );
 451     WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
 452     WriteTIbyte( (crc     )&0xff ); // crc lo
 453     WriteTIbyte( (crc>>8  )&0xff ); // crc hi
 454     WriteTIbyte(0x00); // write frame lo
 455     WriteTIbyte(0x03); // write frame hi
 456     HIGH(GPIO_SSC_DOUT);
 457     SpinDelay(50);      // programming time
 458
 459     LED_A_OFF();
 460
 461     // get TI tag data into the buffer
 462     AcquireTiType();
 463
 464     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 465     DbpString("Now use tiread to check");
 466 }
 467
 468 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 469 {
 470     int i;
 471     uint8_t *tab = BigBuf_get_addr();
 472
 473     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 474     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
 475
 476     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
 477
 478     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 479     AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
 480
 481 #define SHORT_COIL()    LOW(GPIO_SSC_DOUT)
 482 #define OPEN_COIL()             HIGH(GPIO_SSC_DOUT)
 483
 484     i = 0;
 485     for(;;) {
 486         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
 487             if(BUTTON_PRESS()) {
 488                 DbpString("Stopped");
 489                 return;
 490             }
 491             WDT_HIT();
 492         }
 493
 494         if (ledcontrol)
 495             LED_D_ON();
 496
 497         if(tab[i])
 498             OPEN_COIL();
 499         else
 500             SHORT_COIL();
 501
 502         if (ledcontrol)
 503             LED_D_OFF();
 504
 505         while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
 506             if(BUTTON_PRESS()) {
 507                 DbpString("Stopped");
 508                 return;
 509             }
 510             WDT_HIT();
 511         }
 512
 513         i++;
 514         if(i == period) {
 515             i = 0;
 516             if (gap) {
 517                 SHORT_COIL();
 518                 SpinDelayUs(gap);
 519             }
 520         }
 521     }
 522 }
 523
 524 #define DEBUG_FRAME_CONTENTS 1
 525 void SimulateTagLowFrequencyBidir(int divisor, int t0)
 526 {
 527 }
 528
 529 // compose fc/8 fc/10 waveform
 530 static void fc(int c, int *n) {
 531     uint8_t *dest = BigBuf_get_addr();
 532     int idx;
 533
 534     // for when we want an fc8 pattern every 4 logical bits
 535     if(c==0) {
 536         dest[((*n)++)]=1;
 537         dest[((*n)++)]=1;
 538         dest[((*n)++)]=0;
 539         dest[((*n)++)]=0;
 540         dest[((*n)++)]=0;
 541         dest[((*n)++)]=0;
 542         dest[((*n)++)]=0;
 543         dest[((*n)++)]=0;
 544     }
 545     //  an fc/8  encoded bit is a bit pattern of  11000000  x6 = 48 samples
 546     if(c==8) {
 547         for (idx=0; idx<6; idx++) {
 548             dest[((*n)++)]=1;
 549             dest[((*n)++)]=1;
 550             dest[((*n)++)]=0;
 551             dest[((*n)++)]=0;
 552             dest[((*n)++)]=0;
 553             dest[((*n)++)]=0;
 554             dest[((*n)++)]=0;
 555             dest[((*n)++)]=0;
 556         }
 557     }
 558
 559     //  an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
 560     if(c==10) {
 561         for (idx=0; idx<5; idx++) {
 562             dest[((*n)++)]=1;
 563             dest[((*n)++)]=1;
 564             dest[((*n)++)]=1;
 565             dest[((*n)++)]=0;
 566             dest[((*n)++)]=0;
 567             dest[((*n)++)]=0;
 568             dest[((*n)++)]=0;
 569             dest[((*n)++)]=0;
 570             dest[((*n)++)]=0;
 571             dest[((*n)++)]=0;
 572         }
 573     }
 574 }
 575
 576 // prepare a waveform pattern in the buffer based on the ID given then
 577 // simulate a HID tag until the button is pressed
 578 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 579 {
 580     int n=0, i=0;
 581     /*
 582      HID tag bitstream format
 583      The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
 584      A 1 bit is represented as 6 fc8 and 5 fc10 patterns
 585      A 0 bit is represented as 5 fc10 and 6 fc8 patterns
 586      A fc8 is inserted before every 4 bits
 587      A special start of frame pattern is used consisting a0b0 where a and b are neither 0
 588      nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
 589     */
 590
 591     if (hi>0xFFF) {
 592         DbpString("Tags can only have 44 bits.");
 593         return;
 594     }
 595     fc(0,&n);
 596     // special start of frame marker containing invalid bit sequences
 597     fc(8,  &n); fc(8,  &n);     // invalid
 598     fc(8,  &n); fc(10, &n); // logical 0
 599     fc(10, &n); fc(10, &n); // invalid
 600     fc(8,  &n); fc(10, &n); // logical 0
 601
 602     WDT_HIT();
 603     // manchester encode bits 43 to 32
 604     for (i=11; i>=0; i--) {
 605         if ((i%4)==3) fc(0,&n);
 606         if ((hi>>i)&1) {
 607             fc(10, &n); fc(8,  &n);             // low-high transition
 608         } else {
 609             fc(8,  &n); fc(10, &n);             // high-low transition
 610         }
 611     }
 612
 613     WDT_HIT();
 614     // manchester encode bits 31 to 0
 615     for (i=31; i>=0; i--) {
 616         if ((i%4)==3) fc(0,&n);
 617         if ((lo>>i)&1) {
 618             fc(10, &n); fc(8,  &n);             // low-high transition
 619         } else {
 620             fc(8,  &n); fc(10, &n);             // high-low transition
 621         }
 622     }
 623
 624     if (ledcontrol)
 625         LED_A_ON();
 626     SimulateTagLowFrequency(n, 0, ledcontrol);
 627
 628     if (ledcontrol)
 629         LED_A_OFF();
 630 }
 631
 632 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
 633 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 634 {
 635     uint8_t *dest = BigBuf_get_addr();
 636     const size_t sizeOfBigBuff = BigBuf_max_traceLen();
 637     size_t size = 0;
 638     uint32_t hi2=0, hi=0, lo=0;
 639     int idx=0;
 640     // Configure to go in 125Khz listen mode
 641     LFSetupFPGAForADC(95, true);
 642
 643     while(!BUTTON_PRESS()) {
 644
 645         WDT_HIT();
 646         if (ledcontrol) LED_A_ON();
 647
 648         DoAcquisition125k_internal(-1,true);
 649         // FSK demodulator
 650         size = sizeOfBigBuff;  //variable size will change after demod so re initialize it before use
 651                 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
 652
 653                 if (idx>0 && lo>0){
 654             // final loop, go over previously decoded manchester data and decode into usable tag ID
 655             // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
 656             if (hi2 != 0){ //extra large HID tags
 657                 Dbprintf("TAG ID: %x%08x%08x (%d)",
 658                          (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
 659             }else {  //standard HID tags <38 bits
 660                 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
 661                 uint8_t bitlen = 0;
 662                 uint32_t fc = 0;
 663                 uint32_t cardnum = 0;
 664                                 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
 665                     uint32_t lo2=0;
 666                     lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
 667                     uint8_t idx3 = 1;
 668                                         while(lo2 > 1){ //find last bit set to 1 (format len bit)
 669                                                 lo2=lo2 >> 1;
 670                         idx3++;
 671                     }
 672                                         bitlen = idx3+19;
 673                     fc =0;
 674                     cardnum=0;
 675                                         if(bitlen == 26){
 676                         cardnum = (lo>>1)&0xFFFF;
 677                         fc = (lo>>17)&0xFF;
 678                     }
 679                                         if(bitlen == 37){
 680                         cardnum = (lo>>1)&0x7FFFF;
 681                         fc = ((hi&0xF)<<12)|(lo>>20);
 682                     }
 683                                         if(bitlen == 34){
 684                         cardnum = (lo>>1)&0xFFFF;
 685                         fc= ((hi&1)<<15)|(lo>>17);
 686                     }
 687                                         if(bitlen == 35){
 688                         cardnum = (lo>>1)&0xFFFFF;
 689                         fc = ((hi&1)<<11)|(lo>>21);
 690                     }
 691                 }
 692                 else { //if bit 38 is not set then 37 bit format is used
 693                     bitlen= 37;
 694                     fc =0;
 695                     cardnum=0;
 696                     if(bitlen==37){
 697                         cardnum = (lo>>1)&0x7FFFF;
 698                         fc = ((hi&0xF)<<12)|(lo>>20);
 699                     }
 700                 }
 701                 //Dbprintf("TAG ID: %x%08x (%d)",
 702                 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
 703                 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
 704                          (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
 705                          (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
 706             }
 707             if (findone){
 708                 if (ledcontrol) LED_A_OFF();
 709                 return;
 710             }
 711             // reset
 712             hi2 = hi = lo = 0;
 713         }
 714         WDT_HIT();
 715     }
 716     DbpString("Stopped");
 717     if (ledcontrol) LED_A_OFF();
 718 }
 719
 720 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
 721 {
 722     uint8_t *dest = BigBuf_get_addr();
 723
 724         size_t size=0, idx=0;
 725     int clk=0, invert=0, errCnt=0;
 726     uint64_t lo=0;
 727     // Configure to go in 125Khz listen mode
 728     LFSetupFPGAForADC(95, true);
 729
 730     while(!BUTTON_PRESS()) {
 731
 732         WDT_HIT();
 733         if (ledcontrol) LED_A_ON();
 734
 735         DoAcquisition125k_internal(-1,true);
 736         size  = BigBuf_max_traceLen();
 737         //Dbprintf("DEBUG: Buffer got");
 738                 //askdemod and manchester decode
 739                 errCnt = askmandemod(dest, &size, &clk, &invert);
 740         //Dbprintf("DEBUG: ASK Got");
 741         WDT_HIT();
 742
 743         if (errCnt>=0){
 744                         lo = Em410xDecode(dest, &size, &idx);
 745             //Dbprintf("DEBUG: EM GOT");
 746             if (lo>0){
 747                                 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
 748                                     (uint32_t)(lo>>32),
 749                                     (uint32_t)lo,
 750                                     (uint32_t)(lo&0xFFFF),
 751                                     (uint32_t)((lo>>16LL) & 0xFF),
 752                                     (uint32_t)(lo & 0xFFFFFF));
 753             }
 754             if (findone){
 755                 if (ledcontrol) LED_A_OFF();
 756                 return;
 757             }
 758         } else{
 759             //Dbprintf("DEBUG: No Tag");
 760         }
 761         WDT_HIT();
 762         lo = 0;
 763         clk=0;
 764         invert=0;
 765         errCnt=0;
 766         size=0;
 767     }
 768     DbpString("Stopped");
 769     if (ledcontrol) LED_A_OFF();
 770 }
 771
 772 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 773 {
 774     uint8_t *dest = BigBuf_get_addr();
 775     int idx=0;
 776     uint32_t code=0, code2=0;
 777     uint8_t version=0;
 778     uint8_t facilitycode=0;
 779     uint16_t number=0;
 780     // Configure to go in 125Khz listen mode
 781     LFSetupFPGAForADC(95, true);
 782
 783     while(!BUTTON_PRESS()) {
 784         WDT_HIT();
 785         if (ledcontrol) LED_A_ON();
 786         DoAcquisition125k_internal(-1,true);
 787         //fskdemod and get start index
 788         WDT_HIT();
 789         idx = IOdemodFSK(dest, BigBuf_max_traceLen());
 790         if (idx>0){
 791             //valid tag found
 792
 793             //Index map
 794             //0           10          20          30          40          50          60
 795             //|           |           |           |           |           |           |
 796             //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
 797             //-----------------------------------------------------------------------------
 798             //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
 799             //
 800             //XSF(version)facility:codeone+codetwo
 801             //Handle the data
 802             if(findone){ //only print binary if we are doing one
 803                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
 804                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
 805                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
 806                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
 807                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
 808                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
 809                 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
 810             }
 811             code = bytebits_to_byte(dest+idx,32);
 812             code2 = bytebits_to_byte(dest+idx+32,32);
 813             version = bytebits_to_byte(dest+idx+27,8); //14,4
 814             facilitycode = bytebits_to_byte(dest+idx+18,8) ;
 815             number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
 816
 817             Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
 818             // if we're only looking for one tag
 819             if (findone){
 820                 if (ledcontrol) LED_A_OFF();
 821                 //LED_A_OFF();
 822                 return;
 823             }
 824             code=code2=0;
 825             version=facilitycode=0;
 826             number=0;
 827             idx=0;
 828         }
 829         WDT_HIT();
 830     }
 831     DbpString("Stopped");
 832     if (ledcontrol) LED_A_OFF();
 833 }
 834
 835 /*------------------------------
 836  * T5555/T5557/T5567 routines
 837  *------------------------------
 838  */
 839
 840 /* T55x7 configuration register definitions */
 841 #define T55x7_POR_DELAY                 0x00000001
 842 #define T55x7_ST_TERMINATOR             0x00000008
 843 #define T55x7_PWD                       0x00000010
 844 #define T55x7_MAXBLOCK_SHIFT            5
 845 #define T55x7_AOR                       0x00000200
 846 #define T55x7_PSKCF_RF_2                0
 847 #define T55x7_PSKCF_RF_4                0x00000400
 848 #define T55x7_PSKCF_RF_8                0x00000800
 849 #define T55x7_MODULATION_DIRECT         0
 850 #define T55x7_MODULATION_PSK1           0x00001000
 851 #define T55x7_MODULATION_PSK2           0x00002000
 852 #define T55x7_MODULATION_PSK3           0x00003000
 853 #define T55x7_MODULATION_FSK1           0x00004000
 854 #define T55x7_MODULATION_FSK2           0x00005000
 855 #define T55x7_MODULATION_FSK1a          0x00006000
 856 #define T55x7_MODULATION_FSK2a          0x00007000
 857 #define T55x7_MODULATION_MANCHESTER     0x00008000
 858 #define T55x7_MODULATION_BIPHASE        0x00010000
 859 #define T55x7_BITRATE_RF_8              0
 860 #define T55x7_BITRATE_RF_16             0x00040000
 861 #define T55x7_BITRATE_RF_32             0x00080000
 862 #define T55x7_BITRATE_RF_40             0x000C0000
 863 #define T55x7_BITRATE_RF_50             0x00100000
 864 #define T55x7_BITRATE_RF_64             0x00140000
 865 #define T55x7_BITRATE_RF_100            0x00180000
 866 #define T55x7_BITRATE_RF_128            0x001C0000
 867
 868 /* T5555 (Q5) configuration register definitions */
 869 #define T5555_ST_TERMINATOR             0x00000001
 870 #define T5555_MAXBLOCK_SHIFT            0x00000001
 871 #define T5555_MODULATION_MANCHESTER     0
 872 #define T5555_MODULATION_PSK1           0x00000010
 873 #define T5555_MODULATION_PSK2           0x00000020
 874 #define T5555_MODULATION_PSK3           0x00000030
 875 #define T5555_MODULATION_FSK1           0x00000040
 876 #define T5555_MODULATION_FSK2           0x00000050
 877 #define T5555_MODULATION_BIPHASE        0x00000060
 878 #define T5555_MODULATION_DIRECT         0x00000070
 879 #define T5555_INVERT_OUTPUT             0x00000080
 880 #define T5555_PSK_RF_2                  0
 881 #define T5555_PSK_RF_4                  0x00000100
 882 #define T5555_PSK_RF_8                  0x00000200
 883 #define T5555_USE_PWD                   0x00000400
 884 #define T5555_USE_AOR                   0x00000800
 885 #define T5555_BITRATE_SHIFT             12
 886 #define T5555_FAST_WRITE                0x00004000
 887 #define T5555_PAGE_SELECT               0x00008000
 888
 889 /*
 890  * Relevant times in microsecond
 891  * To compensate antenna falling times shorten the write times
 892  * and enlarge the gap ones.
 893  */
 894 #define START_GAP 250
 895 #define WRITE_GAP 160
 896 #define WRITE_0   144 // 192
 897 #define WRITE_1   400 // 432 for T55x7; 448 for E5550
 898
 899 // Write one bit to card
 900 void T55xxWriteBit(int bit)
 901 {
 902     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 903     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 904     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 905     if (bit == 0)
 906         SpinDelayUs(WRITE_0);
 907     else
 908         SpinDelayUs(WRITE_1);
 909     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 910     SpinDelayUs(WRITE_GAP);
 911 }
 912
 913 // Write one card block in page 0, no lock
 914 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 915 {
 916     //unsigned int i;  //enio adjustment 12/10/14
 917     uint32_t i;
 918
 919     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 920     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 921     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 922
 923     // Give it a bit of time for the resonant antenna to settle.
 924     // And for the tag to fully power up
 925     SpinDelay(150);
 926
 927     // Now start writting
 928     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 929     SpinDelayUs(START_GAP);
 930
 931     // Opcode
 932     T55xxWriteBit(1);
 933     T55xxWriteBit(0); //Page 0
 934     if (PwdMode == 1){
 935         // Pwd
 936         for (i = 0x80000000; i != 0; i >>= 1)
 937             T55xxWriteBit(Pwd & i);
 938     }
 939     // Lock bit
 940     T55xxWriteBit(0);
 941
 942     // Data
 943     for (i = 0x80000000; i != 0; i >>= 1)
 944         T55xxWriteBit(Data & i);
 945
 946     // Block
 947     for (i = 0x04; i != 0; i >>= 1)
 948         T55xxWriteBit(Block & i);
 949
 950     // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
 951     // so wait a little more)
 952     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 953     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 954     SpinDelay(20);
 955     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 956 }
 957
 958 // Read one card block in page 0
 959 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 960 {
 961     uint8_t *dest = BigBuf_get_addr();
 962     //int m=0, i=0; //enio adjustment 12/10/14
 963     uint32_t m=0, i=0;
 964     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 965     m = BigBuf_max_traceLen();
 966     // Clear destination buffer before sending the command
 967     memset(dest, 128, m);
 968     // Connect the A/D to the peak-detected low-frequency path.
 969     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 970     // Now set up the SSC to get the ADC samples that are now streaming at us.
 971     FpgaSetupSsc();
 972
 973     LED_D_ON();
 974     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 975     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 976
 977     // Give it a bit of time for the resonant antenna to settle.
 978     // And for the tag to fully power up
 979     SpinDelay(150);
 980
 981     // Now start writting
 982     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 983     SpinDelayUs(START_GAP);
 984
 985     // Opcode
 986     T55xxWriteBit(1);
 987     T55xxWriteBit(0); //Page 0
 988     if (PwdMode == 1){
 989         // Pwd
 990         for (i = 0x80000000; i != 0; i >>= 1)
 991             T55xxWriteBit(Pwd & i);
 992     }
 993     // Lock bit
 994     T55xxWriteBit(0);
 995     // Block
 996     for (i = 0x04; i != 0; i >>= 1)
 997         T55xxWriteBit(Block & i);
 998
 999     // Turn field on to read the response
1000     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1001     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1002
1003     // Now do the acquisition
1004     i = 0;
1005     for(;;) {
1006         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1007             AT91C_BASE_SSC->SSC_THR = 0x43;
1008         }
1009         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1010             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1011             // we don't care about actual value, only if it's more or less than a
1012             // threshold essentially we capture zero crossings for later analysis
1013             //                  if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1014             i++;
1015             if (i >= m) break;
1016         }
1017     }
1018
1019     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1020     LED_D_OFF();
1021     DbpString("DONE!");
1022 }
1023
1024 // Read card traceability data (page 1)
1025 void T55xxReadTrace(void){
1026     uint8_t *dest = BigBuf_get_addr();
1027     int m=0, i=0;
1028
1029     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1030     m = BigBuf_max_traceLen();
1031     // Clear destination buffer before sending the command
1032     memset(dest, 128, m);
1033     // Connect the A/D to the peak-detected low-frequency path.
1034     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1035     // Now set up the SSC to get the ADC samples that are now streaming at us.
1036     FpgaSetupSsc();
1037
1038     LED_D_ON();
1039     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1040     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1041
1042     // Give it a bit of time for the resonant antenna to settle.
1043     // And for the tag to fully power up
1044     SpinDelay(150);
1045
1046     // Now start writting
1047     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1048     SpinDelayUs(START_GAP);
1049
1050     // Opcode
1051     T55xxWriteBit(1);
1052     T55xxWriteBit(1); //Page 1
1053
1054     // Turn field on to read the response
1055     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1056     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1057
1058     // Now do the acquisition
1059     i = 0;
1060     for(;;) {
1061         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1062             AT91C_BASE_SSC->SSC_THR = 0x43;
1063         }
1064         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1065             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1066             i++;
1067             if (i >= m) break;
1068         }
1069     }
1070
1071     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1072     LED_D_OFF();
1073     DbpString("DONE!");
1074 }
1075
1076 /*-------------- Cloning routines -----------*/
1077 // Copy HID id to card and setup block 0 config
1078 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1079 {
1080     int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1081     int last_block = 0;
1082
1083     if (longFMT){
1084         // Ensure no more than 84 bits supplied
1085         if (hi2>0xFFFFF) {
1086             DbpString("Tags can only have 84 bits.");
1087             return;
1088         }
1089         // Build the 6 data blocks for supplied 84bit ID
1090         last_block = 6;
1091         data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1092         for (int i=0;i<4;i++) {
1093             if (hi2 & (1<<(19-i)))
1094                 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1095             else
1096                 data1 |= (1<<((3-i)*2)); // 0 -> 01
1097         }
1098
1099         data2 = 0;
1100         for (int i=0;i<16;i++) {
1101             if (hi2 & (1<<(15-i)))
1102                 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1103             else
1104                 data2 |= (1<<((15-i)*2)); // 0 -> 01
1105         }
1106
1107         data3 = 0;
1108         for (int i=0;i<16;i++) {
1109             if (hi & (1<<(31-i)))
1110                 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1111             else
1112                 data3 |= (1<<((15-i)*2)); // 0 -> 01
1113         }
1114
1115         data4 = 0;
1116         for (int i=0;i<16;i++) {
1117             if (hi & (1<<(15-i)))
1118                 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1119             else
1120                 data4 |= (1<<((15-i)*2)); // 0 -> 01
1121         }
1122
1123         data5 = 0;
1124         for (int i=0;i<16;i++) {
1125             if (lo & (1<<(31-i)))
1126                 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1127             else
1128                 data5 |= (1<<((15-i)*2)); // 0 -> 01
1129         }
1130
1131         data6 = 0;
1132         for (int i=0;i<16;i++) {
1133             if (lo & (1<<(15-i)))
1134                 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1135             else
1136                 data6 |= (1<<((15-i)*2)); // 0 -> 01
1137         }
1138     }
1139     else {
1140         // Ensure no more than 44 bits supplied
1141         if (hi>0xFFF) {
1142             DbpString("Tags can only have 44 bits.");
1143             return;
1144         }
1145
1146         // Build the 3 data blocks for supplied 44bit ID
1147         last_block = 3;
1148
1149         data1 = 0x1D000000; // load preamble
1150
1151         for (int i=0;i<12;i++) {
1152             if (hi & (1<<(11-i)))
1153                 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1154             else
1155                 data1 |= (1<<((11-i)*2)); // 0 -> 01
1156         }
1157
1158         data2 = 0;
1159         for (int i=0;i<16;i++) {
1160             if (lo & (1<<(31-i)))
1161                 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1162             else
1163                 data2 |= (1<<((15-i)*2)); // 0 -> 01
1164         }
1165
1166         data3 = 0;
1167         for (int i=0;i<16;i++) {
1168             if (lo & (1<<(15-i)))
1169                 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1170             else
1171                 data3 |= (1<<((15-i)*2)); // 0 -> 01
1172         }
1173     }
1174
1175     LED_D_ON();
1176     // Program the data blocks for supplied ID
1177     // and the block 0 for HID format
1178     T55xxWriteBlock(data1,1,0,0);
1179     T55xxWriteBlock(data2,2,0,0);
1180     T55xxWriteBlock(data3,3,0,0);
1181
1182     if (longFMT) { // if long format there are 6 blocks
1183         T55xxWriteBlock(data4,4,0,0);
1184         T55xxWriteBlock(data5,5,0,0);
1185         T55xxWriteBlock(data6,6,0,0);
1186     }
1187
1188     // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1189     T55xxWriteBlock(T55x7_BITRATE_RF_50    |
1190                     T55x7_MODULATION_FSK2a |
1191                     last_block << T55x7_MAXBLOCK_SHIFT,
1192                     0,0,0);
1193
1194     LED_D_OFF();
1195
1196     DbpString("DONE!");
1197 }
1198
1199 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1200 {
1201     int data1=0, data2=0; //up to six blocks for long format
1202
1203     data1 = hi;  // load preamble
1204     data2 = lo;
1205
1206     LED_D_ON();
1207     // Program the data blocks for supplied ID
1208     // and the block 0 for HID format
1209     T55xxWriteBlock(data1,1,0,0);
1210     T55xxWriteBlock(data2,2,0,0);
1211
1212     //Config Block
1213     T55xxWriteBlock(0x00147040,0,0,0);
1214     LED_D_OFF();
1215
1216     DbpString("DONE!");
1217 }
1218
1219 // Define 9bit header for EM410x tags
1220 #define EM410X_HEADER           0x1FF
1221 #define EM410X_ID_LENGTH        40
1222
1223 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1224 {
1225     int i, id_bit;
1226     uint64_t id = EM410X_HEADER;
1227     uint64_t rev_id = 0;        // reversed ID
1228     int c_parity[4];    // column parity
1229     int r_parity = 0;   // row parity
1230     uint32_t clock = 0;
1231
1232     // Reverse ID bits given as parameter (for simpler operations)
1233     for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1234         if (i < 32) {
1235             rev_id = (rev_id << 1) | (id_lo & 1);
1236             id_lo >>= 1;
1237         } else {
1238             rev_id = (rev_id << 1) | (id_hi & 1);
1239             id_hi >>= 1;
1240         }
1241     }
1242
1243     for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1244         id_bit = rev_id & 1;
1245
1246         if (i % 4 == 0) {
1247             // Don't write row parity bit at start of parsing
1248             if (i)
1249                 id = (id << 1) | r_parity;
1250             // Start counting parity for new row
1251             r_parity = id_bit;
1252         } else {
1253             // Count row parity
1254             r_parity ^= id_bit;
1255         }
1256
1257         // First elements in column?
1258         if (i < 4)
1259             // Fill out first elements
1260             c_parity[i] = id_bit;
1261         else
1262             // Count column parity
1263             c_parity[i % 4] ^= id_bit;
1264
1265         // Insert ID bit
1266         id = (id << 1) | id_bit;
1267         rev_id >>= 1;
1268     }
1269
1270     // Insert parity bit of last row
1271     id = (id << 1) | r_parity;
1272
1273     // Fill out column parity at the end of tag
1274     for (i = 0; i < 4; ++i)
1275         id = (id << 1) | c_parity[i];
1276
1277     // Add stop bit
1278     id <<= 1;
1279
1280     Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1281     LED_D_ON();
1282
1283     // Write EM410x ID
1284     T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1285     T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1286
1287     // Config for EM410x (RF/64, Manchester, Maxblock=2)
1288     if (card) {
1289         // Clock rate is stored in bits 8-15 of the card value
1290         clock = (card & 0xFF00) >> 8;
1291         Dbprintf("Clock rate: %d", clock);
1292         switch (clock)
1293         {
1294         case 32:
1295             clock = T55x7_BITRATE_RF_32;
1296             break;
1297         case 16:
1298             clock = T55x7_BITRATE_RF_16;
1299             break;
1300         case 0:
1301             // A value of 0 is assumed to be 64 for backwards-compatibility
1302             // Fall through...
1303         case 64:
1304             clock = T55x7_BITRATE_RF_64;
1305             break;
1306         default:
1307             Dbprintf("Invalid clock rate: %d", clock);
1308             return;
1309         }
1310
1311         // Writing configuration for T55x7 tag
1312         T55xxWriteBlock(clock       |
1313                         T55x7_MODULATION_MANCHESTER |
1314                         2 << T55x7_MAXBLOCK_SHIFT,
1315                         0, 0, 0);
1316     }
1317     else
1318         // Writing configuration for T5555(Q5) tag
1319         T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1320                         T5555_MODULATION_MANCHESTER   |
1321                         2 << T5555_MAXBLOCK_SHIFT,
1322                         0, 0, 0);
1323
1324     LED_D_OFF();
1325     Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1326              (uint32_t)(id >> 32), (uint32_t)id);
1327 }
1328
1329 // Clone Indala 64-bit tag by UID to T55x7
1330 void CopyIndala64toT55x7(int hi, int lo)
1331 {
1332
1333     //Program the 2 data blocks for supplied 64bit UID
1334     // and the block 0 for Indala64 format
1335     T55xxWriteBlock(hi,1,0,0);
1336     T55xxWriteBlock(lo,2,0,0);
1337     //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1338     T55xxWriteBlock(T55x7_BITRATE_RF_32    |
1339                     T55x7_MODULATION_PSK1 |
1340                     2 << T55x7_MAXBLOCK_SHIFT,
1341                     0, 0, 0);
1342     //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1343     //  T5567WriteBlock(0x603E1042,0);
1344
1345     DbpString("DONE!");
1346
1347 }
1348
1349 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1350 {
1351
1352     //Program the 7 data blocks for supplied 224bit UID
1353     // and the block 0 for Indala224 format
1354     T55xxWriteBlock(uid1,1,0,0);
1355     T55xxWriteBlock(uid2,2,0,0);
1356     T55xxWriteBlock(uid3,3,0,0);
1357     T55xxWriteBlock(uid4,4,0,0);
1358     T55xxWriteBlock(uid5,5,0,0);
1359     T55xxWriteBlock(uid6,6,0,0);
1360     T55xxWriteBlock(uid7,7,0,0);
1361     //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1362     T55xxWriteBlock(T55x7_BITRATE_RF_32    |
1363                     T55x7_MODULATION_PSK1 |
1364                     7 << T55x7_MAXBLOCK_SHIFT,
1365                     0,0,0);
1366     //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1367     //  T5567WriteBlock(0x603E10E2,0);
1368
1369     DbpString("DONE!");
1370
1371 }
1372
1373
1374 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1375 #define max(x,y) ( x<y ? y:x)
1376
1377 int DemodPCF7931(uint8_t **outBlocks) {
1378     uint8_t BitStream[256];
1379     uint8_t Blocks[8][16];
1380     uint8_t *GraphBuffer = BigBuf_get_addr();
1381     int GraphTraceLen = BigBuf_max_traceLen();
1382     int i, j, lastval, bitidx, half_switch;
1383     int clock = 64;
1384     int tolerance = clock / 8;
1385     int pmc, block_done;
1386     int lc, warnings = 0;
1387     int num_blocks = 0;
1388     int lmin=128, lmax=128;
1389     uint8_t dir;
1390
1391     AcquireRawAdcSamples125k(0);
1392
1393     lmin = 64;
1394     lmax = 192;
1395
1396     i = 2;
1397
1398     /* Find first local max/min */
1399     if(GraphBuffer[1] > GraphBuffer[0]) {
1400         while(i < GraphTraceLen) {
1401             if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1402                 break;
1403             i++;
1404         }
1405         dir = 0;
1406     }
1407     else {
1408         while(i < GraphTraceLen) {
1409             if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1410                 break;
1411             i++;
1412         }
1413         dir = 1;
1414     }
1415
1416     lastval = i++;
1417     half_switch = 0;
1418     pmc = 0;
1419     block_done = 0;
1420
1421     for (bitidx = 0; i < GraphTraceLen; i++)
1422     {
1423         if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1424         {
1425             lc = i - lastval;
1426             lastval = i;
1427
1428             // Switch depending on lc length:
1429             // Tolerance is 1/8 of clock rate (arbitrary)
1430             if (abs(lc-clock/4) < tolerance) {
1431                 // 16T0
1432                 if((i - pmc) == lc) { /* 16T0 was previous one */
1433                     /* It's a PMC ! */
1434                     i += (128+127+16+32+33+16)-1;
1435                     lastval = i;
1436                     pmc = 0;
1437                     block_done = 1;
1438                 }
1439                 else {
1440                     pmc = i;
1441                 }
1442             } else if (abs(lc-clock/2) < tolerance) {
1443                 // 32TO
1444                 if((i - pmc) == lc) { /* 16T0 was previous one */
1445                     /* It's a PMC ! */
1446                     i += (128+127+16+32+33)-1;
1447                     lastval = i;
1448                     pmc = 0;
1449                     block_done = 1;
1450                 }
1451                 else if(half_switch == 1) {
1452                     BitStream[bitidx++] = 0;
1453                     half_switch = 0;
1454                 }
1455                 else
1456                     half_switch++;
1457             } else if (abs(lc-clock) < tolerance) {
1458                 // 64TO
1459                 BitStream[bitidx++] = 1;
1460             } else {
1461                 // Error
1462                 warnings++;
1463                 if (warnings > 10)
1464                 {
1465                     Dbprintf("Error: too many detection errors, aborting.");
1466                     return 0;
1467                 }
1468             }
1469
1470             if(block_done == 1) {
1471                 if(bitidx == 128) {
1472                     for(j=0; j<16; j++) {
1473                         Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1474                                 64*BitStream[j*8+6]+
1475                                 32*BitStream[j*8+5]+
1476                                 16*BitStream[j*8+4]+
1477                                 8*BitStream[j*8+3]+
1478                                 4*BitStream[j*8+2]+
1479                                 2*BitStream[j*8+1]+
1480                                 BitStream[j*8];
1481                     }
1482                     num_blocks++;
1483                 }
1484                 bitidx = 0;
1485                 block_done = 0;
1486                 half_switch = 0;
1487             }
1488             if(i < GraphTraceLen)
1489             {
1490                 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1491                 else dir = 1;
1492             }
1493         }
1494         if(bitidx==255)
1495             bitidx=0;
1496         warnings = 0;
1497         if(num_blocks == 4) break;
1498     }
1499     memcpy(outBlocks, Blocks, 16*num_blocks);
1500     return num_blocks;
1501 }
1502
1503 int IsBlock0PCF7931(uint8_t *Block) {
1504     // Assume RFU means 0 :)
1505     if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1506         return 1;
1507     if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1508         return 1;
1509     return 0;
1510 }
1511
1512 int IsBlock1PCF7931(uint8_t *Block) {
1513     // Assume RFU means 0 :)
1514     if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1515         if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1516             return 1;
1517
1518     return 0;
1519 }
1520
1521 #define ALLOC 16
1522
1523 void ReadPCF7931() {
1524     uint8_t Blocks[8][17];
1525     uint8_t tmpBlocks[4][16];
1526     int i, j, ind, ind2, n;
1527     int num_blocks = 0;
1528     int max_blocks = 8;
1529     int ident = 0;
1530     int error = 0;
1531     int tries = 0;
1532
1533     memset(Blocks, 0, 8*17*sizeof(uint8_t));
1534
1535     do {
1536         memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1537         n = DemodPCF7931((uint8_t**)tmpBlocks);
1538         if(!n)
1539             error++;
1540         if(error==10 && num_blocks == 0) {
1541             Dbprintf("Error, no tag or bad tag");
1542             return;
1543         }
1544         else if (tries==20 || error==10) {
1545             Dbprintf("Error reading the tag");
1546             Dbprintf("Here is the partial content");
1547             goto end;
1548         }
1549
1550         for(i=0; i<n; i++)
1551             Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1552                      tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1553                     tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1554         if(!ident) {
1555             for(i=0; i<n; i++) {
1556                 if(IsBlock0PCF7931(tmpBlocks[i])) {
1557                     // Found block 0 ?
1558                     if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1559                         // Found block 1!
1560                         // \o/
1561                         ident = 1;
1562                         memcpy(Blocks[0], tmpBlocks[i], 16);
1563                         Blocks[0][ALLOC] = 1;
1564                         memcpy(Blocks[1], tmpBlocks[i+1], 16);
1565                         Blocks[1][ALLOC] = 1;
1566                         max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1567                         // Debug print
1568                         Dbprintf("(dbg) Max blocks: %d", max_blocks);
1569                         num_blocks = 2;
1570                         // Handle following blocks
1571                         for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1572                             if(j==n) j=0;
1573                             if(j==i) break;
1574                             memcpy(Blocks[ind2], tmpBlocks[j], 16);
1575                             Blocks[ind2][ALLOC] = 1;
1576                         }
1577                         break;
1578                     }
1579                 }
1580             }
1581         }
1582         else {
1583             for(i=0; i<n; i++) { // Look for identical block in known blocks
1584                 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1585                     for(j=0; j<max_blocks; j++) {
1586                         if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1587                             // Found an identical block
1588                             for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1589                                 if(ind2 < 0)
1590                                     ind2 = max_blocks;
1591                                 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1592                                     // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1593                                     memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1594                                     Blocks[ind2][ALLOC] = 1;
1595                                     num_blocks++;
1596                                     if(num_blocks == max_blocks) goto end;
1597                                 }
1598                             }
1599                             for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1600                                 if(ind2 > max_blocks)
1601                                     ind2 = 0;
1602                                 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1603                                     // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1604                                     memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1605                                     Blocks[ind2][ALLOC] = 1;
1606                                     num_blocks++;
1607                                     if(num_blocks == max_blocks) goto end;
1608                                 }
1609                             }
1610                         }
1611                     }
1612                 }
1613             }
1614         }
1615         tries++;
1616         if (BUTTON_PRESS()) return;
1617     } while (num_blocks != max_blocks);
1618 end:
1619     Dbprintf("-----------------------------------------");
1620     Dbprintf("Memory content:");
1621     Dbprintf("-----------------------------------------");
1622     for(i=0; i<max_blocks; i++) {
1623         if(Blocks[i][ALLOC]==1)
1624             Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1625                      Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1626                     Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1627         else
1628             Dbprintf("<missing block %d>", i);
1629     }
1630     Dbprintf("-----------------------------------------");
1631
1632     return ;
1633 }
1634
1635
1636 //-----------------------------------
1637 // EM4469 / EM4305 routines
1638 //-----------------------------------
1639 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1640 #define FWD_CMD_WRITE 0xA
1641 #define FWD_CMD_READ 0x9
1642 #define FWD_CMD_DISABLE 0x5
1643
1644
1645 uint8_t forwardLink_data[64]; //array of forwarded bits
1646 uint8_t * forward_ptr; //ptr for forward message preparation
1647 uint8_t fwd_bit_sz; //forwardlink bit counter
1648 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1649
1650 //====================================================================
1651 // prepares command bits
1652 // see EM4469 spec
1653 //====================================================================
1654 //--------------------------------------------------------------------
1655 uint8_t Prepare_Cmd( uint8_t cmd ) {
1656     //--------------------------------------------------------------------
1657
1658     *forward_ptr++ = 0; //start bit
1659     *forward_ptr++ = 0; //second pause for 4050 code
1660
1661     *forward_ptr++ = cmd;
1662     cmd >>= 1;
1663     *forward_ptr++ = cmd;
1664     cmd >>= 1;
1665     *forward_ptr++ = cmd;
1666     cmd >>= 1;
1667     *forward_ptr++ = cmd;
1668
1669     return 6; //return number of emited bits
1670 }
1671
1672 //====================================================================
1673 // prepares address bits
1674 // see EM4469 spec
1675 //====================================================================
1676
1677 //--------------------------------------------------------------------
1678 uint8_t Prepare_Addr( uint8_t addr ) {
1679     //--------------------------------------------------------------------
1680
1681     register uint8_t line_parity;
1682
1683     uint8_t i;
1684     line_parity = 0;
1685     for(i=0;i<6;i++) {
1686         *forward_ptr++ = addr;
1687         line_parity ^= addr;
1688         addr >>= 1;
1689     }
1690
1691     *forward_ptr++ = (line_parity & 1);
1692
1693     return 7; //return number of emited bits
1694 }
1695
1696 //====================================================================
1697 // prepares data bits intreleaved with parity bits
1698 // see EM4469 spec
1699 //====================================================================
1700
1701 //--------------------------------------------------------------------
1702 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1703     //--------------------------------------------------------------------
1704
1705     register uint8_t line_parity;
1706     register uint8_t column_parity;
1707     register uint8_t i, j;
1708     register uint16_t data;
1709
1710     data = data_low;
1711     column_parity = 0;
1712
1713     for(i=0; i<4; i++) {
1714         line_parity = 0;
1715         for(j=0; j<8; j++) {
1716             line_parity ^= data;
1717             column_parity ^= (data & 1) << j;
1718             *forward_ptr++ = data;
1719             data >>= 1;
1720         }
1721         *forward_ptr++ = line_parity;
1722         if(i == 1)
1723             data = data_hi;
1724     }
1725
1726     for(j=0; j<8; j++) {
1727         *forward_ptr++ = column_parity;
1728         column_parity >>= 1;
1729     }
1730     *forward_ptr = 0;
1731
1732     return 45; //return number of emited bits
1733 }
1734
1735 //====================================================================
1736 // Forward Link send function
1737 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1738 // fwd_bit_count set with number of bits to be sent
1739 //====================================================================
1740 void SendForward(uint8_t fwd_bit_count) {
1741
1742     fwd_write_ptr = forwardLink_data;
1743     fwd_bit_sz = fwd_bit_count;
1744
1745     LED_D_ON();
1746
1747     //Field on
1748     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1749     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1750     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1751
1752     // Give it a bit of time for the resonant antenna to settle.
1753     // And for the tag to fully power up
1754     SpinDelay(150);
1755
1756     // force 1st mod pulse (start gap must be longer for 4305)
1757     fwd_bit_sz--; //prepare next bit modulation
1758     fwd_write_ptr++;
1759     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1760     SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1761     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1762     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1763     SpinDelayUs(16*8); //16 cycles on (8us each)
1764
1765     // now start writting
1766     while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1767         if(((*fwd_write_ptr++) & 1) == 1)
1768             SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1769         else {
1770             //These timings work for 4469/4269/4305 (with the 55*8 above)
1771             FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1772             SpinDelayUs(23*8); //16-4 cycles off (8us each)
1773             FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1774             FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1775             SpinDelayUs(9*8); //16 cycles on (8us each)
1776         }
1777     }
1778 }
1779
1780 void EM4xLogin(uint32_t Password) {
1781
1782     uint8_t fwd_bit_count;
1783
1784     forward_ptr = forwardLink_data;
1785     fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1786     fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1787
1788     SendForward(fwd_bit_count);
1789
1790     //Wait for command to complete
1791     SpinDelay(20);
1792
1793 }
1794
1795 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1796
1797     uint8_t fwd_bit_count;
1798     uint8_t *dest = BigBuf_get_addr();
1799     int m=0, i=0;
1800
1801     //If password mode do login
1802     if (PwdMode == 1) EM4xLogin(Pwd);
1803
1804     forward_ptr = forwardLink_data;
1805     fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1806     fwd_bit_count += Prepare_Addr( Address );
1807
1808     m = BigBuf_max_traceLen();
1809     // Clear destination buffer before sending the command
1810     memset(dest, 128, m);
1811     // Connect the A/D to the peak-detected low-frequency path.
1812     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1813     // Now set up the SSC to get the ADC samples that are now streaming at us.
1814     FpgaSetupSsc();
1815
1816     SendForward(fwd_bit_count);
1817
1818     // Now do the acquisition
1819     i = 0;
1820     for(;;) {
1821         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1822             AT91C_BASE_SSC->SSC_THR = 0x43;
1823         }
1824         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1825             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1826             i++;
1827             if (i >= m) break;
1828         }
1829     }
1830     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1831     LED_D_OFF();
1832 }
1833
1834 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1835
1836     uint8_t fwd_bit_count;
1837
1838     //If password mode do login
1839     if (PwdMode == 1) EM4xLogin(Pwd);
1840
1841     forward_ptr = forwardLink_data;
1842     fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1843     fwd_bit_count += Prepare_Addr( Address );
1844     fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1845
1846     SendForward(fwd_bit_count);
1847
1848     //Wait for write to complete
1849     SpinDelay(20);
1850     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1851     LED_D_OFF();
1852 }