]> cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/lo_passthru.v
added dissector for ISO 14443-A ATS response
[proxmark3-svn] / fpga / lo_passthru.v
1 //-----------------------------------------------------------------------------
2 // For reading TI tags, we need to place the FPGA in pass through mode
3 // and pass everything through to the ARM
4 //-----------------------------------------------------------------------------
5
6 module lo_passthru(
7 pck0, ck_1356meg, ck_1356megb,
8 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
9 adc_d, adc_clk,
10 ssp_frame, ssp_din, ssp_dout, ssp_clk,
11 cross_hi, cross_lo,
12 dbg, divisor
13 );
14 input pck0, ck_1356meg, ck_1356megb;
15 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
16 input [7:0] adc_d;
17 output adc_clk;
18 input ssp_dout;
19 output ssp_frame, ssp_din, ssp_clk;
20 input cross_hi, cross_lo;
21 output dbg;
22 input [7:0] divisor;
23
24 reg [7:0] pck_divider;
25 reg ant_lo;
26
27 // this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
28 // which is high for (divisor+1) pck0 cycles and low for the same duration
29 // ant_lo is therefore a 50% duty cycle clock signal with a frequency of
30 // 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
31 always @(posedge pck0)
32 begin
33 if(pck_divider == divisor[7:0])
34 begin
35 pck_divider <= 8'd0;
36 ant_lo = !ant_lo;
37 end
38 else
39 begin
40 pck_divider <= pck_divider + 1;
41 end
42 end
43
44 // the antenna is modulated when ssp_dout = 1, when 0 the
45 // antenna drivers stop modulating and go into listen mode
46 assign pwr_oe3 = 1'b0;
47 assign pwr_oe1 = ssp_dout;
48 assign pwr_oe2 = ssp_dout;
49 assign pwr_oe4 = ssp_dout;
50 assign pwr_lo = ant_lo && ssp_dout;
51 assign pwr_hi = 1'b0;
52 assign adc_clk = 1'b0;
53 assign ssp_din = cross_lo;
54 assign dbg = cross_lo;
55
56 endmodule
Impressum, Datenschutz