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CHG: Minor tweaks, the tracing dissappeared, the spindelay for powering up too...
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // LEGIC RF simulation code
9 //-----------------------------------------------------------------------------
10 #include "legicrf.h"
11
12 static struct legic_frame {
13 int bits;
14 uint32_t data;
15 } current_frame;
16
17 static enum {
18 STATE_DISCON,
19 STATE_IV,
20 STATE_CON,
21 } legic_state;
22
23 static crc_t legic_crc;
24 static int legic_read_count;
25 static uint32_t legic_prng_bc;
26 static uint32_t legic_prng_iv;
27
28 static int legic_phase_drift;
29 static int legic_frame_drift;
30 static int legic_reqresp_drift;
31
32 AT91PS_TC timer;
33 AT91PS_TC prng_timer;
34
35 /*
36 static void setup_timer(void) {
37 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
38 // this it won't be terribly accurate but should be good enough.
39 //
40 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
41 timer = AT91C_BASE_TC1;
42 timer->TC_CCR = AT91C_TC_CLKDIS;
43 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
44 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
45
46 //
47 // Set up Timer 2 to use for measuring time between frames in
48 // tag simulation mode. Runs 4x faster as Timer 1
49 //
50 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
51 prng_timer = AT91C_BASE_TC2;
52 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
53 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
54 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
55 }
56
57 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
58 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
59
60 // fast clock
61 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
62 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
63 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
64 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
65 AT91C_BASE_TC0->TC_RA = 1;
66 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
67
68 */
69
70 // At TIMER_CLOCK3 (MCK/32)
71 // testing calculating in (us) microseconds.
72 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
73 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
74 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
75 #define TAG_BIT_PERIOD 150 // 100us == 100 * 1.5 == 150ticks
76 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
77
78 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
79
80 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
81 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
82
83 #define OFFSET_LOG 1024
84
85 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
86
87 #ifndef SHORT_COIL
88 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
89 #endif
90 #ifndef OPEN_COIL
91 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
92 #endif
93
94 uint32_t sendFrameStop = 0;
95
96 // Pause pulse, off in 20us / 30ticks,
97 // ONE / ZERO bit pulse,
98 // one == 80us / 120ticks
99 // zero == 40us / 60ticks
100 #ifndef COIL_PULSE
101 # define COIL_PULSE(x) \
102 do { \
103 SHORT_COIL; \
104 WaitTicks( (RWD_TIME_PAUSE) ); \
105 OPEN_COIL; \
106 WaitTicks((x)); \
107 } while (0)
108 #endif
109
110 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
111 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
112 #define LEGIC_CARD_MEMSIZE 1024
113 static uint8_t* cardmem;
114
115 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
116 // Overflow, won't happen
117 if (f->bits >= 31) return;
118
119 f->data |= (bit << f->bits);
120 f->bits++;
121 }
122
123 static void frame_clean(struct legic_frame * const f) {
124 f->data = 0;
125 f->bits = 0;
126 }
127
128 // Prng works when waiting in 99.1us cycles.
129 // and while sending/receiving in bit frames (100, 60)
130 /*static void CalibratePrng( uint32_t time){
131 // Calculate Cycles based on timer 100us
132 uint32_t i = (time - sendFrameStop) / 100 ;
133
134 // substract cycles of finished frames
135 int k = i - legic_prng_count()+1;
136
137 // substract current frame length, rewind to beginning
138 if ( k > 0 )
139 legic_prng_forward(k);
140 }
141 */
142
143 /* Generate Keystream */
144 uint32_t get_key_stream(int skip, int count) {
145 uint32_t key = 0;
146 int i;
147
148 // Use int to enlarge timer tc to 32bit
149 legic_prng_bc += prng_timer->TC_CV;
150
151 // reset the prng timer.
152 ResetTimer(prng_timer);
153
154 /* If skip == -1, forward prng time based */
155 if(skip == -1) {
156 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
157 i -= legic_prng_count(); /* substract cycles of finished frames */
158 i -= count; /* substract current frame length, rewind to beginning */
159 legic_prng_forward(i);
160 } else {
161 legic_prng_forward(skip);
162 }
163
164 i = (count == 6) ? -1 : legic_read_count;
165
166 /* Write Time Data into LOG */
167 // uint8_t *BigBuf = BigBuf_get_addr();
168 // BigBuf[OFFSET_LOG+128+i] = legic_prng_count();
169 // BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;
170 // BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;
171 // BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;
172 // BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;
173 // BigBuf[OFFSET_LOG+384+i] = count;
174
175 /* Generate KeyStream */
176 for(i=0; i<count; i++) {
177 key |= legic_prng_get_bit() << i;
178 legic_prng_forward(1);
179 }
180 return key;
181 }
182
183 /* Send a frame in tag mode, the FPGA must have been set up by
184 * LegicRfSimulate
185 */
186 void frame_send_tag(uint16_t response, uint8_t bits, uint8_t crypt) {
187 /* Bitbang the response */
188 LOW(GPIO_SSC_DOUT);
189 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
190 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
191
192 /* Use time to crypt frame */
193 if(crypt) {
194 legic_prng_forward(2); /* TAG_FRAME_WAIT -> shift by 2 */
195 response ^= legic_prng_get_bits(bits);
196 }
197
198 /* Wait for the frame start */
199 WaitUS( TAG_FRAME_WAIT );
200
201 uint8_t bit = 0;
202 for(int i = 0; i < bits; i++) {
203
204 bit = response & 1;
205 response >>= 1;
206
207 if (bit)
208 HIGH(GPIO_SSC_DOUT);
209 else
210 LOW(GPIO_SSC_DOUT);
211
212 WaitUS(100);
213 }
214 LOW(GPIO_SSC_DOUT);
215 }
216
217 /* Send a frame in reader mode, the FPGA must have been set up by
218 * LegicRfReader
219 */
220 void frame_sendAsReader(uint32_t data, uint8_t bits){
221
222 uint32_t starttime = GET_TICKS, send = 0;
223 uint16_t mask = 1;
224 uint8_t prngstart = legic_prng_count() ;
225
226 // xor lsfr onto data.
227 send = data ^ legic_prng_get_bits(bits);
228
229 for (; mask < BITMASK(bits); mask <<= 1) {
230 if (send & mask) {
231 COIL_PULSE(RWD_TIME_1);
232 } else {
233 COIL_PULSE(RWD_TIME_0);
234 }
235 }
236
237 // Final pause to mark the end of the frame
238 COIL_PULSE(0);
239
240 sendFrameStop = GET_TICKS;
241 uint8_t cmdbytes[] = {
242 bits,
243 BYTEx(data, 0),
244 BYTEx(data, 1),
245 BYTEx(send, 0),
246 BYTEx(send, 1),
247 prngstart,
248 legic_prng_count()
249 };
250 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, sendFrameStop, NULL, TRUE);
251 }
252
253 /* Receive a frame from the card in reader emulation mode, the FPGA and
254 * timer must have been set up by LegicRfReader and frame_sendAsReader.
255 *
256 * The LEGIC RF protocol from card to reader does not include explicit
257 * frame start/stop information or length information. The reader must
258 * know beforehand how many bits it wants to receive. (Notably: a card
259 * sending a stream of 0-bits is indistinguishable from no card present.)
260 *
261 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
262 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
263 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
264 * for edges. Count the edges in each bit interval. If they are approximately
265 * 0 this was a 0-bit, if they are approximately equal to the number of edges
266 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
267 * timer that's still running from frame_sendAsReader in order to get a synchronization
268 * with the frame that we just sent.
269 *
270 * FIXME: Because we're relying on the hysteresis to just do the right thing
271 * the range is severely reduced (and you'll probably also need a good antenna).
272 * So this should be fixed some time in the future for a proper receiver.
273 */
274 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
275
276 frame_clean(f);
277 if ( bits > 32 ) return;
278
279 uint8_t i = bits, edges = 0;
280 uint16_t lsfr = 0;
281 uint32_t the_bit = 1, next_bit_at = 0, data;
282
283 int old_level = 0, level = 0;
284
285 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
286 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
287
288 // calibrate the prng.
289 legic_prng_forward(2);
290
291 // precompute the cipher
292 uint8_t prngstart = legic_prng_count() ;
293
294 data = lsfr = legic_prng_get_bits(bits);
295
296 //FIXED time between sending frame and now listening frame. 330us
297 // 387 = 0x19 0001 1001
298 // 480 = 0x19
299 // 500 = 0x1C 0001 1100
300 uint32_t starttime = GET_TICKS;
301 //uint16_t mywait = TAG_FRAME_WAIT - (starttime - sendFrameStop);
302 //uint16_t mywait = 495 - (starttime - sendFrameStop);
303 if ( bits == 6) {
304 //Dbprintf("6 WAIT %d", 495 - 9 - 9 );
305 WaitTicks( 495 - 9 - 9 );
306 } else {
307 //Dbprintf("x WAIT %d", mywait );
308 //WaitTicks( mywait );
309 WaitTicks( 450 );
310 }
311
312 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
313
314 while ( i-- ){
315 edges = 0;
316 uint8_t adjust = 0;
317 while ( GET_TICKS < next_bit_at) {
318
319 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
320
321 if (level != old_level)
322 ++edges;
323
324 old_level = level;
325
326 if(edges > 20 && adjust == 0) {
327 next_bit_at -= 15;
328 adjust = 1;
329 }
330 }
331
332 next_bit_at += TAG_BIT_PERIOD;
333
334 // We expect 42 edges == ONE
335 //if (edges > 20 && edges < 64)
336 if ( edges > 20 )
337 data ^= the_bit;
338
339 the_bit <<= 1;
340 }
341
342 // output
343 f->data = data;
344 f->bits = bits;
345
346 uint8_t cmdbytes[] = {
347 bits,
348 BYTEx(data,0),
349 BYTEx(data,1),
350 BYTEx(data, 0) ^ BYTEx(lsfr,0),
351 BYTEx(data, 1) ^ BYTEx(lsfr,1),
352 prngstart,
353 legic_prng_count()
354 };
355 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
356 }
357
358 // Setup pm3 as a Legic Reader
359 static uint32_t setup_phase_reader(uint8_t iv) {
360
361 // Switch on carrier and let the tag charge for 1ms
362 HIGH(GPIO_SSC_DOUT);
363 WaitUS(100);
364
365 ResetTicks();
366
367 // no keystream yet
368 legic_prng_init(0);
369
370 // send IV handshake
371 frame_sendAsReader(iv, 7);
372
373 // Now both tag and reader has same IV. Prng can start.
374 legic_prng_init(iv);
375
376 frame_receiveAsReader(&current_frame, 6);
377
378 // fixed delay before sending ack.
379 WaitTicks(366); // 244us
380 legic_prng_forward(1); //240us / 100 == 2.4 iterations
381
382 // Send obsfuscated acknowledgment frame.
383 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
384 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
385 switch ( current_frame.data ) {
386 case 0x0D: frame_sendAsReader(0x19, 6); break;
387 case 0x1D:
388 case 0x3D: frame_sendAsReader(0x39, 6); break;
389 default: break;
390 }
391 return current_frame.data;
392 }
393
394 static void LegicCommonInit(void) {
395
396 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
397 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
398 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
399
400 /* Bitbang the transmitter */
401 LOW(GPIO_SSC_DOUT);
402 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
403 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
404
405 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
406 cardmem = BigBuf_malloc(LEGIC_CARD_MEMSIZE);
407 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
408
409 clear_trace();
410 set_tracing(TRUE);
411 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
412
413 StartTicks();
414 }
415
416 // Switch off carrier, make sure tag is reset
417 static void switch_off_tag_rwd(void) {
418 LOW(GPIO_SSC_DOUT);
419 WaitUS(20);
420 WDT_HIT();
421 }
422
423 // calculate crc4 for a legic READ command
424 // 5,8,10 address size.
425 static uint32_t legic4Crc(uint8_t legicCmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
426 crc_clear(&legic_crc);
427 //uint32_t temp = (value << cmd_sz) | (byte_index << 1) | legicCmd;
428 //crc_update(&legic_crc, temp, cmd_sz + 8 );
429 crc_update(&legic_crc, 1, 1); /* CMD_READ */
430 crc_update(&legic_crc, byte_index, cmd_sz-1);
431 crc_update(&legic_crc, value, 8);
432 return crc_finish(&legic_crc);
433 }
434
435 int legic_read_byte(int byte_index, int cmd_sz) {
436
437 uint8_t byte = 0, crc = 0, calcCrc = 0;
438 uint32_t cmd = (byte_index << 1) | LEGIC_READ;
439
440 // (us)| ticks
441 // -------------
442 // 330 | 495
443 // 460 | 690
444 // 258 | 387
445 // 244 | 366
446 WaitTicks(495);
447 legic_prng_forward(3); // 460 / 100 = 4.6 iterations
448
449 frame_sendAsReader(cmd, cmd_sz);
450 frame_receiveAsReader(&current_frame, 12);
451
452 byte = BYTEx(current_frame.data, 0);
453 calcCrc = legic4Crc(LEGIC_READ, byte_index, byte, cmd_sz);
454 crc = BYTEx(current_frame.data, 1);
455
456 if( calcCrc != crc ) {
457 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc);
458 return -1;
459 }
460 return byte;
461 }
462
463 /*
464 * - assemble a write_cmd_frame with crc and send it
465 * - wait until the tag sends back an ACK ('1' bit unencrypted)
466 * - forward the prng based on the timing
467 */
468 //int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) {
469 int legic_write_byte(uint8_t byte, uint16_t addr, uint8_t addr_sz) {
470
471 //do not write UID, CRC at offset 0-4.
472 if (addr <= 4) return 0;
473
474 // crc
475 crc_clear(&legic_crc);
476 crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
477 crc_update(&legic_crc, addr, addr_sz);
478 crc_update(&legic_crc, byte, 8);
479 uint32_t crc = crc_finish(&legic_crc);
480
481 uint32_t crc2 = legic4Crc(LEGIC_WRITE, addr, byte, addr_sz+1);
482 if ( crc != crc2 )
483 Dbprintf("crc is missmatch");
484
485 // send write command
486 uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
487 |(byte <<(addr_sz+1)) //Data
488 |(addr <<1) //Address
489 | LEGIC_WRITE); //CMD = Write
490
491 uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
492
493 legic_prng_forward(2); /* we wait anyways */
494
495 WaitUS(TAG_FRAME_WAIT);
496
497 frame_sendAsReader(cmd, cmd_sz);
498
499 // wllm-rbnt doesnt have these
500 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
501 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
502
503 // wait for ack
504 int t, old_level = 0, edges = 0;
505 int next_bit_at = 0;
506
507 WaitUS(TAG_FRAME_WAIT);
508
509 for( t = 0; t < 80; ++t) {
510 edges = 0;
511 next_bit_at += TAG_BIT_PERIOD;
512 while(timer->TC_CV < next_bit_at) {
513 int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
514 if(level != old_level)
515 edges++;
516
517 old_level = level;
518 }
519 if(edges > 20 && edges < 60) { /* expected are 42 edges */
520 int t = timer->TC_CV;
521 int c = t / TAG_BIT_PERIOD;
522
523 ResetTimer(timer);
524 legic_prng_forward(c);
525 return 0;
526 }
527 }
528
529 ResetTimer(timer);
530 return -1;
531 }
532
533 int LegicRfReader(int offset, int bytes, int iv) {
534
535 uint16_t byte_index = 0;
536 uint8_t cmd_sz = 0, isOK = 1;
537 int card_sz = 0;
538
539 LegicCommonInit();
540
541 uint32_t tag_type = setup_phase_reader(iv);
542
543 switch_off_tag_rwd();
544
545 switch(tag_type) {
546 case 0x0d:
547 if ( MF_DBGLEVEL >= 2) DbpString("MIM22 card found, reading card");
548 cmd_sz = 6;
549 card_sz = 22;
550 break;
551 case 0x1d:
552 if ( MF_DBGLEVEL >= 2) DbpString("MIM256 card found, reading card");
553 cmd_sz = 9;
554 card_sz = 256;
555 break;
556 case 0x3d:
557 if ( MF_DBGLEVEL >= 2) DbpString("MIM1024 card found, reading card");
558 cmd_sz = 11;
559 card_sz = 1024;
560 break;
561 default:
562 if ( MF_DBGLEVEL >= 1) Dbprintf("Unknown card format: %x", tag_type);
563 isOK = 0;
564 goto OUT;
565 break;
566 }
567 if (bytes == -1)
568 bytes = card_sz;
569
570 if (bytes + offset >= card_sz)
571 bytes = card_sz - offset;
572
573 // Start setup and read bytes.
574 setup_phase_reader(iv);
575
576 LED_B_ON();
577 while (byte_index < bytes) {
578 int r = legic_read_byte(byte_index + offset, cmd_sz);
579
580 if (r == -1 || BUTTON_PRESS()) {
581 if ( MF_DBGLEVEL >= 3) DbpString("operation aborted");
582 isOK = 0;
583 goto OUT;
584 }
585 cardmem[++byte_index] = r;
586 WDT_HIT();
587 }
588
589 OUT:
590 WDT_HIT();
591 switch_off_tag_rwd();
592 LEDsoff();
593 uint8_t len = (bytes & 0x3FF);
594 cmd_send(CMD_ACK,isOK,len,0,cardmem,len);
595 return 0;
596 }
597
598 /*int _LegicRfWriter(int offset, int bytes, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) {
599 int byte_index=0;
600
601 LED_B_ON();
602 setup_phase_reader(iv);
603 //legic_prng_forward(2);
604 while(byte_index < bytes) {
605 int r;
606
607 //check if the DCF should be changed
608 if ( (offset == 0x05) && (bytes == 0x02) ) {
609 //write DCF in reverse order (addr 0x06 before 0x05)
610 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
611 //legic_prng_forward(1);
612 if(r == 0) {
613 byte_index++;
614 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
615 }
616 //legic_prng_forward(1);
617 }
618 else {
619 r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue);
620 }
621 if((r != 0) || BUTTON_PRESS()) {
622 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
623 switch_off_tag_rwd();
624 LED_B_OFF();
625 LED_C_OFF();
626 return -1;
627 }
628
629 WDT_HIT();
630 byte_index++;
631 if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
632 }
633 LED_B_OFF();
634 LED_C_OFF();
635 DbpString("write successful");
636 return 0;
637 }*/
638
639 void LegicRfWriter(int offset, int bytes, int iv) {
640
641 int byte_index = 0, addr_sz = 0;
642
643 LegicCommonInit();
644
645 if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
646
647 uint32_t tag_type = setup_phase_reader(iv);
648
649 switch_off_tag_rwd();
650
651 switch(tag_type) {
652 case 0x0d:
653 if(offset+bytes > 22) {
654 Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset + bytes);
655 return;
656 }
657 addr_sz = 5;
658 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
659 break;
660 case 0x1d:
661 if(offset+bytes > 0x100) {
662 Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset + bytes);
663 return;
664 }
665 addr_sz = 8;
666 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
667 break;
668 case 0x3d:
669 if(offset+bytes > 0x400) {
670 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset + bytes);
671 return;
672 }
673 addr_sz = 10;
674 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset + bytes);
675 break;
676 default:
677 Dbprintf("No or unknown card found, aborting");
678 return;
679 }
680
681 LED_B_ON();
682 setup_phase_reader(iv);
683 int r = 0;
684 while(byte_index < bytes) {
685
686 //check if the DCF should be changed
687 if ( ((byte_index+offset) == 0x05) && (bytes >= 0x02) ) {
688 //write DCF in reverse order (addr 0x06 before 0x05)
689 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), addr_sz);
690
691 // write second byte on success...
692 if(r == 0) {
693 byte_index++;
694 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), addr_sz);
695 }
696 }
697 else {
698 r = legic_write_byte(cardmem[byte_index+offset], byte_index+offset, addr_sz);
699 }
700
701 if ((r != 0) || BUTTON_PRESS()) {
702 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
703 switch_off_tag_rwd();
704 LEDsoff();
705 return;
706 }
707
708 WDT_HIT();
709 byte_index++;
710 }
711 LEDsoff();
712 if ( MF_DBGLEVEL >= 1) DbpString("write successful");
713 }
714
715 void LegicRfRawWriter(int address, int byte, int iv) {
716
717 int byte_index = 0, addr_sz = 0;
718
719 LegicCommonInit();
720
721 if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
722
723 uint32_t tag_type = setup_phase_reader(iv);
724
725 switch_off_tag_rwd();
726
727 switch(tag_type) {
728 case 0x0d:
729 if(address > 22) {
730 Dbprintf("Error: can not write to 0x%03.3x on MIM22", address);
731 return;
732 }
733 addr_sz = 5;
734 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
735 break;
736 case 0x1d:
737 if(address > 0x100) {
738 Dbprintf("Error: can not write to 0x%03.3x on MIM256", address);
739 return;
740 }
741 addr_sz = 8;
742 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
743 break;
744 case 0x3d:
745 if(address > 0x400) {
746 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", address);
747 return;
748 }
749 addr_sz = 10;
750 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", address, byte);
751 break;
752 default:
753 Dbprintf("No or unknown card found, aborting");
754 return;
755 }
756
757 Dbprintf("integer value: %d address: %d addr_sz: %d", byte, address, addr_sz);
758 LED_B_ON();
759
760 setup_phase_reader(iv);
761
762 int r = legic_write_byte(byte, address, addr_sz);
763
764 if((r != 0) || BUTTON_PRESS()) {
765 Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index, r);
766 switch_off_tag_rwd();
767 LEDsoff();
768 return;
769 }
770
771 LEDsoff();
772 if ( MF_DBGLEVEL >= 1) DbpString("write successful");
773 }
774
775 void LegicRfInfo(void){
776
777 LegicCommonInit();
778 uint32_t tag_type = setup_phase_reader(0x55);
779 uint8_t cmd_sz = 0;
780 uint16_t card_sz = 0;
781
782 switch(tag_type) {
783 case 0x0d:
784 cmd_sz = 6;
785 card_sz = 22;
786 break;
787 case 0x1d:
788 cmd_sz = 9;
789 card_sz = 256;
790 break;
791 case 0x3d:
792 cmd_sz = 11;
793 card_sz = 1024;
794 break;
795 default:
796 cmd_send(CMD_ACK,0,0,0,0,0);
797 goto OUT;
798 }
799
800 // read UID bytes.
801 uint8_t uid[] = {0,0,0,0};
802 for ( uint8_t i = 0; i < sizeof(uid); ++i) {
803 int r = legic_read_byte(i, cmd_sz);
804 if ( r == -1 ) {
805 cmd_send(CMD_ACK,0,0,0,0,0);
806 goto OUT;
807 }
808 uid[i] = r & 0xFF;
809 }
810
811 cmd_send(CMD_ACK,1,card_sz,0,uid,sizeof(uid));
812 OUT:
813 switch_off_tag_rwd();
814 LEDsoff();
815
816 }
817
818 /* Handle (whether to respond) a frame in tag mode
819 * Only called when simulating a tag.
820 */
821 static void frame_handle_tag(struct legic_frame const * const f)
822 {
823 uint8_t *BigBuf = BigBuf_get_addr();
824
825 /* First Part of Handshake (IV) */
826 if(f->bits == 7) {
827
828 LED_C_ON();
829
830 // Reset prng timer
831 ResetTimer(prng_timer);
832
833 legic_prng_init(f->data);
834 frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1B */
835 legic_state = STATE_IV;
836 legic_read_count = 0;
837 legic_prng_bc = 0;
838 legic_prng_iv = f->data;
839
840
841 ResetTimer(timer);
842 WaitUS(280);
843 return;
844 }
845
846 /* 0x19==??? */
847 if(legic_state == STATE_IV) {
848 int local_key = get_key_stream(3, 6);
849 int xored = 0x39 ^ local_key;
850 if((f->bits == 6) && (f->data == xored)) {
851 legic_state = STATE_CON;
852
853 ResetTimer(timer);
854 WaitUS(200);
855 return;
856
857 } else {
858 legic_state = STATE_DISCON;
859 LED_C_OFF();
860 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
861 return;
862 }
863 }
864
865 /* Read */
866 if(f->bits == 11) {
867 if(legic_state == STATE_CON) {
868 int key = get_key_stream(2, 11); //legic_phase_drift, 11);
869 int addr = f->data ^ key; addr = addr >> 1;
870 int data = BigBuf[addr];
871 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
872 BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr;
873 legic_read_count++;
874
875 //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
876 legic_prng_forward(legic_reqresp_drift);
877
878 frame_send_tag(hash | data, 12, 1);
879
880 ResetTimer(timer);
881 legic_prng_forward(2);
882 WaitUS(180);
883 return;
884 }
885 }
886
887 /* Write */
888 if(f->bits == 23) {
889 int key = get_key_stream(-1, 23); //legic_frame_drift, 23);
890 int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;
891 int data = f->data ^ key; data = data >> 11; data = data & 0xff;
892
893 /* write command */
894 legic_state = STATE_DISCON;
895 LED_C_OFF();
896 Dbprintf("write - addr: %x, data: %x", addr, data);
897 return;
898 }
899
900 if(legic_state != STATE_DISCON) {
901 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
902 int i;
903 Dbprintf("IV: %03.3x", legic_prng_iv);
904 for(i = 0; i<legic_read_count; i++) {
905 Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]);
906 }
907
908 for(i = -1; i<legic_read_count; i++) {
909 uint32_t t;
910 t = BigBuf[OFFSET_LOG+256+i*4];
911 t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8;
912 t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16;
913 t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24;
914
915 Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
916 BigBuf[OFFSET_LOG+128+i],
917 BigBuf[OFFSET_LOG+384+i],
918 t);
919 }
920 }
921 legic_state = STATE_DISCON;
922 legic_read_count = 0;
923 SpinDelay(10);
924 LED_C_OFF();
925 return;
926 }
927
928 /* Read bit by bit untill full frame is received
929 * Call to process frame end answer
930 */
931 static void emit(int bit) {
932
933 switch (bit) {
934 case 1:
935 frame_append_bit(&current_frame, 1);
936 break;
937 case 0:
938 frame_append_bit(&current_frame, 0);
939 break;
940 default:
941 if(current_frame.bits <= 4) {
942 frame_clean(&current_frame);
943 } else {
944 frame_handle_tag(&current_frame);
945 frame_clean(&current_frame);
946 }
947 WDT_HIT();
948 break;
949 }
950 }
951
952 void LegicRfSimulate(int phase, int frame, int reqresp)
953 {
954 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
955 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
956 * envelope waveform on DIN and should send our response on DOUT.
957 *
958 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
959 * measure the time between two rising edges on DIN, and no encoding on the
960 * subcarrier from card to reader, so we'll just shift out our verbatim data
961 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
962 * seems to be 300us-ish.
963 */
964
965 legic_phase_drift = phase;
966 legic_frame_drift = frame;
967 legic_reqresp_drift = reqresp;
968
969 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
970 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
971 FpgaSetupSsc();
972 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
973
974 /* Bitbang the receiver */
975 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
976 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
977
978 //setup_timer();
979 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
980
981 int old_level = 0;
982 int active = 0;
983 legic_state = STATE_DISCON;
984
985 LED_B_ON();
986 DbpString("Starting Legic emulator, press button to end");
987
988 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
989 int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
990 int time = timer->TC_CV;
991
992 if(level != old_level) {
993 if(level == 1) {
994 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
995
996 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
997 /* 1 bit */
998 emit(1);
999 active = 1;
1000 LED_A_ON();
1001 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
1002 /* 0 bit */
1003 emit(0);
1004 active = 1;
1005 LED_A_ON();
1006 } else if (active) {
1007 /* invalid */
1008 emit(-1);
1009 active = 0;
1010 LED_A_OFF();
1011 }
1012 }
1013 }
1014
1015 /* Frame end */
1016 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
1017 emit(-1);
1018 active = 0;
1019 LED_A_OFF();
1020 }
1021
1022 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
1023 timer->TC_CCR = AT91C_TC_CLKDIS;
1024 }
1025
1026 old_level = level;
1027 WDT_HIT();
1028 }
1029 if ( MF_DBGLEVEL >= 1) DbpString("Stopped");
1030 LEDsoff();
1031 }
1032
1033 //-----------------------------------------------------------------------------
1034 // Code up a string of octets at layer 2 (including CRC, we don't generate
1035 // that here) so that they can be transmitted to the reader. Doesn't transmit
1036 // them yet, just leaves them ready to send in ToSend[].
1037 //-----------------------------------------------------------------------------
1038 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
1039 // {
1040 // int i;
1041
1042 // ToSendReset();
1043
1044 // // Transmit a burst of ones, as the initial thing that lets the
1045 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
1046 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
1047 // // so I will too.
1048 // for(i = 0; i < 20; i++) {
1049 // ToSendStuffBit(1);
1050 // ToSendStuffBit(1);
1051 // ToSendStuffBit(1);
1052 // ToSendStuffBit(1);
1053 // }
1054
1055 // // Send SOF.
1056 // for(i = 0; i < 10; i++) {
1057 // ToSendStuffBit(0);
1058 // ToSendStuffBit(0);
1059 // ToSendStuffBit(0);
1060 // ToSendStuffBit(0);
1061 // }
1062 // for(i = 0; i < 2; i++) {
1063 // ToSendStuffBit(1);
1064 // ToSendStuffBit(1);
1065 // ToSendStuffBit(1);
1066 // ToSendStuffBit(1);
1067 // }
1068
1069 // for(i = 0; i < len; i++) {
1070 // int j;
1071 // uint8_t b = cmd[i];
1072
1073 // // Start bit
1074 // ToSendStuffBit(0);
1075 // ToSendStuffBit(0);
1076 // ToSendStuffBit(0);
1077 // ToSendStuffBit(0);
1078
1079 // // Data bits
1080 // for(j = 0; j < 8; j++) {
1081 // if(b & 1) {
1082 // ToSendStuffBit(1);
1083 // ToSendStuffBit(1);
1084 // ToSendStuffBit(1);
1085 // ToSendStuffBit(1);
1086 // } else {
1087 // ToSendStuffBit(0);
1088 // ToSendStuffBit(0);
1089 // ToSendStuffBit(0);
1090 // ToSendStuffBit(0);
1091 // }
1092 // b >>= 1;
1093 // }
1094
1095 // // Stop bit
1096 // ToSendStuffBit(1);
1097 // ToSendStuffBit(1);
1098 // ToSendStuffBit(1);
1099 // ToSendStuffBit(1);
1100 // }
1101
1102 // // Send EOF.
1103 // for(i = 0; i < 10; i++) {
1104 // ToSendStuffBit(0);
1105 // ToSendStuffBit(0);
1106 // ToSendStuffBit(0);
1107 // ToSendStuffBit(0);
1108 // }
1109 // for(i = 0; i < 2; i++) {
1110 // ToSendStuffBit(1);
1111 // ToSendStuffBit(1);
1112 // ToSendStuffBit(1);
1113 // ToSendStuffBit(1);
1114 // }
1115
1116 // // Convert from last byte pos to length
1117 // ToSendMax++;
1118 // }
1119
1120 //-----------------------------------------------------------------------------
1121 // The software UART that receives commands from the reader, and its state
1122 // variables.
1123 //-----------------------------------------------------------------------------
1124 /*
1125 static struct {
1126 enum {
1127 STATE_UNSYNCD,
1128 STATE_GOT_FALLING_EDGE_OF_SOF,
1129 STATE_AWAITING_START_BIT,
1130 STATE_RECEIVING_DATA
1131 } state;
1132 uint16_t shiftReg;
1133 int bitCnt;
1134 int byteCnt;
1135 int byteCntMax;
1136 int posCnt;
1137 uint8_t *output;
1138 } Uart;
1139 */
1140 /* Receive & handle a bit coming from the reader.
1141 *
1142 * This function is called 4 times per bit (every 2 subcarrier cycles).
1143 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1144 *
1145 * LED handling:
1146 * LED A -> ON once we have received the SOF and are expecting the rest.
1147 * LED A -> OFF once we have received EOF or are in error state or unsynced
1148 *
1149 * Returns: true if we received a EOF
1150 * false if we are still waiting for some more
1151 */
1152 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1153 // {
1154 // switch(Uart.state) {
1155 // case STATE_UNSYNCD:
1156 // if(!bit) {
1157 // // we went low, so this could be the beginning of an SOF
1158 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1159 // Uart.posCnt = 0;
1160 // Uart.bitCnt = 0;
1161 // }
1162 // break;
1163
1164 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1165 // Uart.posCnt++;
1166 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1167 // if(bit) {
1168 // if(Uart.bitCnt > 9) {
1169 // // we've seen enough consecutive
1170 // // zeros that it's a valid SOF
1171 // Uart.posCnt = 0;
1172 // Uart.byteCnt = 0;
1173 // Uart.state = STATE_AWAITING_START_BIT;
1174 // LED_A_ON(); // Indicate we got a valid SOF
1175 // } else {
1176 // // didn't stay down long enough
1177 // // before going high, error
1178 // Uart.state = STATE_UNSYNCD;
1179 // }
1180 // } else {
1181 // // do nothing, keep waiting
1182 // }
1183 // Uart.bitCnt++;
1184 // }
1185 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1186 // if(Uart.bitCnt > 12) {
1187 // // Give up if we see too many zeros without
1188 // // a one, too.
1189 // LED_A_OFF();
1190 // Uart.state = STATE_UNSYNCD;
1191 // }
1192 // break;
1193
1194 // case STATE_AWAITING_START_BIT:
1195 // Uart.posCnt++;
1196 // if(bit) {
1197 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1198 // // stayed high for too long between
1199 // // characters, error
1200 // Uart.state = STATE_UNSYNCD;
1201 // }
1202 // } else {
1203 // // falling edge, this starts the data byte
1204 // Uart.posCnt = 0;
1205 // Uart.bitCnt = 0;
1206 // Uart.shiftReg = 0;
1207 // Uart.state = STATE_RECEIVING_DATA;
1208 // }
1209 // break;
1210
1211 // case STATE_RECEIVING_DATA:
1212 // Uart.posCnt++;
1213 // if(Uart.posCnt == 2) {
1214 // // time to sample a bit
1215 // Uart.shiftReg >>= 1;
1216 // if(bit) {
1217 // Uart.shiftReg |= 0x200;
1218 // }
1219 // Uart.bitCnt++;
1220 // }
1221 // if(Uart.posCnt >= 4) {
1222 // Uart.posCnt = 0;
1223 // }
1224 // if(Uart.bitCnt == 10) {
1225 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1226 // {
1227 // // this is a data byte, with correct
1228 // // start and stop bits
1229 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1230 // Uart.byteCnt++;
1231
1232 // if(Uart.byteCnt >= Uart.byteCntMax) {
1233 // // Buffer overflowed, give up
1234 // LED_A_OFF();
1235 // Uart.state = STATE_UNSYNCD;
1236 // } else {
1237 // // so get the next byte now
1238 // Uart.posCnt = 0;
1239 // Uart.state = STATE_AWAITING_START_BIT;
1240 // }
1241 // } else if (Uart.shiftReg == 0x000) {
1242 // // this is an EOF byte
1243 // LED_A_OFF(); // Finished receiving
1244 // Uart.state = STATE_UNSYNCD;
1245 // if (Uart.byteCnt != 0) {
1246 // return TRUE;
1247 // }
1248 // } else {
1249 // // this is an error
1250 // LED_A_OFF();
1251 // Uart.state = STATE_UNSYNCD;
1252 // }
1253 // }
1254 // break;
1255
1256 // default:
1257 // LED_A_OFF();
1258 // Uart.state = STATE_UNSYNCD;
1259 // break;
1260 // }
1261
1262 // return FALSE;
1263 // }
1264 /*
1265
1266 static void UartReset() {
1267 Uart.byteCntMax = 3;
1268 Uart.state = STATE_UNSYNCD;
1269 Uart.byteCnt = 0;
1270 Uart.bitCnt = 0;
1271 Uart.posCnt = 0;
1272 memset(Uart.output, 0x00, 3);
1273 }
1274 */
1275 // static void UartInit(uint8_t *data) {
1276 // Uart.output = data;
1277 // UartReset();
1278 // }
1279
1280 //=============================================================================
1281 // An LEGIC reader. We take layer two commands, code them
1282 // appropriately, and then send them to the tag. We then listen for the
1283 // tag's response, which we leave in the buffer to be demodulated on the
1284 // PC side.
1285 //=============================================================================
1286 /*
1287 static struct {
1288 enum {
1289 DEMOD_UNSYNCD,
1290 DEMOD_PHASE_REF_TRAINING,
1291 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1292 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1293 DEMOD_AWAITING_START_BIT,
1294 DEMOD_RECEIVING_DATA
1295 } state;
1296 int bitCount;
1297 int posCount;
1298 int thisBit;
1299 uint16_t shiftReg;
1300 uint8_t *output;
1301 int len;
1302 int sumI;
1303 int sumQ;
1304 } Demod;
1305 */
1306 /*
1307 * Handles reception of a bit from the tag
1308 *
1309 * This function is called 2 times per bit (every 4 subcarrier cycles).
1310 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1311 *
1312 * LED handling:
1313 * LED C -> ON once we have received the SOF and are expecting the rest.
1314 * LED C -> OFF once we have received EOF or are unsynced
1315 *
1316 * Returns: true if we received a EOF
1317 * false if we are still waiting for some more
1318 *
1319 */
1320
1321 /*
1322 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1323 {
1324 int v = 0;
1325 int ai = ABS(ci);
1326 int aq = ABS(cq);
1327 int halfci = (ai >> 1);
1328 int halfcq = (aq >> 1);
1329
1330 switch(Demod.state) {
1331 case DEMOD_UNSYNCD:
1332
1333 CHECK_FOR_SUBCARRIER()
1334
1335 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1336 Demod.state = DEMOD_PHASE_REF_TRAINING;
1337 Demod.sumI = ci;
1338 Demod.sumQ = cq;
1339 Demod.posCount = 1;
1340 }
1341 break;
1342
1343 case DEMOD_PHASE_REF_TRAINING:
1344 if(Demod.posCount < 8) {
1345
1346 CHECK_FOR_SUBCARRIER()
1347
1348 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1349 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1350 // note: synchronization time > 80 1/fs
1351 Demod.sumI += ci;
1352 Demod.sumQ += cq;
1353 ++Demod.posCount;
1354 } else {
1355 // subcarrier lost
1356 Demod.state = DEMOD_UNSYNCD;
1357 }
1358 } else {
1359 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1360 }
1361 break;
1362
1363 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1364
1365 MAKE_SOFT_DECISION()
1366
1367 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1368 // logic '0' detected
1369 if (v <= 0) {
1370
1371 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1372
1373 // start of SOF sequence
1374 Demod.posCount = 0;
1375 } else {
1376 // maximum length of TR1 = 200 1/fs
1377 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1378 }
1379 ++Demod.posCount;
1380 break;
1381
1382 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1383 ++Demod.posCount;
1384
1385 MAKE_SOFT_DECISION()
1386
1387 if(v > 0) {
1388 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1389 if(Demod.posCount < 10*2) {
1390 Demod.state = DEMOD_UNSYNCD;
1391 } else {
1392 LED_C_ON(); // Got SOF
1393 Demod.state = DEMOD_AWAITING_START_BIT;
1394 Demod.posCount = 0;
1395 Demod.len = 0;
1396 }
1397 } else {
1398 // low phase of SOF too long (> 12 etu)
1399 if(Demod.posCount > 13*2) {
1400 Demod.state = DEMOD_UNSYNCD;
1401 LED_C_OFF();
1402 }
1403 }
1404 break;
1405
1406 case DEMOD_AWAITING_START_BIT:
1407 ++Demod.posCount;
1408
1409 MAKE_SOFT_DECISION()
1410
1411 if(v > 0) {
1412 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1413 if(Demod.posCount > 3*2) {
1414 Demod.state = DEMOD_UNSYNCD;
1415 LED_C_OFF();
1416 }
1417 } else {
1418 // start bit detected
1419 Demod.bitCount = 0;
1420 Demod.posCount = 1; // this was the first half
1421 Demod.thisBit = v;
1422 Demod.shiftReg = 0;
1423 Demod.state = DEMOD_RECEIVING_DATA;
1424 }
1425 break;
1426
1427 case DEMOD_RECEIVING_DATA:
1428
1429 MAKE_SOFT_DECISION()
1430
1431 if(Demod.posCount == 0) {
1432 // first half of bit
1433 Demod.thisBit = v;
1434 Demod.posCount = 1;
1435 } else {
1436 // second half of bit
1437 Demod.thisBit += v;
1438 Demod.shiftReg >>= 1;
1439 // logic '1'
1440 if(Demod.thisBit > 0)
1441 Demod.shiftReg |= 0x200;
1442
1443 ++Demod.bitCount;
1444
1445 if(Demod.bitCount == 10) {
1446
1447 uint16_t s = Demod.shiftReg;
1448
1449 if((s & 0x200) && !(s & 0x001)) {
1450 // stop bit == '1', start bit == '0'
1451 uint8_t b = (s >> 1);
1452 Demod.output[Demod.len] = b;
1453 ++Demod.len;
1454 Demod.state = DEMOD_AWAITING_START_BIT;
1455 } else {
1456 Demod.state = DEMOD_UNSYNCD;
1457 LED_C_OFF();
1458
1459 if(s == 0x000) {
1460 // This is EOF (start, stop and all data bits == '0'
1461 return TRUE;
1462 }
1463 }
1464 }
1465 Demod.posCount = 0;
1466 }
1467 break;
1468
1469 default:
1470 Demod.state = DEMOD_UNSYNCD;
1471 LED_C_OFF();
1472 break;
1473 }
1474 return FALSE;
1475 }
1476 */
1477 /*
1478 // Clear out the state of the "UART" that receives from the tag.
1479 static void DemodReset() {
1480 Demod.len = 0;
1481 Demod.state = DEMOD_UNSYNCD;
1482 Demod.posCount = 0;
1483 Demod.sumI = 0;
1484 Demod.sumQ = 0;
1485 Demod.bitCount = 0;
1486 Demod.thisBit = 0;
1487 Demod.shiftReg = 0;
1488 memset(Demod.output, 0x00, 3);
1489 }
1490
1491 static void DemodInit(uint8_t *data) {
1492 Demod.output = data;
1493 DemodReset();
1494 }
1495 */
1496
1497 /*
1498 * Demodulate the samples we received from the tag, also log to tracebuffer
1499 * quiet: set to 'TRUE' to disable debug output
1500 */
1501
1502 /*
1503 #define LEGIC_DMA_BUFFER_SIZE 256
1504
1505 static void GetSamplesForLegicDemod(int n, bool quiet)
1506 {
1507 int max = 0;
1508 bool gotFrame = FALSE;
1509 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1510 int ci, cq, samples = 0;
1511
1512 BigBuf_free();
1513
1514 // And put the FPGA in the appropriate mode
1515 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1516
1517 // The response (tag -> reader) that we're receiving.
1518 // Set up the demodulator for tag -> reader responses.
1519 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1520
1521 // The DMA buffer, used to stream samples from the FPGA
1522 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1523 int8_t *upTo = dmaBuf;
1524
1525 // Setup and start DMA.
1526 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1527 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1528 return;
1529 }
1530
1531 // Signal field is ON with the appropriate LED:
1532 LED_D_ON();
1533 for(;;) {
1534 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1535 if(behindBy > max) max = behindBy;
1536
1537 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1538 ci = upTo[0];
1539 cq = upTo[1];
1540 upTo += 2;
1541 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1542 upTo = dmaBuf;
1543 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1544 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1545 }
1546 lastRxCounter -= 2;
1547 if(lastRxCounter <= 0)
1548 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1549
1550 samples += 2;
1551
1552 gotFrame = HandleLegicSamplesDemod(ci , cq );
1553 if ( gotFrame )
1554 break;
1555 }
1556
1557 if(samples > n || gotFrame)
1558 break;
1559 }
1560
1561 FpgaDisableSscDma();
1562
1563 if (!quiet && Demod.len == 0) {
1564 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1565 max,
1566 samples,
1567 gotFrame,
1568 Demod.len,
1569 Demod.sumI,
1570 Demod.sumQ
1571 );
1572 }
1573
1574 //Tracing
1575 if (Demod.len > 0) {
1576 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1577 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1578 }
1579 }
1580
1581 */
1582
1583 //-----------------------------------------------------------------------------
1584 // Transmit the command (to the tag) that was placed in ToSend[].
1585 //-----------------------------------------------------------------------------
1586 /*
1587 static void TransmitForLegic(void)
1588 {
1589 int c;
1590
1591 FpgaSetupSsc();
1592
1593 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1594 AT91C_BASE_SSC->SSC_THR = 0xff;
1595
1596 // Signal field is ON with the appropriate Red LED
1597 LED_D_ON();
1598
1599 // Signal we are transmitting with the Green LED
1600 LED_B_ON();
1601 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1602
1603 for(c = 0; c < 10;) {
1604 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1605 AT91C_BASE_SSC->SSC_THR = 0xff;
1606 c++;
1607 }
1608 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1609 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1610 (void)r;
1611 }
1612 WDT_HIT();
1613 }
1614
1615 c = 0;
1616 for(;;) {
1617 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1618 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1619 legic_prng_forward(1); // forward the lfsr
1620 c++;
1621 if(c >= ToSendMax) {
1622 break;
1623 }
1624 }
1625 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1626 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1627 (void)r;
1628 }
1629 WDT_HIT();
1630 }
1631 LED_B_OFF();
1632 }
1633 */
1634
1635 //-----------------------------------------------------------------------------
1636 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1637 // so that it is ready to transmit to the tag using TransmitForLegic().
1638 //-----------------------------------------------------------------------------
1639 /*
1640 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1641 {
1642 int i, j;
1643 uint8_t b;
1644
1645 ToSendReset();
1646
1647 // Send SOF
1648 for(i = 0; i < 7; i++)
1649 ToSendStuffBit(1);
1650
1651
1652 for(i = 0; i < cmdlen; i++) {
1653 // Start bit
1654 ToSendStuffBit(0);
1655
1656 // Data bits
1657 b = cmd[i];
1658 for(j = 0; j < bits; j++) {
1659 if(b & 1) {
1660 ToSendStuffBit(1);
1661 } else {
1662 ToSendStuffBit(0);
1663 }
1664 b >>= 1;
1665 }
1666 }
1667
1668 // Convert from last character reference to length
1669 ++ToSendMax;
1670 }
1671 */
1672 /**
1673 Convenience function to encode, transmit and trace Legic comms
1674 **/
1675 /*
1676 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1677 {
1678 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1679 TransmitForLegic();
1680 if (tracing) {
1681 uint8_t parity[1] = {0x00};
1682 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1683 }
1684 }
1685
1686 */
1687 // Set up LEGIC communication
1688 /*
1689 void ice_legic_setup() {
1690
1691 // standard things.
1692 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1693 BigBuf_free(); BigBuf_Clear_ext(false);
1694 clear_trace();
1695 set_tracing(TRUE);
1696 DemodReset();
1697 UartReset();
1698
1699 // Set up the synchronous serial port
1700 FpgaSetupSsc();
1701
1702 // connect Demodulated Signal to ADC:
1703 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1704
1705 // Signal field is on with the appropriate LED
1706 LED_D_ON();
1707 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1708 SpinDelay(20);
1709 // Start the timer
1710 //StartCountSspClk();
1711
1712 // initalize CRC
1713 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1714
1715 // initalize prng
1716 legic_prng_init(0);
1717 }
1718 */
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