cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/hi_read_rx_xcorr.v

   1 //-----------------------------------------------------------------------------
   2 //
   3 // Jonathan Westhues, April 2006
   4 //-----------------------------------------------------------------------------
   5
   6 module hi_read_rx_xcorr(
   7     pck0, ck_1356meg, ck_1356megb,
   8     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
   9     adc_d, adc_clk,
  10     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  11     cross_hi, cross_lo,
  12     dbg,
  13     xcorr_is_848, snoop, xcorr_quarter_freq
  14 );
  15     input pck0, ck_1356meg, ck_1356megb;
  16     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  17     input [7:0] adc_d;
  18     output adc_clk;
  19     input ssp_dout;
  20     output ssp_frame, ssp_din, ssp_clk;
  21     input cross_hi, cross_lo;
  22     output dbg;
  23     input xcorr_is_848, snoop, xcorr_quarter_freq;
  24
  25 // Carrier is steady on through this, unless we're snooping.
  26 assign pwr_hi = ck_1356megb & (~snoop);
  27 assign pwr_oe1 = 1'b0;
  28 assign pwr_oe2 = 1'b0;
  29 assign pwr_oe3 = 1'b0;
  30 assign pwr_oe4 = 1'b0;
  31
  32 reg ssp_clk;
  33 reg ssp_frame;
  34
  35 reg fc_div_2;
  36 always @(posedge ck_1356meg)
  37     fc_div_2 = ~fc_div_2;
  38
  39 reg fc_div_4;
  40 always @(posedge fc_div_2)
  41     fc_div_4 = ~fc_div_4;
  42
  43 reg fc_div_8;
  44 always @(posedge fc_div_4)
  45     fc_div_8 = ~fc_div_8;
  46
  47 reg adc_clk;
  48
  49 always @(xcorr_is_848 or xcorr_quarter_freq or ck_1356meg)
  50     if(~xcorr_quarter_freq)
  51     begin
  52             if(xcorr_is_848)
  53                 // The subcarrier frequency is fc/16; we will sample at fc, so that
  54                 // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...
  55                 adc_clk <= ck_1356meg;
  56             else
  57                 // The subcarrier frequency is fc/32; we will sample at fc/2, and
  58                 // the subcarrier will look identical.
  59                 adc_clk <= fc_div_2;
  60     end
  61     else
  62     begin
  63             if(xcorr_is_848)
  64                 // The subcarrier frequency is fc/64
  65                 adc_clk <= fc_div_4;
  66             else
  67                 // The subcarrier frequency is fc/128
  68                 adc_clk <= fc_div_8;
  69         end
  70
  71 // When we're a reader, we just need to do the BPSK demod; but when we're an
  72 // eavesdropper, we also need to pick out the commands sent by the reader,
  73 // using AM. Do this the same way that we do it for the simulated tag.
  74 reg after_hysteresis, after_hysteresis_prev;
  75 reg [11:0] has_been_low_for;
  76 always @(negedge adc_clk)
  77 begin
  78     if(& adc_d[7:0]) after_hysteresis <= 1'b1;
  79     else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
  80
  81     if(after_hysteresis)
  82     begin
  83         has_been_low_for <= 7'b0;
  84     end
  85     else
  86     begin
  87         if(has_been_low_for == 12'd4095)
  88         begin
  89             has_been_low_for <= 12'd0;
  90             after_hysteresis <= 1'b1;
  91         end
  92         else
  93             has_been_low_for <= has_been_low_for + 1;
  94     end
  95 end
  96
  97 // Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
  98 // so we need a 6-bit counter.
  99 reg [5:0] corr_i_cnt;
 100 reg [5:0] corr_q_cnt;
 101 // And a couple of registers in which to accumulate the correlations.
 102 // we would add at most 32 times adc_d, the result can be held in 13 bits.
 103 // Need one additional bit because it can be negative as well
 104 reg signed [13:0] corr_i_accum;
 105 reg signed [13:0] corr_q_accum;
 106 reg signed [7:0] corr_i_out;
 107 reg signed [7:0] corr_q_out;
 108
 109 // ADC data appears on the rising edge, so sample it on the falling edge
 110 always @(negedge adc_clk)
 111 begin
 112     // These are the correlators: we correlate against in-phase and quadrature
 113     // versions of our reference signal, and keep the (signed) result to
 114     // send out later over the SSP.
 115     if(corr_i_cnt == 7'd63)
 116     begin
 117         if(snoop)
 118         begin
 119                         // highest 7 significant bits of tag signal (signed), 1 bit reader signal:
 120             corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev};
 121             corr_q_out <= {corr_q_accum[13:7], after_hysteresis};
 122         end
 123         else
 124         begin
 125             // highest 8 significant bits of tag signal
 126             corr_i_out <= corr_i_accum[13:6];
 127             corr_q_out <= corr_q_accum[13:6];
 128         end
 129
 130         corr_i_accum <= adc_d;
 131         corr_q_accum <= adc_d;
 132         corr_q_cnt <= 4;
 133         corr_i_cnt <= 0;
 134     end
 135     else
 136     begin
 137         if(corr_i_cnt[3])
 138             corr_i_accum <= corr_i_accum - adc_d;
 139         else
 140             corr_i_accum <= corr_i_accum + adc_d;
 141
 142         if(corr_q_cnt[3])
 143             corr_q_accum <= corr_q_accum - adc_d;
 144         else
 145             corr_q_accum <= corr_q_accum + adc_d;
 146
 147         corr_i_cnt <= corr_i_cnt + 1;
 148         corr_q_cnt <= corr_q_cnt + 1;
 149     end
 150
 151     // The logic in hi_simulate.v reports 4 samples per bit. We report two
 152     // (I, Q) pairs per bit, so we should do 2 samples per pair.
 153     if(corr_i_cnt == 6'd31)
 154         after_hysteresis_prev <= after_hysteresis;
 155
 156     // Then the result from last time is serialized and send out to the ARM.
 157     // We get one report each cycle, and each report is 16 bits, so the
 158     // ssp_clk should be the adc_clk divided by 64/16 = 4.
 159
 160     if(corr_i_cnt[1:0] == 2'b10)
 161         ssp_clk <= 1'b0;
 162
 163     if(corr_i_cnt[1:0] == 2'b00)
 164     begin
 165         ssp_clk <= 1'b1;
 166         // Don't shift if we just loaded new data, obviously.
 167         if(corr_i_cnt != 7'd0)
 168         begin
 169             corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
 170             corr_q_out[7:1] <= corr_q_out[6:0];
 171         end
 172     end
 173
 174     if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)
 175         ssp_frame = 1'b1;
 176     else
 177         ssp_frame = 1'b0;
 178
 179 end
 180
 181 assign ssp_din = corr_i_out[7];
 182
 183 assign dbg = corr_i_cnt[3];
 184
 185 // Unused.
 186 assign pwr_lo = 1'b0;
 187
 188 endmodule